drivers/usb/musb/musbhsdma.c

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33 #include <linux/device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/slab.h>
  37 #include "musb_core.h"
  38 #include "musbhsdma.h"
  39
  40 static int dma_controller_start(struct dma_controller *c)
  41 {
  42         /* nothing to do */
  43         return 0;
  44 }
  45
  46 static void dma_channel_release(struct dma_channel *channel);
  47
  48 static int dma_controller_stop(struct dma_controller *c)
  49 {
  50         struct musb_dma_controller *controller = container_of(c,
  51                         struct musb_dma_controller, controller);
  52         struct musb *musb = controller->private_data;
  53         struct dma_channel *channel;
  54         u8 bit;
  55
  56         if (controller->used_channels != 0) {
  57                 dev_err(musb->controller,
  58                         "Stopping DMA controller while channel active\n");
  59
  60                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  61                         if (controller->used_channels & (1 << bit)) {
  62                                 channel = &controller->channel[bit].channel;
  63                                 dma_channel_release(channel);
  64
  65                                 if (!controller->used_channels)
  66                                         break;
  67                         }
  68                 }
  69         }
  70
  71         return 0;
  72 }
  73
  74 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  75                                 struct musb_hw_ep *hw_ep, u8 transmit)
  76 {
  77         struct musb_dma_controller *controller = container_of(c,
  78                         struct musb_dma_controller, controller);
  79         struct musb_dma_channel *musb_channel = NULL;
  80         struct dma_channel *channel = NULL;
  81         u8 bit;
  82
  83         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  84                 if (!(controller->used_channels & (1 << bit))) {
  85                         controller->used_channels |= (1 << bit);
  86                         musb_channel = &(controller->channel[bit]);
  87                         musb_channel->controller = controller;
  88                         musb_channel->idx = bit;
  89                         musb_channel->epnum = hw_ep->epnum;
  90                         musb_channel->transmit = transmit;
  91                         channel = &(musb_channel->channel);
  92                         channel->private_data = musb_channel;
  93                         channel->status = MUSB_DMA_STATUS_FREE;
  94                         channel->max_len = 0x100000;
  95                         /* Tx => mode 1; Rx => mode 0 */
  96                         channel->desired_mode = transmit;
  97                         channel->actual_len = 0;
  98                         break;
  99                 }
 100         }
 101
 102         return channel;
 103 }
 104
 105 static void dma_channel_release(struct dma_channel *channel)
 106 {
 107         struct musb_dma_channel *musb_channel = channel->private_data;
 108
 109         channel->actual_len = 0;
 110         musb_channel->start_addr = 0;
 111         musb_channel->len = 0;
 112
 113         musb_channel->controller->used_channels &=
 114                 ~(1 << musb_channel->idx);
 115
 116         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 117 }
 118
 119 static void configure_channel(struct dma_channel *channel,
 120                                 u16 packet_sz, u8 mode,
 121                                 dma_addr_t dma_addr, u32 len)
 122 {
 123         struct musb_dma_channel *musb_channel = channel->private_data;
 124         struct musb_dma_controller *controller = musb_channel->controller;
 125         void __iomem *mbase = controller->base;
 126         u8 bchannel = musb_channel->idx;
 127         u16 csr = 0;
 128
 129         DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
 130                         channel, packet_sz, dma_addr, len, mode);
 131
 132         if (mode) {
 133                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 134                 BUG_ON(len < packet_sz);
 135         }
 136         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 137                                 << MUSB_HSDMA_BURSTMODE_SHIFT;
 138
 139         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 140                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 141                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 142                 | (musb_channel->transmit
 143                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 144                                 : 0);
 145
 146         /* address/count */
 147         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 148         musb_write_hsdma_count(mbase, bchannel, len);
 149
 150         /* control (this should start things) */
 151         musb_writew(mbase,
 152                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 153                 csr);
 154 }
 155
 156 static int dma_channel_program(struct dma_channel *channel,
 157                                 u16 packet_sz, u8 mode,
 158                                 dma_addr_t dma_addr, u32 len)
 159 {
 160         struct musb_dma_channel *musb_channel = channel->private_data;
 161         struct musb_dma_controller *controller = musb_channel->controller;
 162         struct musb *musb = controller->private_data;
 163
 164         DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 165                 musb_channel->epnum,
 166                 musb_channel->transmit ? "Tx" : "Rx",
 167                 packet_sz, dma_addr, len, mode);
 168
 169         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 170                 channel->status == MUSB_DMA_STATUS_BUSY);
 171
 172         /* Let targets check/tweak the arguments */
 173         if (musb->ops->adjust_channel_params) {
 174                 int ret = musb->ops->adjust_channel_params(channel,
 175                         packet_sz, &mode, &dma_addr, &len);
 176                 if (ret)
 177                         return ret;
 178         }
 179
 180         /*
 181          * The DMA engine in RTL1.8 and above cannot handle
 182          * DMA addresses that are not aligned to a 4 byte boundary.
 183          * It ends up masking the last two bits of the address
 184          * programmed in DMA_ADDR.
 185          *
 186          * Fail such DMA transfers, so that the backup PIO mode
 187          * can carry out the transfer
 188          */
 189         if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
 190                 return false;
 191
 192         channel->actual_len = 0;
 193         musb_channel->start_addr = dma_addr;
 194         musb_channel->len = len;
 195         musb_channel->max_packet_sz = packet_sz;
 196         channel->status = MUSB_DMA_STATUS_BUSY;
 197
 198         configure_channel(channel, packet_sz, mode, dma_addr, len);
 199
 200         return true;
 201 }
 202
 203 static int dma_channel_abort(struct dma_channel *channel)
 204 {
 205         struct musb_dma_channel *musb_channel = channel->private_data;
 206         void __iomem *mbase = musb_channel->controller->base;
 207
 208         u8 bchannel = musb_channel->idx;
 209         int offset;
 210         u16 csr;
 211
 212         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 213                 if (musb_channel->transmit) {
 214                         offset = MUSB_EP_OFFSET(musb_channel->epnum,
 215                                                 MUSB_TXCSR);
 216
 217                         /*
 218                          * The programming guide says that we must clear
 219                          * the DMAENAB bit before the DMAMODE bit...
 220                          */
 221                         csr = musb_readw(mbase, offset);
 222                         csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
 223                         musb_writew(mbase, offset, csr);
 224                         csr &= ~MUSB_TXCSR_DMAMODE;
 225                         musb_writew(mbase, offset, csr);
 226                 } else {
 227                         offset = MUSB_EP_OFFSET(musb_channel->epnum,
 228                                                 MUSB_RXCSR);
 229
 230                         csr = musb_readw(mbase, offset);
 231                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 232                                  MUSB_RXCSR_DMAENAB |
 233                                  MUSB_RXCSR_DMAMODE);
 234                         musb_writew(mbase, offset, csr);
 235                 }
 236
 237                 musb_writew(mbase,
 238                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 239                         0);
 240                 musb_write_hsdma_addr(mbase, bchannel, 0);
 241                 musb_write_hsdma_count(mbase, bchannel, 0);
 242                 channel->status = MUSB_DMA_STATUS_FREE;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 249 {
 250         struct musb_dma_controller *controller = private_data;
 251         struct musb *musb = controller->private_data;
 252         struct musb_dma_channel *musb_channel;
 253         struct dma_channel *channel;
 254
 255         void __iomem *mbase = controller->base;
 256
 257         irqreturn_t retval = IRQ_NONE;
 258
 259         unsigned long flags;
 260
 261         u8 bchannel;
 262         u8 int_hsdma;
 263
 264         u32 addr, count;
 265         u16 csr;
 266
 267         spin_lock_irqsave(&musb->lock, flags);
 268
 269         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 270
 271 #ifdef CONFIG_BLACKFIN
 272         /* Clear DMA interrupt flags */
 273         musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 274 #endif
 275
 276         if (!int_hsdma) {
 277                 DBG(2, "spurious DMA irq\n");
 278
 279                 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 280                         musb_channel = (struct musb_dma_channel *)
 281                                         &(controller->channel[bchannel]);
 282                         channel = &musb_channel->channel;
 283                         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 284                                 count = musb_read_hsdma_count(mbase, bchannel);
 285
 286                                 if (count == 0)
 287                                         int_hsdma |= (1 << bchannel);
 288                         }
 289                 }
 290
 291                 DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
 292
 293                 if (!int_hsdma)
 294                         goto done;
 295         }
 296
 297         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 298                 if (int_hsdma & (1 << bchannel)) {
 299                         musb_channel = (struct musb_dma_channel *)
 300                                         &(controller->channel[bchannel]);
 301                         channel = &musb_channel->channel;
 302
 303                         csr = musb_readw(mbase,
 304                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 305                                                         MUSB_HSDMA_CONTROL));
 306
 307                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 308                                 musb_channel->channel.status =
 309                                         MUSB_DMA_STATUS_BUS_ABORT;
 310                         } else {
 311                                 u8 devctl;
 312
 313                                 addr = musb_read_hsdma_addr(mbase,
 314                                                 bchannel);
 315                                 channel->actual_len = addr
 316                                         - musb_channel->start_addr;
 317
 318                                 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
 319                                         channel, musb_channel->start_addr,
 320                                         addr, channel->actual_len,
 321                                         musb_channel->len,
 322                                         (channel->actual_len
 323                                                 < musb_channel->len) ?
 324                                         "=> reconfig 0" : "=> complete");
 325
 326                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 327
 328                                 channel->status = MUSB_DMA_STATUS_FREE;
 329
 330                                 /* completed */
 331                                 if ((devctl & MUSB_DEVCTL_HM)
 332                                         && (musb_channel->transmit)
 333                                         && ((channel->desired_mode == 0)
 334                                             || (channel->actual_len &
 335                                             (musb_channel->max_packet_sz - 1)))
 336                                     ) {
 337                                         u8  epnum  = musb_channel->epnum;
 338                                         int offset = MUSB_EP_OFFSET(epnum,
 339                                                                     MUSB_TXCSR);
 340                                         u16 txcsr;
 341
 342                                         /*
 343                                          * The programming guide says that we
 344                                          * must clear DMAENAB before DMAMODE.
 345                                          */
 346                                         musb_ep_select(mbase, epnum);
 347                                         txcsr = musb_readw(mbase, offset);
 348                                         txcsr &= ~(MUSB_TXCSR_DMAENAB
 349                                                         | MUSB_TXCSR_AUTOSET);
 350                                         musb_writew(mbase, offset, txcsr);
 351                                         /* Send out the packet */
 352                                         txcsr &= ~MUSB_TXCSR_DMAMODE;
 353                                         txcsr |=  MUSB_TXCSR_TXPKTRDY;
 354                                         musb_writew(mbase, offset, txcsr);
 355                                 }
 356                                 musb_dma_completion(musb, musb_channel->epnum,
 357                                                     musb_channel->transmit);
 358                         }
 359                 }
 360         }
 361
 362         retval = IRQ_HANDLED;
 363 done:
 364         spin_unlock_irqrestore(&musb->lock, flags);
 365         return retval;
 366 }
 367
 368 void dma_controller_destroy(struct dma_controller *c)
 369 {
 370         struct musb_dma_controller *controller = container_of(c,
 371                         struct musb_dma_controller, controller);
 372
 373         if (!controller)
 374                 return;
 375
 376         if (controller->irq)
 377                 free_irq(controller->irq, c);
 378
 379         kfree(controller);
 380 }
 381
 382 struct dma_controller *__init
 383 dma_controller_create(struct musb *musb, void __iomem *base)
 384 {
 385         struct musb_dma_controller *controller;
 386         struct device *dev = musb->controller;
 387         struct platform_device *pdev = to_platform_device(dev);
 388         int irq = platform_get_irq_byname(pdev, "dma");
 389
 390         if (irq == 0) {
 391                 dev_err(dev, "No DMA interrupt line!\n");
 392                 return NULL;
 393         }
 394
 395         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 396         if (!controller)
 397                 return NULL;
 398
 399         controller->channel_count = MUSB_HSDMA_CHANNELS;
 400         controller->private_data = musb;
 401         controller->base = base;
 402
 403         controller->controller.start = dma_controller_start;
 404         controller->controller.stop = dma_controller_stop;
 405         controller->controller.channel_alloc = dma_channel_allocate;
 406         controller->controller.channel_release = dma_channel_release;
 407         controller->controller.channel_program = dma_channel_program;
 408         controller->controller.channel_abort = dma_channel_abort;
 409
 410         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
 411                         dev_name(musb->controller), &controller->controller)) {
 412                 dev_err(dev, "request_irq %d failed!\n", irq);
 413                 dma_controller_destroy(&controller->controller);
 414
 415                 return NULL;
 416         }
 417
 418         controller->irq = irq;
 419
 420         return &controller->controller;
 421 }