?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add linux-next specific files for 20110421
[linux-2.6/next.git] / sound / pci / hda / hda_intel.c
blob6f891ee82a7c9161e2332bfc73c1280d6268a14c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, int, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, CPT},"
129 "{Intel, PPT},"
130 "{Intel, PBG},"
131 "{Intel, SCH},"
132 "{ATI, SB450},"
133 "{ATI, SB600},"
134 "{ATI, RS600},"
135 "{ATI, RS690},"
136 "{ATI, RS780},"
137 "{ATI, R600},"
138 "{ATI, RV630},"
139 "{ATI, RV610},"
140 "{ATI, RV670},"
141 "{ATI, RV635},"
142 "{ATI, RV620},"
143 "{ATI, RV770},"
144 "{VIA, VT8251},"
145 "{VIA, VT8237A},"
146 "{SiS, SIS966},"
147 "{ULI, M5461}}");
148 MODULE_DESCRIPTION("Intel HDA driver");
149
150 #ifdef CONFIG_SND_VERBOSE_PRINTK
151 #define SFX /* nop */
152 #else
153 #define SFX "hda-intel: "
154 #endif
155
156 /*
157 * registers
158 */
159 #define ICH6_REG_GCAP 0x00
160 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
161 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
162 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
163 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
164 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
165 #define ICH6_REG_VMIN 0x02
166 #define ICH6_REG_VMAJ 0x03
167 #define ICH6_REG_OUTPAY 0x04
168 #define ICH6_REG_INPAY 0x06
169 #define ICH6_REG_GCTL 0x08
170 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
171 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
172 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
173 #define ICH6_REG_WAKEEN 0x0c
174 #define ICH6_REG_STATESTS 0x0e
175 #define ICH6_REG_GSTS 0x10
176 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
177 #define ICH6_REG_INTCTL 0x20
178 #define ICH6_REG_INTSTS 0x24
179 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
180 #define ICH6_REG_SYNC 0x34
181 #define ICH6_REG_CORBLBASE 0x40
182 #define ICH6_REG_CORBUBASE 0x44
183 #define ICH6_REG_CORBWP 0x48
184 #define ICH6_REG_CORBRP 0x4a
185 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
186 #define ICH6_REG_CORBCTL 0x4c
187 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
188 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
189 #define ICH6_REG_CORBSTS 0x4d
190 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
191 #define ICH6_REG_CORBSIZE 0x4e
192
193 #define ICH6_REG_RIRBLBASE 0x50
194 #define ICH6_REG_RIRBUBASE 0x54
195 #define ICH6_REG_RIRBWP 0x58
196 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
197 #define ICH6_REG_RINTCNT 0x5a
198 #define ICH6_REG_RIRBCTL 0x5c
199 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
200 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
201 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
202 #define ICH6_REG_RIRBSTS 0x5d
203 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
204 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
205 #define ICH6_REG_RIRBSIZE 0x5e
206
207 #define ICH6_REG_IC 0x60
208 #define ICH6_REG_IR 0x64
209 #define ICH6_REG_IRS 0x68
210 #define ICH6_IRS_VALID (1<<1)
211 #define ICH6_IRS_BUSY (1<<0)
212
213 #define ICH6_REG_DPLBASE 0x70
214 #define ICH6_REG_DPUBASE 0x74
215 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
216
217 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
218 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
219
220 /* stream register offsets from stream base */
221 #define ICH6_REG_SD_CTL 0x00
222 #define ICH6_REG_SD_STS 0x03
223 #define ICH6_REG_SD_LPIB 0x04
224 #define ICH6_REG_SD_CBL 0x08
225 #define ICH6_REG_SD_LVI 0x0c
226 #define ICH6_REG_SD_FIFOW 0x0e
227 #define ICH6_REG_SD_FIFOSIZE 0x10
228 #define ICH6_REG_SD_FORMAT 0x12
229 #define ICH6_REG_SD_BDLPL 0x18
230 #define ICH6_REG_SD_BDLPU 0x1c
231
232 /* PCI space */
233 #define ICH6_PCIREG_TCSEL 0x44
234
235 /*
236 * other constants
237 */
238
239 /* max number of SDs */
240 /* ICH, ATI and VIA have 4 playback and 4 capture */
241 #define ICH6_NUM_CAPTURE 4
242 #define ICH6_NUM_PLAYBACK 4
243
244 /* ULI has 6 playback and 5 capture */
245 #define ULI_NUM_CAPTURE 5
246 #define ULI_NUM_PLAYBACK 6
247
248 /* ATI HDMI has 1 playback and 0 capture */
249 #define ATIHDMI_NUM_CAPTURE 0
250 #define ATIHDMI_NUM_PLAYBACK 1
251
252 /* TERA has 4 playback and 3 capture */
253 #define TERA_NUM_CAPTURE 3
254 #define TERA_NUM_PLAYBACK 4
255
256 /* this number is statically defined for simplicity */
257 #define MAX_AZX_DEV 16
258
259 /* max number of fragments - we may use more if allocating more pages for BDL */
260 #define BDL_SIZE 4096
261 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
262 #define AZX_MAX_FRAG 32
263 /* max buffer size - no h/w limit, you can increase as you like */
264 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
265
266 /* RIRB int mask: overrun[2], response[0] */
267 #define RIRB_INT_RESPONSE 0x01
268 #define RIRB_INT_OVERRUN 0x04
269 #define RIRB_INT_MASK 0x05
270
271 /* STATESTS int mask: S3,SD2,SD1,SD0 */
272 #define AZX_MAX_CODECS 8
273 #define AZX_DEFAULT_CODECS 4
274 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
275
276 /* SD_CTL bits */
277 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
278 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
279 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
280 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
281 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
282 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
283 #define SD_CTL_STREAM_TAG_SHIFT 20
284
285 /* SD_CTL and SD_STS */
286 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
287 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
288 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
289 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
290 SD_INT_COMPLETE)
291
292 /* SD_STS */
293 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
294
295 /* INTCTL and INTSTS */
296 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
297 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
298 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
299
300 /* below are so far hardcoded - should read registers in future */
301 #define ICH6_MAX_CORB_ENTRIES 256
302 #define ICH6_MAX_RIRB_ENTRIES 256
303
304 /* position fix mode */
305 enum {
306 POS_FIX_AUTO,
307 POS_FIX_LPIB,
308 POS_FIX_POSBUF,
309 POS_FIX_VIACOMBO,
310 };
311
312 /* Defines for ATI HD Audio support in SB450 south bridge */
313 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
314 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
315
316 /* Defines for Nvidia HDA support */
317 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
318 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
319 #define NVIDIA_HDA_ISTRM_COH 0x4d
320 #define NVIDIA_HDA_OSTRM_COH 0x4c
321 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
322
323 /* Defines for Intel SCH HDA snoop control */
324 #define INTEL_SCH_HDA_DEVC 0x78
325 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
326
327 /* Define IN stream 0 FIFO size offset in VIA controller */
328 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
329 /* Define VIA HD Audio Device ID*/
330 #define VIA_HDAC_DEVICE_ID 0x3288
331
332 /* HD Audio class code */
333 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
334
335 /*
336 */
337
338 struct azx_dev {
339 struct snd_dma_buffer bdl; /* BDL buffer */
340 u32 *posbuf; /* position buffer pointer */
341
342 unsigned int bufsize; /* size of the play buffer in bytes */
343 unsigned int period_bytes; /* size of the period in bytes */
344 unsigned int frags; /* number for period in the play buffer */
345 unsigned int fifo_size; /* FIFO size */
346 unsigned long start_wallclk; /* start + minimum wallclk */
347 unsigned long period_wallclk; /* wallclk for period */
348
349 void __iomem *sd_addr; /* stream descriptor pointer */
350
351 u32 sd_int_sta_mask; /* stream int status mask */
352
353 /* pcm support */
354 struct snd_pcm_substream *substream; /* assigned substream,
355 * set in PCM open
356 */
357 unsigned int format_val; /* format value to be set in the
358 * controller and the codec
359 */
360 unsigned char stream_tag; /* assigned stream */
361 unsigned char index; /* stream index */
362 int device; /* last device number assigned to */
363
364 unsigned int opened :1;
365 unsigned int running :1;
366 unsigned int irq_pending :1;
367 /*
368 * For VIA:
369 * A flag to ensure DMA position is 0
370 * when link position is not greater than FIFO size
371 */
372 unsigned int insufficient :1;
373 };
374
375 /* CORB/RIRB */
376 struct azx_rb {
377 u32 *buf; /* CORB/RIRB buffer
378 * Each CORB entry is 4byte, RIRB is 8byte
379 */
380 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
381 /* for RIRB */
382 unsigned short rp, wp; /* read/write pointers */
383 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
384 u32 res[AZX_MAX_CODECS]; /* last read value */
385 };
386
387 struct azx {
388 struct snd_card *card;
389 struct pci_dev *pci;
390 int dev_index;
391
392 /* chip type specific */
393 int driver_type;
394 int playback_streams;
395 int playback_index_offset;
396 int capture_streams;
397 int capture_index_offset;
398 int num_streams;
399
400 /* pci resources */
401 unsigned long addr;
402 void __iomem *remap_addr;
403 int irq;
404
405 /* locks */
406 spinlock_t reg_lock;
407 struct mutex open_mutex;
408
409 /* streams (x num_streams) */
410 struct azx_dev *azx_dev;
411
412 /* PCM */
413 struct snd_pcm *pcm[HDA_MAX_PCMS];
414
415 /* HD codec */
416 unsigned short codec_mask;
417 int codec_probe_mask; /* copied from probe_mask option */
418 struct hda_bus *bus;
419 unsigned int beep_mode;
420
421 /* CORB/RIRB */
422 struct azx_rb corb;
423 struct azx_rb rirb;
424
425 /* CORB/RIRB and position buffers */
426 struct snd_dma_buffer rb;
427 struct snd_dma_buffer posbuf;
428
429 /* flags */
430 int position_fix[2]; /* for both playback/capture streams */
431 int poll_count;
432 unsigned int running :1;
433 unsigned int initialized :1;
434 unsigned int single_cmd :1;
435 unsigned int polling_mode :1;
436 unsigned int msi :1;
437 unsigned int irq_pending_warned :1;
438 unsigned int probing :1; /* codec probing phase */
439
440 /* for debugging */
441 unsigned int last_cmd[AZX_MAX_CODECS];
442
443 /* for pending irqs */
444 struct work_struct irq_pending_work;
445
446 /* reboot notifier (for mysterious hangup problem at power-down) */
447 struct notifier_block reboot_notifier;
448 };
449
450 /* driver types */
451 enum {
452 AZX_DRIVER_ICH,
453 AZX_DRIVER_PCH,
454 AZX_DRIVER_SCH,
455 AZX_DRIVER_ATI,
456 AZX_DRIVER_ATIHDMI,
457 AZX_DRIVER_VIA,
458 AZX_DRIVER_SIS,
459 AZX_DRIVER_ULI,
460 AZX_DRIVER_NVIDIA,
461 AZX_DRIVER_TERA,
462 AZX_DRIVER_CTX,
463 AZX_DRIVER_GENERIC,
464 AZX_NUM_DRIVERS, /* keep this as last entry */
465 };
466
467 static char *driver_short_names[] __devinitdata = {
468 [AZX_DRIVER_ICH] = "HDA Intel",
469 [AZX_DRIVER_PCH] = "HDA Intel PCH",
470 [AZX_DRIVER_SCH] = "HDA Intel MID",
471 [AZX_DRIVER_ATI] = "HDA ATI SB",
472 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
473 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
474 [AZX_DRIVER_SIS] = "HDA SIS966",
475 [AZX_DRIVER_ULI] = "HDA ULI M5461",
476 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
477 [AZX_DRIVER_TERA] = "HDA Teradici",
478 [AZX_DRIVER_CTX] = "HDA Creative",
479 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
480 };
481
482 /*
483 * macros for easy use
484 */
485 #define azx_writel(chip,reg,value) \
486 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
487 #define azx_readl(chip,reg) \
488 readl((chip)->remap_addr + ICH6_REG_##reg)
489 #define azx_writew(chip,reg,value) \
490 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
491 #define azx_readw(chip,reg) \
492 readw((chip)->remap_addr + ICH6_REG_##reg)
493 #define azx_writeb(chip,reg,value) \
494 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
495 #define azx_readb(chip,reg) \
496 readb((chip)->remap_addr + ICH6_REG_##reg)
497
498 #define azx_sd_writel(dev,reg,value) \
499 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
500 #define azx_sd_readl(dev,reg) \
501 readl((dev)->sd_addr + ICH6_REG_##reg)
502 #define azx_sd_writew(dev,reg,value) \
503 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
504 #define azx_sd_readw(dev,reg) \
505 readw((dev)->sd_addr + ICH6_REG_##reg)
506 #define azx_sd_writeb(dev,reg,value) \
507 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
508 #define azx_sd_readb(dev,reg) \
509 readb((dev)->sd_addr + ICH6_REG_##reg)
510
511 /* for pcm support */
512 #define get_azx_dev(substream) (substream->runtime->private_data)
513
514 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
515 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
516 /*
517 * Interface for HD codec
518 */
519
520 /*
521 * CORB / RIRB interface
522 */
523 static int azx_alloc_cmd_io(struct azx *chip)
524 {
525 int err;
526
527 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
528 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
529 snd_dma_pci_data(chip->pci),
530 PAGE_SIZE, &chip->rb);
531 if (err < 0) {
532 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
533 return err;
534 }
535 return 0;
536 }
537
538 static void azx_init_cmd_io(struct azx *chip)
539 {
540 spin_lock_irq(&chip->reg_lock);
541 /* CORB set up */
542 chip->corb.addr = chip->rb.addr;
543 chip->corb.buf = (u32 *)chip->rb.area;
544 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
545 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
546
547 /* set the corb size to 256 entries (ULI requires explicitly) */
548 azx_writeb(chip, CORBSIZE, 0x02);
549 /* set the corb write pointer to 0 */
550 azx_writew(chip, CORBWP, 0);
551 /* reset the corb hw read pointer */
552 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
553 /* enable corb dma */
554 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
555
556 /* RIRB set up */
557 chip->rirb.addr = chip->rb.addr + 2048;
558 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
559 chip->rirb.wp = chip->rirb.rp = 0;
560 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
561 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
562 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
563
564 /* set the rirb size to 256 entries (ULI requires explicitly) */
565 azx_writeb(chip, RIRBSIZE, 0x02);
566 /* reset the rirb hw write pointer */
567 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
568 /* set N=1, get RIRB response interrupt for new entry */
569 if (chip->driver_type == AZX_DRIVER_CTX)
570 azx_writew(chip, RINTCNT, 0xc0);
571 else
572 azx_writew(chip, RINTCNT, 1);
573 /* enable rirb dma and response irq */
574 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
575 spin_unlock_irq(&chip->reg_lock);
576 }
577
578 static void azx_free_cmd_io(struct azx *chip)
579 {
580 spin_lock_irq(&chip->reg_lock);
581 /* disable ringbuffer DMAs */
582 azx_writeb(chip, RIRBCTL, 0);
583 azx_writeb(chip, CORBCTL, 0);
584 spin_unlock_irq(&chip->reg_lock);
585 }
586
587 static unsigned int azx_command_addr(u32 cmd)
588 {
589 unsigned int addr = cmd >> 28;
590
591 if (addr >= AZX_MAX_CODECS) {
592 snd_BUG();
593 addr = 0;
594 }
595
596 return addr;
597 }
598
599 static unsigned int azx_response_addr(u32 res)
600 {
601 unsigned int addr = res & 0xf;
602
603 if (addr >= AZX_MAX_CODECS) {
604 snd_BUG();
605 addr = 0;
606 }
607
608 return addr;
609 }
610
611 /* send a command */
612 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
613 {
614 struct azx *chip = bus->private_data;
615 unsigned int addr = azx_command_addr(val);
616 unsigned int wp;
617
618 spin_lock_irq(&chip->reg_lock);
619
620 /* add command to corb */
621 wp = azx_readb(chip, CORBWP);
622 wp++;
623 wp %= ICH6_MAX_CORB_ENTRIES;
624
625 chip->rirb.cmds[addr]++;
626 chip->corb.buf[wp] = cpu_to_le32(val);
627 azx_writel(chip, CORBWP, wp);
628
629 spin_unlock_irq(&chip->reg_lock);
630
631 return 0;
632 }
633
634 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
635
636 /* retrieve RIRB entry - called from interrupt handler */
637 static void azx_update_rirb(struct azx *chip)
638 {
639 unsigned int rp, wp;
640 unsigned int addr;
641 u32 res, res_ex;
642
643 wp = azx_readb(chip, RIRBWP);
644 if (wp == chip->rirb.wp)
645 return;
646 chip->rirb.wp = wp;
647
648 while (chip->rirb.rp != wp) {
649 chip->rirb.rp++;
650 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
651
652 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
653 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
654 res = le32_to_cpu(chip->rirb.buf[rp]);
655 addr = azx_response_addr(res_ex);
656 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
657 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
658 else if (chip->rirb.cmds[addr]) {
659 chip->rirb.res[addr] = res;
660 smp_wmb();
661 chip->rirb.cmds[addr]--;
662 } else
663 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
664 "last cmd=%#08x\n",
665 res, res_ex,
666 chip->last_cmd[addr]);
667 }
668 }
669
670 /* receive a response */
671 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
672 unsigned int addr)
673 {
674 struct azx *chip = bus->private_data;
675 unsigned long timeout;
676 int do_poll = 0;
677
678 again:
679 timeout = jiffies + msecs_to_jiffies(1000);
680 for (;;) {
681 if (chip->polling_mode || do_poll) {
682 spin_lock_irq(&chip->reg_lock);
683 azx_update_rirb(chip);
684 spin_unlock_irq(&chip->reg_lock);
685 }
686 if (!chip->rirb.cmds[addr]) {
687 smp_rmb();
688 bus->rirb_error = 0;
689
690 if (!do_poll)
691 chip->poll_count = 0;
692 return chip->rirb.res[addr]; /* the last value */
693 }
694 if (time_after(jiffies, timeout))
695 break;
696 if (bus->needs_damn_long_delay)
697 msleep(2); /* temporary workaround */
698 else {
699 udelay(10);
700 cond_resched();
701 }
702 }
703
704 if (!chip->polling_mode && chip->poll_count < 2) {
705 snd_printdd(SFX "azx_get_response timeout, "
706 "polling the codec once: last cmd=0x%08x\n",
707 chip->last_cmd[addr]);
708 do_poll = 1;
709 chip->poll_count++;
710 goto again;
711 }
712
713
714 if (!chip->polling_mode) {
715 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
716 "switching to polling mode: last cmd=0x%08x\n",
717 chip->last_cmd[addr]);
718 chip->polling_mode = 1;
719 goto again;
720 }
721
722 if (chip->msi) {
723 snd_printk(KERN_WARNING SFX "No response from codec, "
724 "disabling MSI: last cmd=0x%08x\n",
725 chip->last_cmd[addr]);
726 free_irq(chip->irq, chip);
727 chip->irq = -1;
728 pci_disable_msi(chip->pci);
729 chip->msi = 0;
730 if (azx_acquire_irq(chip, 1) < 0) {
731 bus->rirb_error = 1;
732 return -1;
733 }
734 goto again;
735 }
736
737 if (chip->probing) {
738 /* If this critical timeout happens during the codec probing
739 * phase, this is likely an access to a non-existing codec
740 * slot. Better to return an error and reset the system.
741 */
742 return -1;
743 }
744
745 /* a fatal communication error; need either to reset or to fallback
746 * to the single_cmd mode
747 */
748 bus->rirb_error = 1;
749 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
750 bus->response_reset = 1;
751 return -1; /* give a chance to retry */
752 }
753
754 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
755 "switching to single_cmd mode: last cmd=0x%08x\n",
756 chip->last_cmd[addr]);
757 chip->single_cmd = 1;
758 bus->response_reset = 0;
759 /* release CORB/RIRB */
760 azx_free_cmd_io(chip);
761 /* disable unsolicited responses */
762 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
763 return -1;
764 }
765
766 /*
767 * Use the single immediate command instead of CORB/RIRB for simplicity
768 *
769 * Note: according to Intel, this is not preferred use. The command was
770 * intended for the BIOS only, and may get confused with unsolicited
771 * responses. So, we shouldn't use it for normal operation from the
772 * driver.
773 * I left the codes, however, for debugging/testing purposes.
774 */
775
776 /* receive a response */
777 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
778 {
779 int timeout = 50;
780
781 while (timeout--) {
782 /* check IRV busy bit */
783 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
784 /* reuse rirb.res as the response return value */
785 chip->rirb.res[addr] = azx_readl(chip, IR);
786 return 0;
787 }
788 udelay(1);
789 }
790 if (printk_ratelimit())
791 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
792 azx_readw(chip, IRS));
793 chip->rirb.res[addr] = -1;
794 return -EIO;
795 }
796
797 /* send a command */
798 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
799 {
800 struct azx *chip = bus->private_data;
801 unsigned int addr = azx_command_addr(val);
802 int timeout = 50;
803
804 bus->rirb_error = 0;
805 while (timeout--) {
806 /* check ICB busy bit */
807 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
808 /* Clear IRV valid bit */
809 azx_writew(chip, IRS, azx_readw(chip, IRS) |
810 ICH6_IRS_VALID);
811 azx_writel(chip, IC, val);
812 azx_writew(chip, IRS, azx_readw(chip, IRS) |
813 ICH6_IRS_BUSY);
814 return azx_single_wait_for_response(chip, addr);
815 }
816 udelay(1);
817 }
818 if (printk_ratelimit())
819 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
820 azx_readw(chip, IRS), val);
821 return -EIO;
822 }
823
824 /* receive a response */
825 static unsigned int azx_single_get_response(struct hda_bus *bus,
826 unsigned int addr)
827 {
828 struct azx *chip = bus->private_data;
829 return chip->rirb.res[addr];
830 }
831
832 /*
833 * The below are the main callbacks from hda_codec.
834 *
835 * They are just the skeleton to call sub-callbacks according to the
836 * current setting of chip->single_cmd.
837 */
838
839 /* send a command */
840 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
841 {
842 struct azx *chip = bus->private_data;
843
844 chip->last_cmd[azx_command_addr(val)] = val;
845 if (chip->single_cmd)
846 return azx_single_send_cmd(bus, val);
847 else
848 return azx_corb_send_cmd(bus, val);
849 }
850
851 /* get a response */
852 static unsigned int azx_get_response(struct hda_bus *bus,
853 unsigned int addr)
854 {
855 struct azx *chip = bus->private_data;
856 if (chip->single_cmd)
857 return azx_single_get_response(bus, addr);
858 else
859 return azx_rirb_get_response(bus, addr);
860 }
861
862 #ifdef CONFIG_SND_HDA_POWER_SAVE
863 static void azx_power_notify(struct hda_bus *bus);
864 #endif
865
866 /* reset codec link */
867 static int azx_reset(struct azx *chip, int full_reset)
868 {
869 int count;
870
871 if (!full_reset)
872 goto __skip;
873
874 /* clear STATESTS */
875 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
876
877 /* reset controller */
878 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
879
880 count = 50;
881 while (azx_readb(chip, GCTL) && --count)
882 msleep(1);
883
884 /* delay for >= 100us for codec PLL to settle per spec
885 * Rev 0.9 section 5.5.1
886 */
887 msleep(1);
888
889 /* Bring controller out of reset */
890 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
891
892 count = 50;
893 while (!azx_readb(chip, GCTL) && --count)
894 msleep(1);
895
896 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
897 msleep(1);
898
899 __skip:
900 /* check to see if controller is ready */
901 if (!azx_readb(chip, GCTL)) {
902 snd_printd(SFX "azx_reset: controller not ready!\n");
903 return -EBUSY;
904 }
905
906 /* Accept unsolicited responses */
907 if (!chip->single_cmd)
908 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
909 ICH6_GCTL_UNSOL);
910
911 /* detect codecs */
912 if (!chip->codec_mask) {
913 chip->codec_mask = azx_readw(chip, STATESTS);
914 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
915 }
916
917 return 0;
918 }
919
920
921 /*
922 * Lowlevel interface
923 */
924
925 /* enable interrupts */
926 static void azx_int_enable(struct azx *chip)
927 {
928 /* enable controller CIE and GIE */
929 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
930 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
931 }
932
933 /* disable interrupts */
934 static void azx_int_disable(struct azx *chip)
935 {
936 int i;
937
938 /* disable interrupts in stream descriptor */
939 for (i = 0; i < chip->num_streams; i++) {
940 struct azx_dev *azx_dev = &chip->azx_dev[i];
941 azx_sd_writeb(azx_dev, SD_CTL,
942 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
943 }
944
945 /* disable SIE for all streams */
946 azx_writeb(chip, INTCTL, 0);
947
948 /* disable controller CIE and GIE */
949 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
950 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
951 }
952
953 /* clear interrupts */
954 static void azx_int_clear(struct azx *chip)
955 {
956 int i;
957
958 /* clear stream status */
959 for (i = 0; i < chip->num_streams; i++) {
960 struct azx_dev *azx_dev = &chip->azx_dev[i];
961 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
962 }
963
964 /* clear STATESTS */
965 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
966
967 /* clear rirb status */
968 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
969
970 /* clear int status */
971 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
972 }
973
974 /* start a stream */
975 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
976 {
977 /*
978 * Before stream start, initialize parameter
979 */
980 azx_dev->insufficient = 1;
981
982 /* enable SIE */
983 azx_writel(chip, INTCTL,
984 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
985 /* set DMA start and interrupt mask */
986 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
987 SD_CTL_DMA_START | SD_INT_MASK);
988 }
989
990 /* stop DMA */
991 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
992 {
993 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
994 ~(SD_CTL_DMA_START | SD_INT_MASK));
995 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
996 }
997
998 /* stop a stream */
999 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1000 {
1001 azx_stream_clear(chip, azx_dev);
1002 /* disable SIE */
1003 azx_writel(chip, INTCTL,
1004 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1005 }
1006
1007
1008 /*
1009 * reset and start the controller registers
1010 */
1011 static void azx_init_chip(struct azx *chip, int full_reset)
1012 {
1013 if (chip->initialized)
1014 return;
1015
1016 /* reset controller */
1017 azx_reset(chip, full_reset);
1018
1019 /* initialize interrupts */
1020 azx_int_clear(chip);
1021 azx_int_enable(chip);
1022
1023 /* initialize the codec command I/O */
1024 if (!chip->single_cmd)
1025 azx_init_cmd_io(chip);
1026
1027 /* program the position buffer */
1028 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1029 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1030
1031 chip->initialized = 1;
1032 }
1033
1034 /*
1035 * initialize the PCI registers
1036 */
1037 /* update bits in a PCI register byte */
1038 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1039 unsigned char mask, unsigned char val)
1040 {
1041 unsigned char data;
1042
1043 pci_read_config_byte(pci, reg, &data);
1044 data &= ~mask;
1045 data |= (val & mask);
1046 pci_write_config_byte(pci, reg, data);
1047 }
1048
1049 static void azx_init_pci(struct azx *chip)
1050 {
1051 unsigned short snoop;
1052
1053 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1054 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1055 * Ensuring these bits are 0 clears playback static on some HD Audio
1056 * codecs.
1057 * The PCI register TCSEL is defined in the Intel manuals.
1058 */
1059 if (chip->driver_type != AZX_DRIVER_ATI &&
1060 chip->driver_type != AZX_DRIVER_ATIHDMI)
1061 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1062
1063 switch (chip->driver_type) {
1064 case AZX_DRIVER_ATI:
1065 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1066 update_pci_byte(chip->pci,
1067 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1068 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1069 break;
1070 case AZX_DRIVER_NVIDIA:
1071 /* For NVIDIA HDA, enable snoop */
1072 update_pci_byte(chip->pci,
1073 NVIDIA_HDA_TRANSREG_ADDR,
1074 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1075 update_pci_byte(chip->pci,
1076 NVIDIA_HDA_ISTRM_COH,
1077 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1078 update_pci_byte(chip->pci,
1079 NVIDIA_HDA_OSTRM_COH,
1080 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1081 break;
1082 case AZX_DRIVER_SCH:
1083 case AZX_DRIVER_PCH:
1084 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1085 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1086 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1087 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1088 pci_read_config_word(chip->pci,
1089 INTEL_SCH_HDA_DEVC, &snoop);
1090 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1091 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1092 ? "Failed" : "OK");
1093 }
1094 break;
1095
1096 }
1097 }
1098
1099
1100 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1101
1102 /*
1103 * interrupt handler
1104 */
1105 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1106 {
1107 struct azx *chip = dev_id;
1108 struct azx_dev *azx_dev;
1109 u32 status;
1110 u8 sd_status;
1111 int i, ok;
1112
1113 spin_lock(&chip->reg_lock);
1114
1115 status = azx_readl(chip, INTSTS);
1116 if (status == 0) {
1117 spin_unlock(&chip->reg_lock);
1118 return IRQ_NONE;
1119 }
1120
1121 for (i = 0; i < chip->num_streams; i++) {
1122 azx_dev = &chip->azx_dev[i];
1123 if (status & azx_dev->sd_int_sta_mask) {
1124 sd_status = azx_sd_readb(azx_dev, SD_STS);
1125 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1126 if (!azx_dev->substream || !azx_dev->running ||
1127 !(sd_status & SD_INT_COMPLETE))
1128 continue;
1129 /* check whether this IRQ is really acceptable */
1130 ok = azx_position_ok(chip, azx_dev);
1131 if (ok == 1) {
1132 azx_dev->irq_pending = 0;
1133 spin_unlock(&chip->reg_lock);
1134 snd_pcm_period_elapsed(azx_dev->substream);
1135 spin_lock(&chip->reg_lock);
1136 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1137 /* bogus IRQ, process it later */
1138 azx_dev->irq_pending = 1;
1139 queue_work(chip->bus->workq,
1140 &chip->irq_pending_work);
1141 }
1142 }
1143 }
1144
1145 /* clear rirb int */
1146 status = azx_readb(chip, RIRBSTS);
1147 if (status & RIRB_INT_MASK) {
1148 if (status & RIRB_INT_RESPONSE) {
1149 if (chip->driver_type == AZX_DRIVER_CTX)
1150 udelay(80);
1151 azx_update_rirb(chip);
1152 }
1153 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1154 }
1155
1156 #if 0
1157 /* clear state status int */
1158 if (azx_readb(chip, STATESTS) & 0x04)
1159 azx_writeb(chip, STATESTS, 0x04);
1160 #endif
1161 spin_unlock(&chip->reg_lock);
1162
1163 return IRQ_HANDLED;
1164 }
1165
1166
1167 /*
1168 * set up a BDL entry
1169 */
1170 static int setup_bdle(struct snd_pcm_substream *substream,
1171 struct azx_dev *azx_dev, u32 **bdlp,
1172 int ofs, int size, int with_ioc)
1173 {
1174 u32 *bdl = *bdlp;
1175
1176 while (size > 0) {
1177 dma_addr_t addr;
1178 int chunk;
1179
1180 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1181 return -EINVAL;
1182
1183 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1184 /* program the address field of the BDL entry */
1185 bdl[0] = cpu_to_le32((u32)addr);
1186 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1187 /* program the size field of the BDL entry */
1188 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1189 bdl[2] = cpu_to_le32(chunk);
1190 /* program the IOC to enable interrupt
1191 * only when the whole fragment is processed
1192 */
1193 size -= chunk;
1194 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1195 bdl += 4;
1196 azx_dev->frags++;
1197 ofs += chunk;
1198 }
1199 *bdlp = bdl;
1200 return ofs;
1201 }
1202
1203 /*
1204 * set up BDL entries
1205 */
1206 static int azx_setup_periods(struct azx *chip,
1207 struct snd_pcm_substream *substream,
1208 struct azx_dev *azx_dev)
1209 {
1210 u32 *bdl;
1211 int i, ofs, periods, period_bytes;
1212 int pos_adj;
1213
1214 /* reset BDL address */
1215 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1216 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1217
1218 period_bytes = azx_dev->period_bytes;
1219 periods = azx_dev->bufsize / period_bytes;
1220
1221 /* program the initial BDL entries */
1222 bdl = (u32 *)azx_dev->bdl.area;
1223 ofs = 0;
1224 azx_dev->frags = 0;
1225 pos_adj = bdl_pos_adj[chip->dev_index];
1226 if (pos_adj > 0) {
1227 struct snd_pcm_runtime *runtime = substream->runtime;
1228 int pos_align = pos_adj;
1229 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1230 if (!pos_adj)
1231 pos_adj = pos_align;
1232 else
1233 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1234 pos_align;
1235 pos_adj = frames_to_bytes(runtime, pos_adj);
1236 if (pos_adj >= period_bytes) {
1237 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1238 bdl_pos_adj[chip->dev_index]);
1239 pos_adj = 0;
1240 } else {
1241 ofs = setup_bdle(substream, azx_dev,
1242 &bdl, ofs, pos_adj,
1243 !substream->runtime->no_period_wakeup);
1244 if (ofs < 0)
1245 goto error;
1246 }
1247 } else
1248 pos_adj = 0;
1249 for (i = 0; i < periods; i++) {
1250 if (i == periods - 1 && pos_adj)
1251 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1252 period_bytes - pos_adj, 0);
1253 else
1254 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1255 period_bytes,
1256 !substream->runtime->no_period_wakeup);
1257 if (ofs < 0)
1258 goto error;
1259 }
1260 return 0;
1261
1262 error:
1263 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1264 azx_dev->bufsize, period_bytes);
1265 return -EINVAL;
1266 }
1267
1268 /* reset stream */
1269 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1270 {
1271 unsigned char val;
1272 int timeout;
1273
1274 azx_stream_clear(chip, azx_dev);
1275
1276 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1277 SD_CTL_STREAM_RESET);
1278 udelay(3);
1279 timeout = 300;
1280 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1281 --timeout)
1282 ;
1283 val &= ~SD_CTL_STREAM_RESET;
1284 azx_sd_writeb(azx_dev, SD_CTL, val);
1285 udelay(3);
1286
1287 timeout = 300;
1288 /* waiting for hardware to report that the stream is out of reset */
1289 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1290 --timeout)
1291 ;
1292
1293 /* reset first position - may not be synced with hw at this time */
1294 *azx_dev->posbuf = 0;
1295 }
1296
1297 /*
1298 * set up the SD for streaming
1299 */
1300 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1301 {
1302 /* make sure the run bit is zero for SD */
1303 azx_stream_clear(chip, azx_dev);
1304 /* program the stream_tag */
1305 azx_sd_writel(azx_dev, SD_CTL,
1306 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1307 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1308
1309 /* program the length of samples in cyclic buffer */
1310 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1311
1312 /* program the stream format */
1313 /* this value needs to be the same as the one programmed */
1314 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1315
1316 /* program the stream LVI (last valid index) of the BDL */
1317 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1318
1319 /* program the BDL address */
1320 /* lower BDL address */
1321 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1322 /* upper BDL address */
1323 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1324
1325 /* enable the position buffer */
1326 if (chip->position_fix[0] != POS_FIX_LPIB ||
1327 chip->position_fix[1] != POS_FIX_LPIB) {
1328 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1329 azx_writel(chip, DPLBASE,
1330 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1331 }
1332
1333 /* set the interrupt enable bits in the descriptor control register */
1334 azx_sd_writel(azx_dev, SD_CTL,
1335 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1336
1337 return 0;
1338 }
1339
1340 /*
1341 * Probe the given codec address
1342 */
1343 static int probe_codec(struct azx *chip, int addr)
1344 {
1345 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1346 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1347 unsigned int res;
1348
1349 mutex_lock(&chip->bus->cmd_mutex);
1350 chip->probing = 1;
1351 azx_send_cmd(chip->bus, cmd);
1352 res = azx_get_response(chip->bus, addr);
1353 chip->probing = 0;
1354 mutex_unlock(&chip->bus->cmd_mutex);
1355 if (res == -1)
1356 return -EIO;
1357 snd_printdd(SFX "codec #%d probed OK\n", addr);
1358 return 0;
1359 }
1360
1361 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1362 struct hda_pcm *cpcm);
1363 static void azx_stop_chip(struct azx *chip);
1364
1365 static void azx_bus_reset(struct hda_bus *bus)
1366 {
1367 struct azx *chip = bus->private_data;
1368
1369 bus->in_reset = 1;
1370 azx_stop_chip(chip);
1371 azx_init_chip(chip, 1);
1372 #ifdef CONFIG_PM
1373 if (chip->initialized) {
1374 int i;
1375
1376 for (i = 0; i < HDA_MAX_PCMS; i++)
1377 snd_pcm_suspend_all(chip->pcm[i]);
1378 snd_hda_suspend(chip->bus);
1379 snd_hda_resume(chip->bus);
1380 }
1381 #endif
1382 bus->in_reset = 0;
1383 }
1384
1385 /*
1386 * Codec initialization
1387 */
1388
1389 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1390 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1391 [AZX_DRIVER_NVIDIA] = 8,
1392 [AZX_DRIVER_TERA] = 1,
1393 };
1394
1395 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1396 {
1397 struct hda_bus_template bus_temp;
1398 int c, codecs, err;
1399 int max_slots;
1400
1401 memset(&bus_temp, 0, sizeof(bus_temp));
1402 bus_temp.private_data = chip;
1403 bus_temp.modelname = model;
1404 bus_temp.pci = chip->pci;
1405 bus_temp.ops.command = azx_send_cmd;
1406 bus_temp.ops.get_response = azx_get_response;
1407 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1408 bus_temp.ops.bus_reset = azx_bus_reset;
1409 #ifdef CONFIG_SND_HDA_POWER_SAVE
1410 bus_temp.power_save = &power_save;
1411 bus_temp.ops.pm_notify = azx_power_notify;
1412 #endif
1413
1414 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1415 if (err < 0)
1416 return err;
1417
1418 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1419 chip->bus->needs_damn_long_delay = 1;
1420
1421 codecs = 0;
1422 max_slots = azx_max_codecs[chip->driver_type];
1423 if (!max_slots)
1424 max_slots = AZX_DEFAULT_CODECS;
1425
1426 /* First try to probe all given codec slots */
1427 for (c = 0; c < max_slots; c++) {
1428 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1429 if (probe_codec(chip, c) < 0) {
1430 /* Some BIOSen give you wrong codec addresses
1431 * that don't exist
1432 */
1433 snd_printk(KERN_WARNING SFX
1434 "Codec #%d probe error; "
1435 "disabling it...\n", c);
1436 chip->codec_mask &= ~(1 << c);
1437 /* More badly, accessing to a non-existing
1438 * codec often screws up the controller chip,
1439 * and disturbs the further communications.
1440 * Thus if an error occurs during probing,
1441 * better to reset the controller chip to
1442 * get back to the sanity state.
1443 */
1444 azx_stop_chip(chip);
1445 azx_init_chip(chip, 1);
1446 }
1447 }
1448 }
1449
1450 /* Then create codec instances */
1451 for (c = 0; c < max_slots; c++) {
1452 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1453 struct hda_codec *codec;
1454 err = snd_hda_codec_new(chip->bus, c, &codec);
1455 if (err < 0)
1456 continue;
1457 codec->beep_mode = chip->beep_mode;
1458 codecs++;
1459 }
1460 }
1461 if (!codecs) {
1462 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1463 return -ENXIO;
1464 }
1465 return 0;
1466 }
1467
1468 /* configure each codec instance */
1469 static int __devinit azx_codec_configure(struct azx *chip)
1470 {
1471 struct hda_codec *codec;
1472 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1473 snd_hda_codec_configure(codec);
1474 }
1475 return 0;
1476 }
1477
1478
1479 /*
1480 * PCM support
1481 */
1482
1483 /* assign a stream for the PCM */
1484 static inline struct azx_dev *
1485 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1486 {
1487 int dev, i, nums;
1488 struct azx_dev *res = NULL;
1489
1490 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1491 dev = chip->playback_index_offset;
1492 nums = chip->playback_streams;
1493 } else {
1494 dev = chip->capture_index_offset;
1495 nums = chip->capture_streams;
1496 }
1497 for (i = 0; i < nums; i++, dev++)
1498 if (!chip->azx_dev[dev].opened) {
1499 res = &chip->azx_dev[dev];
1500 if (res->device == substream->pcm->device)
1501 break;
1502 }
1503 if (res) {
1504 res->opened = 1;
1505 res->device = substream->pcm->device;
1506 }
1507 return res;
1508 }
1509
1510 /* release the assigned stream */
1511 static inline void azx_release_device(struct azx_dev *azx_dev)
1512 {
1513 azx_dev->opened = 0;
1514 }
1515
1516 static struct snd_pcm_hardware azx_pcm_hw = {
1517 .info = (SNDRV_PCM_INFO_MMAP |
1518 SNDRV_PCM_INFO_INTERLEAVED |
1519 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1520 SNDRV_PCM_INFO_MMAP_VALID |
1521 /* No full-resume yet implemented */
1522 /* SNDRV_PCM_INFO_RESUME |*/
1523 SNDRV_PCM_INFO_PAUSE |
1524 SNDRV_PCM_INFO_SYNC_START |
1525 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1526 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1527 .rates = SNDRV_PCM_RATE_48000,
1528 .rate_min = 48000,
1529 .rate_max = 48000,
1530 .channels_min = 2,
1531 .channels_max = 2,
1532 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1533 .period_bytes_min = 128,
1534 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1535 .periods_min = 2,
1536 .periods_max = AZX_MAX_FRAG,
1537 .fifo_size = 0,
1538 };
1539
1540 struct azx_pcm {
1541 struct azx *chip;
1542 struct hda_codec *codec;
1543 struct hda_pcm_stream *hinfo[2];
1544 };
1545
1546 static int azx_pcm_open(struct snd_pcm_substream *substream)
1547 {
1548 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1549 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1550 struct azx *chip = apcm->chip;
1551 struct azx_dev *azx_dev;
1552 struct snd_pcm_runtime *runtime = substream->runtime;
1553 unsigned long flags;
1554 int err;
1555
1556 mutex_lock(&chip->open_mutex);
1557 azx_dev = azx_assign_device(chip, substream);
1558 if (azx_dev == NULL) {
1559 mutex_unlock(&chip->open_mutex);
1560 return -EBUSY;
1561 }
1562 runtime->hw = azx_pcm_hw;
1563 runtime->hw.channels_min = hinfo->channels_min;
1564 runtime->hw.channels_max = hinfo->channels_max;
1565 runtime->hw.formats = hinfo->formats;
1566 runtime->hw.rates = hinfo->rates;
1567 snd_pcm_limit_hw_rates(runtime);
1568 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1569 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1570 128);
1571 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1572 128);
1573 snd_hda_power_up(apcm->codec);
1574 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1575 if (err < 0) {
1576 azx_release_device(azx_dev);
1577 snd_hda_power_down(apcm->codec);
1578 mutex_unlock(&chip->open_mutex);
1579 return err;
1580 }
1581 snd_pcm_limit_hw_rates(runtime);
1582 /* sanity check */
1583 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1584 snd_BUG_ON(!runtime->hw.channels_max) ||
1585 snd_BUG_ON(!runtime->hw.formats) ||
1586 snd_BUG_ON(!runtime->hw.rates)) {
1587 azx_release_device(azx_dev);
1588 hinfo->ops.close(hinfo, apcm->codec, substream);
1589 snd_hda_power_down(apcm->codec);
1590 mutex_unlock(&chip->open_mutex);
1591 return -EINVAL;
1592 }
1593 spin_lock_irqsave(&chip->reg_lock, flags);
1594 azx_dev->substream = substream;
1595 azx_dev->running = 0;
1596 spin_unlock_irqrestore(&chip->reg_lock, flags);
1597
1598 runtime->private_data = azx_dev;
1599 snd_pcm_set_sync(substream);
1600 mutex_unlock(&chip->open_mutex);
1601 return 0;
1602 }
1603
1604 static int azx_pcm_close(struct snd_pcm_substream *substream)
1605 {
1606 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1607 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1608 struct azx *chip = apcm->chip;
1609 struct azx_dev *azx_dev = get_azx_dev(substream);
1610 unsigned long flags;
1611
1612 mutex_lock(&chip->open_mutex);
1613 spin_lock_irqsave(&chip->reg_lock, flags);
1614 azx_dev->substream = NULL;
1615 azx_dev->running = 0;
1616 spin_unlock_irqrestore(&chip->reg_lock, flags);
1617 azx_release_device(azx_dev);
1618 hinfo->ops.close(hinfo, apcm->codec, substream);
1619 snd_hda_power_down(apcm->codec);
1620 mutex_unlock(&chip->open_mutex);
1621 return 0;
1622 }
1623
1624 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1625 struct snd_pcm_hw_params *hw_params)
1626 {
1627 struct azx_dev *azx_dev = get_azx_dev(substream);
1628
1629 azx_dev->bufsize = 0;
1630 azx_dev->period_bytes = 0;
1631 azx_dev->format_val = 0;
1632 return snd_pcm_lib_malloc_pages(substream,
1633 params_buffer_bytes(hw_params));
1634 }
1635
1636 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1637 {
1638 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1639 struct azx_dev *azx_dev = get_azx_dev(substream);
1640 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1641
1642 /* reset BDL address */
1643 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1644 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1645 azx_sd_writel(azx_dev, SD_CTL, 0);
1646 azx_dev->bufsize = 0;
1647 azx_dev->period_bytes = 0;
1648 azx_dev->format_val = 0;
1649
1650 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1651
1652 return snd_pcm_lib_free_pages(substream);
1653 }
1654
1655 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1656 {
1657 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1658 struct azx *chip = apcm->chip;
1659 struct azx_dev *azx_dev = get_azx_dev(substream);
1660 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1661 struct snd_pcm_runtime *runtime = substream->runtime;
1662 unsigned int bufsize, period_bytes, format_val, stream_tag;
1663 int err;
1664
1665 azx_stream_reset(chip, azx_dev);
1666 format_val = snd_hda_calc_stream_format(runtime->rate,
1667 runtime->channels,
1668 runtime->format,
1669 hinfo->maxbps,
1670 apcm->codec->spdif_ctls);
1671 if (!format_val) {
1672 snd_printk(KERN_ERR SFX
1673 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1674 runtime->rate, runtime->channels, runtime->format);
1675 return -EINVAL;
1676 }
1677
1678 bufsize = snd_pcm_lib_buffer_bytes(substream);
1679 period_bytes = snd_pcm_lib_period_bytes(substream);
1680
1681 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1682 bufsize, format_val);
1683
1684 if (bufsize != azx_dev->bufsize ||
1685 period_bytes != azx_dev->period_bytes ||
1686 format_val != azx_dev->format_val) {
1687 azx_dev->bufsize = bufsize;
1688 azx_dev->period_bytes = period_bytes;
1689 azx_dev->format_val = format_val;
1690 err = azx_setup_periods(chip, substream, azx_dev);
1691 if (err < 0)
1692 return err;
1693 }
1694
1695 /* wallclk has 24Mhz clock source */
1696 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1697 runtime->rate) * 1000);
1698 azx_setup_controller(chip, azx_dev);
1699 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1700 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1701 else
1702 azx_dev->fifo_size = 0;
1703
1704 stream_tag = azx_dev->stream_tag;
1705 /* CA-IBG chips need the playback stream starting from 1 */
1706 if (chip->driver_type == AZX_DRIVER_CTX &&
1707 stream_tag > chip->capture_streams)
1708 stream_tag -= chip->capture_streams;
1709 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1710 azx_dev->format_val, substream);
1711 }
1712
1713 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1714 {
1715 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1716 struct azx *chip = apcm->chip;
1717 struct azx_dev *azx_dev;
1718 struct snd_pcm_substream *s;
1719 int rstart = 0, start, nsync = 0, sbits = 0;
1720 int nwait, timeout;
1721
1722 switch (cmd) {
1723 case SNDRV_PCM_TRIGGER_START:
1724 rstart = 1;
1725 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1726 case SNDRV_PCM_TRIGGER_RESUME:
1727 start = 1;
1728 break;
1729 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1730 case SNDRV_PCM_TRIGGER_SUSPEND:
1731 case SNDRV_PCM_TRIGGER_STOP:
1732 start = 0;
1733 break;
1734 default:
1735 return -EINVAL;
1736 }
1737
1738 snd_pcm_group_for_each_entry(s, substream) {
1739 if (s->pcm->card != substream->pcm->card)
1740 continue;
1741 azx_dev = get_azx_dev(s);
1742 sbits |= 1 << azx_dev->index;
1743 nsync++;
1744 snd_pcm_trigger_done(s, substream);
1745 }
1746
1747 spin_lock(&chip->reg_lock);
1748 if (nsync > 1) {
1749 /* first, set SYNC bits of corresponding streams */
1750 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1751 }
1752 snd_pcm_group_for_each_entry(s, substream) {
1753 if (s->pcm->card != substream->pcm->card)
1754 continue;
1755 azx_dev = get_azx_dev(s);
1756 if (start) {
1757 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1758 if (!rstart)
1759 azx_dev->start_wallclk -=
1760 azx_dev->period_wallclk;
1761 azx_stream_start(chip, azx_dev);
1762 } else {
1763 azx_stream_stop(chip, azx_dev);
1764 }
1765 azx_dev->running = start;
1766 }
1767 spin_unlock(&chip->reg_lock);
1768 if (start) {
1769 if (nsync == 1)
1770 return 0;
1771 /* wait until all FIFOs get ready */
1772 for (timeout = 5000; timeout; timeout--) {
1773 nwait = 0;
1774 snd_pcm_group_for_each_entry(s, substream) {
1775 if (s->pcm->card != substream->pcm->card)
1776 continue;
1777 azx_dev = get_azx_dev(s);
1778 if (!(azx_sd_readb(azx_dev, SD_STS) &
1779 SD_STS_FIFO_READY))
1780 nwait++;
1781 }
1782 if (!nwait)
1783 break;
1784 cpu_relax();
1785 }
1786 } else {
1787 /* wait until all RUN bits are cleared */
1788 for (timeout = 5000; timeout; timeout--) {
1789 nwait = 0;
1790 snd_pcm_group_for_each_entry(s, substream) {
1791 if (s->pcm->card != substream->pcm->card)
1792 continue;
1793 azx_dev = get_azx_dev(s);
1794 if (azx_sd_readb(azx_dev, SD_CTL) &
1795 SD_CTL_DMA_START)
1796 nwait++;
1797 }
1798 if (!nwait)
1799 break;
1800 cpu_relax();
1801 }
1802 }
1803 if (nsync > 1) {
1804 spin_lock(&chip->reg_lock);
1805 /* reset SYNC bits */
1806 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1807 spin_unlock(&chip->reg_lock);
1808 }
1809 return 0;
1810 }
1811
1812 /* get the current DMA position with correction on VIA chips */
1813 static unsigned int azx_via_get_position(struct azx *chip,
1814 struct azx_dev *azx_dev)
1815 {
1816 unsigned int link_pos, mini_pos, bound_pos;
1817 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1818 unsigned int fifo_size;
1819
1820 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1821 if (azx_dev->index >= 4) {
1822 /* Playback, no problem using link position */
1823 return link_pos;
1824 }
1825
1826 /* Capture */
1827 /* For new chipset,
1828 * use mod to get the DMA position just like old chipset
1829 */
1830 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1831 mod_dma_pos %= azx_dev->period_bytes;
1832
1833 /* azx_dev->fifo_size can't get FIFO size of in stream.
1834 * Get from base address + offset.
1835 */
1836 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1837
1838 if (azx_dev->insufficient) {
1839 /* Link position never gather than FIFO size */
1840 if (link_pos <= fifo_size)
1841 return 0;
1842
1843 azx_dev->insufficient = 0;
1844 }
1845
1846 if (link_pos <= fifo_size)
1847 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1848 else
1849 mini_pos = link_pos - fifo_size;
1850
1851 /* Find nearest previous boudary */
1852 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1853 mod_link_pos = link_pos % azx_dev->period_bytes;
1854 if (mod_link_pos >= fifo_size)
1855 bound_pos = link_pos - mod_link_pos;
1856 else if (mod_dma_pos >= mod_mini_pos)
1857 bound_pos = mini_pos - mod_mini_pos;
1858 else {
1859 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1860 if (bound_pos >= azx_dev->bufsize)
1861 bound_pos = 0;
1862 }
1863
1864 /* Calculate real DMA position we want */
1865 return bound_pos + mod_dma_pos;
1866 }
1867
1868 static unsigned int azx_get_position(struct azx *chip,
1869 struct azx_dev *azx_dev)
1870 {
1871 unsigned int pos;
1872 int stream = azx_dev->substream->stream;
1873
1874 switch (chip->position_fix[stream]) {
1875 case POS_FIX_LPIB:
1876 /* read LPIB */
1877 pos = azx_sd_readl(azx_dev, SD_LPIB);
1878 break;
1879 case POS_FIX_VIACOMBO:
1880 pos = azx_via_get_position(chip, azx_dev);
1881 break;
1882 default:
1883 /* use the position buffer */
1884 pos = le32_to_cpu(*azx_dev->posbuf);
1885 }
1886
1887 if (pos >= azx_dev->bufsize)
1888 pos = 0;
1889 return pos;
1890 }
1891
1892 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1893 {
1894 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1895 struct azx *chip = apcm->chip;
1896 struct azx_dev *azx_dev = get_azx_dev(substream);
1897 return bytes_to_frames(substream->runtime,
1898 azx_get_position(chip, azx_dev));
1899 }
1900
1901 /*
1902 * Check whether the current DMA position is acceptable for updating
1903 * periods. Returns non-zero if it's OK.
1904 *
1905 * Many HD-audio controllers appear pretty inaccurate about
1906 * the update-IRQ timing. The IRQ is issued before actually the
1907 * data is processed. So, we need to process it afterwords in a
1908 * workqueue.
1909 */
1910 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1911 {
1912 u32 wallclk;
1913 unsigned int pos;
1914 int stream;
1915
1916 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1917 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1918 return -1; /* bogus (too early) interrupt */
1919
1920 stream = azx_dev->substream->stream;
1921 pos = azx_get_position(chip, azx_dev);
1922 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1923 if (!pos) {
1924 printk(KERN_WARNING
1925 "hda-intel: Invalid position buffer, "
1926 "using LPIB read method instead.\n");
1927 chip->position_fix[stream] = POS_FIX_LPIB;
1928 pos = azx_get_position(chip, azx_dev);
1929 } else
1930 chip->position_fix[stream] = POS_FIX_POSBUF;
1931 }
1932
1933 if (WARN_ONCE(!azx_dev->period_bytes,
1934 "hda-intel: zero azx_dev->period_bytes"))
1935 return -1; /* this shouldn't happen! */
1936 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1937 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1938 /* NG - it's below the first next period boundary */
1939 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1940 azx_dev->start_wallclk += wallclk;
1941 return 1; /* OK, it's fine */
1942 }
1943
1944 /*
1945 * The work for pending PCM period updates.
1946 */
1947 static void azx_irq_pending_work(struct work_struct *work)
1948 {
1949 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1950 int i, pending, ok;
1951
1952 if (!chip->irq_pending_warned) {
1953 printk(KERN_WARNING
1954 "hda-intel: IRQ timing workaround is activated "
1955 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1956 chip->card->number);
1957 chip->irq_pending_warned = 1;
1958 }
1959
1960 for (;;) {
1961 pending = 0;
1962 spin_lock_irq(&chip->reg_lock);
1963 for (i = 0; i < chip->num_streams; i++) {
1964 struct azx_dev *azx_dev = &chip->azx_dev[i];
1965 if (!azx_dev->irq_pending ||
1966 !azx_dev->substream ||
1967 !azx_dev->running)
1968 continue;
1969 ok = azx_position_ok(chip, azx_dev);
1970 if (ok > 0) {
1971 azx_dev->irq_pending = 0;
1972 spin_unlock(&chip->reg_lock);
1973 snd_pcm_period_elapsed(azx_dev->substream);
1974 spin_lock(&chip->reg_lock);
1975 } else if (ok < 0) {
1976 pending = 0; /* too early */
1977 } else
1978 pending++;
1979 }
1980 spin_unlock_irq(&chip->reg_lock);
1981 if (!pending)
1982 return;
1983 msleep(1);
1984 }
1985 }
1986
1987 /* clear irq_pending flags and assure no on-going workq */
1988 static void azx_clear_irq_pending(struct azx *chip)
1989 {
1990 int i;
1991
1992 spin_lock_irq(&chip->reg_lock);
1993 for (i = 0; i < chip->num_streams; i++)
1994 chip->azx_dev[i].irq_pending = 0;
1995 spin_unlock_irq(&chip->reg_lock);
1996 }
1997
1998 static struct snd_pcm_ops azx_pcm_ops = {
1999 .open = azx_pcm_open,
2000 .close = azx_pcm_close,
2001 .ioctl = snd_pcm_lib_ioctl,
2002 .hw_params = azx_pcm_hw_params,
2003 .hw_free = azx_pcm_hw_free,
2004 .prepare = azx_pcm_prepare,
2005 .trigger = azx_pcm_trigger,
2006 .pointer = azx_pcm_pointer,
2007 .page = snd_pcm_sgbuf_ops_page,
2008 };
2009
2010 static void azx_pcm_free(struct snd_pcm *pcm)
2011 {
2012 struct azx_pcm *apcm = pcm->private_data;
2013 if (apcm) {
2014 apcm->chip->pcm[pcm->device] = NULL;
2015 kfree(apcm);
2016 }
2017 }
2018
2019 static int
2020 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2021 struct hda_pcm *cpcm)
2022 {
2023 struct azx *chip = bus->private_data;
2024 struct snd_pcm *pcm;
2025 struct azx_pcm *apcm;
2026 int pcm_dev = cpcm->device;
2027 int s, err;
2028
2029 if (pcm_dev >= HDA_MAX_PCMS) {
2030 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2031 pcm_dev);
2032 return -EINVAL;
2033 }
2034 if (chip->pcm[pcm_dev]) {
2035 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2036 return -EBUSY;
2037 }
2038 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2039 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2040 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2041 &pcm);
2042 if (err < 0)
2043 return err;
2044 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2045 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2046 if (apcm == NULL)
2047 return -ENOMEM;
2048 apcm->chip = chip;
2049 apcm->codec = codec;
2050 pcm->private_data = apcm;
2051 pcm->private_free = azx_pcm_free;
2052 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2053 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2054 chip->pcm[pcm_dev] = pcm;
2055 cpcm->pcm = pcm;
2056 for (s = 0; s < 2; s++) {
2057 apcm->hinfo[s] = &cpcm->stream[s];
2058 if (cpcm->stream[s].substreams)
2059 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2060 }
2061 /* buffer pre-allocation */
2062 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2063 snd_dma_pci_data(chip->pci),
2064 1024 * 64, 32 * 1024 * 1024);
2065 return 0;
2066 }
2067
2068 /*
2069 * mixer creation - all stuff is implemented in hda module
2070 */
2071 static int __devinit azx_mixer_create(struct azx *chip)
2072 {
2073 return snd_hda_build_controls(chip->bus);
2074 }
2075
2076
2077 /*
2078 * initialize SD streams
2079 */
2080 static int __devinit azx_init_stream(struct azx *chip)
2081 {
2082 int i;
2083
2084 /* initialize each stream (aka device)
2085 * assign the starting bdl address to each stream (device)
2086 * and initialize
2087 */
2088 for (i = 0; i < chip->num_streams; i++) {
2089 struct azx_dev *azx_dev = &chip->azx_dev[i];
2090 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2091 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2092 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2093 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2094 azx_dev->sd_int_sta_mask = 1 << i;
2095 /* stream tag: must be non-zero and unique */
2096 azx_dev->index = i;
2097 azx_dev->stream_tag = i + 1;
2098 }
2099
2100 return 0;
2101 }
2102
2103 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2104 {
2105 if (request_irq(chip->pci->irq, azx_interrupt,
2106 chip->msi ? 0 : IRQF_SHARED,
2107 "hda_intel", chip)) {
2108 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2109 "disabling device\n", chip->pci->irq);
2110 if (do_disconnect)
2111 snd_card_disconnect(chip->card);
2112 return -1;
2113 }
2114 chip->irq = chip->pci->irq;
2115 pci_intx(chip->pci, !chip->msi);
2116 return 0;
2117 }
2118
2119
2120 static void azx_stop_chip(struct azx *chip)
2121 {
2122 if (!chip->initialized)
2123 return;
2124
2125 /* disable interrupts */
2126 azx_int_disable(chip);
2127 azx_int_clear(chip);
2128
2129 /* disable CORB/RIRB */
2130 azx_free_cmd_io(chip);
2131
2132 /* disable position buffer */
2133 azx_writel(chip, DPLBASE, 0);
2134 azx_writel(chip, DPUBASE, 0);
2135
2136 chip->initialized = 0;
2137 }
2138
2139 #ifdef CONFIG_SND_HDA_POWER_SAVE
2140 /* power-up/down the controller */
2141 static void azx_power_notify(struct hda_bus *bus)
2142 {
2143 struct azx *chip = bus->private_data;
2144 struct hda_codec *c;
2145 int power_on = 0;
2146
2147 list_for_each_entry(c, &bus->codec_list, list) {
2148 if (c->power_on) {
2149 power_on = 1;
2150 break;
2151 }
2152 }
2153 if (power_on)
2154 azx_init_chip(chip, 1);
2155 else if (chip->running && power_save_controller &&
2156 !bus->power_keep_link_on)
2157 azx_stop_chip(chip);
2158 }
2159 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2160
2161 #ifdef CONFIG_PM
2162 /*
2163 * power management
2164 */
2165
2166 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2167 {
2168 struct hda_codec *codec;
2169
2170 list_for_each_entry(codec, &bus->codec_list, list) {
2171 if (snd_hda_codec_needs_resume(codec))
2172 return 1;
2173 }
2174 return 0;
2175 }
2176
2177 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2178 {
2179 struct snd_card *card = pci_get_drvdata(pci);
2180 struct azx *chip = card->private_data;
2181 int i;
2182
2183 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2184 azx_clear_irq_pending(chip);
2185 for (i = 0; i < HDA_MAX_PCMS; i++)
2186 snd_pcm_suspend_all(chip->pcm[i]);
2187 if (chip->initialized)
2188 snd_hda_suspend(chip->bus);
2189 azx_stop_chip(chip);
2190 if (chip->irq >= 0) {
2191 free_irq(chip->irq, chip);
2192 chip->irq = -1;
2193 }
2194 if (chip->msi)
2195 pci_disable_msi(chip->pci);
2196 pci_disable_device(pci);
2197 pci_save_state(pci);
2198 pci_set_power_state(pci, pci_choose_state(pci, state));
2199 return 0;
2200 }
2201
2202 static int azx_resume(struct pci_dev *pci)
2203 {
2204 struct snd_card *card = pci_get_drvdata(pci);
2205 struct azx *chip = card->private_data;
2206
2207 pci_set_power_state(pci, PCI_D0);
2208 pci_restore_state(pci);
2209 if (pci_enable_device(pci) < 0) {
2210 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2211 "disabling device\n");
2212 snd_card_disconnect(card);
2213 return -EIO;
2214 }
2215 pci_set_master(pci);
2216 if (chip->msi)
2217 if (pci_enable_msi(pci) < 0)
2218 chip->msi = 0;
2219 if (azx_acquire_irq(chip, 1) < 0)
2220 return -EIO;
2221 azx_init_pci(chip);
2222
2223 if (snd_hda_codecs_inuse(chip->bus))
2224 azx_init_chip(chip, 1);
2225
2226 snd_hda_resume(chip->bus);
2227 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2228 return 0;
2229 }
2230 #endif /* CONFIG_PM */
2231
2232
2233 /*
2234 * reboot notifier for hang-up problem at power-down
2235 */
2236 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2237 {
2238 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2239 snd_hda_bus_reboot_notify(chip->bus);
2240 azx_stop_chip(chip);
2241 return NOTIFY_OK;
2242 }
2243
2244 static void azx_notifier_register(struct azx *chip)
2245 {
2246 chip->reboot_notifier.notifier_call = azx_halt;
2247 register_reboot_notifier(&chip->reboot_notifier);
2248 }
2249
2250 static void azx_notifier_unregister(struct azx *chip)
2251 {
2252 if (chip->reboot_notifier.notifier_call)
2253 unregister_reboot_notifier(&chip->reboot_notifier);
2254 }
2255
2256 /*
2257 * destructor
2258 */
2259 static int azx_free(struct azx *chip)
2260 {
2261 int i;
2262
2263 azx_notifier_unregister(chip);
2264
2265 if (chip->initialized) {
2266 azx_clear_irq_pending(chip);
2267 for (i = 0; i < chip->num_streams; i++)
2268 azx_stream_stop(chip, &chip->azx_dev[i]);
2269 azx_stop_chip(chip);
2270 }
2271
2272 if (chip->irq >= 0)
2273 free_irq(chip->irq, (void*)chip);
2274 if (chip->msi)
2275 pci_disable_msi(chip->pci);
2276 if (chip->remap_addr)
2277 iounmap(chip->remap_addr);
2278
2279 if (chip->azx_dev) {
2280 for (i = 0; i < chip->num_streams; i++)
2281 if (chip->azx_dev[i].bdl.area)
2282 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2283 }
2284 if (chip->rb.area)
2285 snd_dma_free_pages(&chip->rb);
2286 if (chip->posbuf.area)
2287 snd_dma_free_pages(&chip->posbuf);
2288 pci_release_regions(chip->pci);
2289 pci_disable_device(chip->pci);
2290 kfree(chip->azx_dev);
2291 kfree(chip);
2292
2293 return 0;
2294 }
2295
2296 static int azx_dev_free(struct snd_device *device)
2297 {
2298 return azx_free(device->device_data);
2299 }
2300
2301 /*
2302 * white/black-listing for position_fix
2303 */
2304 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2305 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2306 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2307 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2308 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2309 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2310 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2311 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2312 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2313 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2314 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2315 SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
2316 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2317 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2318 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2319 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2320 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2321 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2322 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2323 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2324 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2325 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2326 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2327 {}
2328 };
2329
2330 static int __devinit check_position_fix(struct azx *chip, int fix)
2331 {
2332 const struct snd_pci_quirk *q;
2333
2334 switch (fix) {
2335 case POS_FIX_LPIB:
2336 case POS_FIX_POSBUF:
2337 case POS_FIX_VIACOMBO:
2338 return fix;
2339 }
2340
2341 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2342 if (q) {
2343 printk(KERN_INFO
2344 "hda_intel: position_fix set to %d "
2345 "for device %04x:%04x\n",
2346 q->value, q->subvendor, q->subdevice);
2347 return q->value;
2348 }
2349
2350 /* Check VIA/ATI HD Audio Controller exist */
2351 switch (chip->driver_type) {
2352 case AZX_DRIVER_VIA:
2353 case AZX_DRIVER_ATI:
2354 /* Use link position directly, avoid any transfer problem. */
2355 return POS_FIX_VIACOMBO;
2356 }
2357
2358 return POS_FIX_AUTO;
2359 }
2360
2361 /*
2362 * black-lists for probe_mask
2363 */
2364 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2365 /* Thinkpad often breaks the controller communication when accessing
2366 * to the non-working (or non-existing) modem codec slot.
2367 */
2368 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2369 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2370 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2371 /* broken BIOS */
2372 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2373 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2374 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2375 /* forced codec slots */
2376 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2377 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2378 {}
2379 };
2380
2381 #define AZX_FORCE_CODEC_MASK 0x100
2382
2383 static void __devinit check_probe_mask(struct azx *chip, int dev)
2384 {
2385 const struct snd_pci_quirk *q;
2386
2387 chip->codec_probe_mask = probe_mask[dev];
2388 if (chip->codec_probe_mask == -1) {
2389 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2390 if (q) {
2391 printk(KERN_INFO
2392 "hda_intel: probe_mask set to 0x%x "
2393 "for device %04x:%04x\n",
2394 q->value, q->subvendor, q->subdevice);
2395 chip->codec_probe_mask = q->value;
2396 }
2397 }
2398
2399 /* check forced option */
2400 if (chip->codec_probe_mask != -1 &&
2401 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2402 chip->codec_mask = chip->codec_probe_mask & 0xff;
2403 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2404 chip->codec_mask);
2405 }
2406 }
2407
2408 /*
2409 * white/black-list for enable_msi
2410 */
2411 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2412 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2413 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2414 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2415 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2416 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2417 {}
2418 };
2419
2420 static void __devinit check_msi(struct azx *chip)
2421 {
2422 const struct snd_pci_quirk *q;
2423
2424 if (enable_msi >= 0) {
2425 chip->msi = !!enable_msi;
2426 return;
2427 }
2428 chip->msi = 1; /* enable MSI as default */
2429 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2430 if (q) {
2431 printk(KERN_INFO
2432 "hda_intel: msi for device %04x:%04x set to %d\n",
2433 q->subvendor, q->subdevice, q->value);
2434 chip->msi = q->value;
2435 return;
2436 }
2437
2438 /* NVidia chipsets seem to cause troubles with MSI */
2439 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2440 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2441 chip->msi = 0;
2442 }
2443 }
2444
2445
2446 /*
2447 * constructor
2448 */
2449 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2450 int dev, int driver_type,
2451 struct azx **rchip)
2452 {
2453 struct azx *chip;
2454 int i, err;
2455 unsigned short gcap;
2456 static struct snd_device_ops ops = {
2457 .dev_free = azx_dev_free,
2458 };
2459
2460 *rchip = NULL;
2461
2462 err = pci_enable_device(pci);
2463 if (err < 0)
2464 return err;
2465
2466 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2467 if (!chip) {
2468 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2469 pci_disable_device(pci);
2470 return -ENOMEM;
2471 }
2472
2473 spin_lock_init(&chip->reg_lock);
2474 mutex_init(&chip->open_mutex);
2475 chip->card = card;
2476 chip->pci = pci;
2477 chip->irq = -1;
2478 chip->driver_type = driver_type;
2479 check_msi(chip);
2480 chip->dev_index = dev;
2481 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2482
2483 chip->position_fix[0] = chip->position_fix[1] =
2484 check_position_fix(chip, position_fix[dev]);
2485 check_probe_mask(chip, dev);
2486
2487 chip->single_cmd = single_cmd;
2488
2489 if (bdl_pos_adj[dev] < 0) {
2490 switch (chip->driver_type) {
2491 case AZX_DRIVER_ICH:
2492 case AZX_DRIVER_PCH:
2493 bdl_pos_adj[dev] = 1;
2494 break;
2495 default:
2496 bdl_pos_adj[dev] = 32;
2497 break;
2498 }
2499 }
2500
2501 #if BITS_PER_LONG != 64
2502 /* Fix up base address on ULI M5461 */
2503 if (chip->driver_type == AZX_DRIVER_ULI) {
2504 u16 tmp3;
2505 pci_read_config_word(pci, 0x40, &tmp3);
2506 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2507 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2508 }
2509 #endif
2510
2511 err = pci_request_regions(pci, "ICH HD audio");
2512 if (err < 0) {
2513 kfree(chip);
2514 pci_disable_device(pci);
2515 return err;
2516 }
2517
2518 chip->addr = pci_resource_start(pci, 0);
2519 chip->remap_addr = pci_ioremap_bar(pci, 0);
2520 if (chip->remap_addr == NULL) {
2521 snd_printk(KERN_ERR SFX "ioremap error\n");
2522 err = -ENXIO;
2523 goto errout;
2524 }
2525
2526 if (chip->msi)
2527 if (pci_enable_msi(pci) < 0)
2528 chip->msi = 0;
2529
2530 if (azx_acquire_irq(chip, 0) < 0) {
2531 err = -EBUSY;
2532 goto errout;
2533 }
2534
2535 pci_set_master(pci);
2536 synchronize_irq(chip->irq);
2537
2538 gcap = azx_readw(chip, GCAP);
2539 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2540
2541 /* disable SB600 64bit support for safety */
2542 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2543 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2544 struct pci_dev *p_smbus;
2545 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2546 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2547 NULL);
2548 if (p_smbus) {
2549 if (p_smbus->revision < 0x30)
2550 gcap &= ~ICH6_GCAP_64OK;
2551 pci_dev_put(p_smbus);
2552 }
2553 }
2554
2555 /* disable 64bit DMA address for Teradici */
2556 /* it does not work with device 6549:1200 subsys e4a2:040b */
2557 if (chip->driver_type == AZX_DRIVER_TERA)
2558 gcap &= ~ICH6_GCAP_64OK;
2559
2560 /* allow 64bit DMA address if supported by H/W */
2561 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2562 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2563 else {
2564 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2565 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2566 }
2567
2568 /* read number of streams from GCAP register instead of using
2569 * hardcoded value
2570 */
2571 chip->capture_streams = (gcap >> 8) & 0x0f;
2572 chip->playback_streams = (gcap >> 12) & 0x0f;
2573 if (!chip->playback_streams && !chip->capture_streams) {
2574 /* gcap didn't give any info, switching to old method */
2575
2576 switch (chip->driver_type) {
2577 case AZX_DRIVER_ULI:
2578 chip->playback_streams = ULI_NUM_PLAYBACK;
2579 chip->capture_streams = ULI_NUM_CAPTURE;
2580 break;
2581 case AZX_DRIVER_ATIHDMI:
2582 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2583 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2584 break;
2585 case AZX_DRIVER_GENERIC:
2586 default:
2587 chip->playback_streams = ICH6_NUM_PLAYBACK;
2588 chip->capture_streams = ICH6_NUM_CAPTURE;
2589 break;
2590 }
2591 }
2592 chip->capture_index_offset = 0;
2593 chip->playback_index_offset = chip->capture_streams;
2594 chip->num_streams = chip->playback_streams + chip->capture_streams;
2595 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2596 GFP_KERNEL);
2597 if (!chip->azx_dev) {
2598 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2599 goto errout;
2600 }
2601
2602 for (i = 0; i < chip->num_streams; i++) {
2603 /* allocate memory for the BDL for each stream */
2604 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2605 snd_dma_pci_data(chip->pci),
2606 BDL_SIZE, &chip->azx_dev[i].bdl);
2607 if (err < 0) {
2608 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2609 goto errout;
2610 }
2611 }
2612 /* allocate memory for the position buffer */
2613 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2614 snd_dma_pci_data(chip->pci),
2615 chip->num_streams * 8, &chip->posbuf);
2616 if (err < 0) {
2617 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2618 goto errout;
2619 }
2620 /* allocate CORB/RIRB */
2621 err = azx_alloc_cmd_io(chip);
2622 if (err < 0)
2623 goto errout;
2624
2625 /* initialize streams */
2626 azx_init_stream(chip);
2627
2628 /* initialize chip */
2629 azx_init_pci(chip);
2630 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2631
2632 /* codec detection */
2633 if (!chip->codec_mask) {
2634 snd_printk(KERN_ERR SFX "no codecs found!\n");
2635 err = -ENODEV;
2636 goto errout;
2637 }
2638
2639 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2640 if (err <0) {
2641 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2642 goto errout;
2643 }
2644
2645 strcpy(card->driver, "HDA-Intel");
2646 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2647 sizeof(card->shortname));
2648 snprintf(card->longname, sizeof(card->longname),
2649 "%s at 0x%lx irq %i",
2650 card->shortname, chip->addr, chip->irq);
2651
2652 *rchip = chip;
2653 return 0;
2654
2655 errout:
2656 azx_free(chip);
2657 return err;
2658 }
2659
2660 static void power_down_all_codecs(struct azx *chip)
2661 {
2662 #ifdef CONFIG_SND_HDA_POWER_SAVE
2663 /* The codecs were powered up in snd_hda_codec_new().
2664 * Now all initialization done, so turn them down if possible
2665 */
2666 struct hda_codec *codec;
2667 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2668 snd_hda_power_down(codec);
2669 }
2670 #endif
2671 }
2672
2673 static int __devinit azx_probe(struct pci_dev *pci,
2674 const struct pci_device_id *pci_id)
2675 {
2676 static int dev;
2677 struct snd_card *card;
2678 struct azx *chip;
2679 int err;
2680
2681 if (dev >= SNDRV_CARDS)
2682 return -ENODEV;
2683 if (!enable[dev]) {
2684 dev++;
2685 return -ENOENT;
2686 }
2687
2688 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2689 if (err < 0) {
2690 snd_printk(KERN_ERR SFX "Error creating card!\n");
2691 return err;
2692 }
2693
2694 /* set this here since it's referred in snd_hda_load_patch() */
2695 snd_card_set_dev(card, &pci->dev);
2696
2697 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2698 if (err < 0)
2699 goto out_free;
2700 card->private_data = chip;
2701
2702 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2703 chip->beep_mode = beep_mode[dev];
2704 #endif
2705
2706 /* create codec instances */
2707 err = azx_codec_create(chip, model[dev]);
2708 if (err < 0)
2709 goto out_free;
2710 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2711 if (patch[dev] && *patch[dev]) {
2712 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2713 patch[dev]);
2714 err = snd_hda_load_patch(chip->bus, patch[dev]);
2715 if (err < 0)
2716 goto out_free;
2717 }
2718 #endif
2719 if ((probe_only[dev] & 1) == 0) {
2720 err = azx_codec_configure(chip);
2721 if (err < 0)
2722 goto out_free;
2723 }
2724
2725 /* create PCM streams */
2726 err = snd_hda_build_pcms(chip->bus);
2727 if (err < 0)
2728 goto out_free;
2729
2730 /* create mixer controls */
2731 err = azx_mixer_create(chip);
2732 if (err < 0)
2733 goto out_free;
2734
2735 err = snd_card_register(card);
2736 if (err < 0)
2737 goto out_free;
2738
2739 pci_set_drvdata(pci, card);
2740 chip->running = 1;
2741 power_down_all_codecs(chip);
2742 azx_notifier_register(chip);
2743
2744 dev++;
2745 return err;
2746 out_free:
2747 snd_card_free(card);
2748 return err;
2749 }
2750
2751 static void __devexit azx_remove(struct pci_dev *pci)
2752 {
2753 snd_card_free(pci_get_drvdata(pci));
2754 pci_set_drvdata(pci, NULL);
2755 }
2756
2757 /* PCI IDs */
2758 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2759 /* CPT */
2760 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2761 /* PBG */
2762 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
2763 /* Panther Point */
2764 { PCI_DEVICE(0x8086, 0x1e20), .driver_data = AZX_DRIVER_PCH },
2765 /* SCH */
2766 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2767 /* Generic Intel */
2768 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2769 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2770 .class_mask = 0xffffff,
2771 .driver_data = AZX_DRIVER_ICH },
2772 /* ATI SB 450/600 */
2773 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2774 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2775 /* ATI HDMI */
2776 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2777 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2778 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2779 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2780 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2781 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2782 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2783 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2784 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2785 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2786 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2787 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2788 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2789 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2790 /* VIA VT8251/VT8237A */
2791 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2792 /* SIS966 */
2793 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2794 /* ULI M5461 */
2795 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2796 /* NVIDIA MCP */
2797 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2798 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2799 .class_mask = 0xffffff,
2800 .driver_data = AZX_DRIVER_NVIDIA },
2801 /* Teradici */
2802 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2803 /* Creative X-Fi (CA0110-IBG) */
2804 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2805 /* the following entry conflicts with snd-ctxfi driver,
2806 * as ctxfi driver mutates from HD-audio to native mode with
2807 * a special command sequence.
2808 */
2809 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2810 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2811 .class_mask = 0xffffff,
2812 .driver_data = AZX_DRIVER_CTX },
2813 #else
2814 /* this entry seems still valid -- i.e. without emu20kx chip */
2815 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
2816 #endif
2817 /* Vortex86MX */
2818 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2819 /* VMware HDAudio */
2820 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2821 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2822 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2823 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2824 .class_mask = 0xffffff,
2825 .driver_data = AZX_DRIVER_GENERIC },
2826 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2827 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2828 .class_mask = 0xffffff,
2829 .driver_data = AZX_DRIVER_GENERIC },
2830 { 0, }
2831 };
2832 MODULE_DEVICE_TABLE(pci, azx_ids);
2833
2834 /* pci_driver definition */
2835 static struct pci_driver driver = {
2836 .name = "HDA Intel",
2837 .id_table = azx_ids,
2838 .probe = azx_probe,
2839 .remove = __devexit_p(azx_remove),
2840 #ifdef CONFIG_PM
2841 .suspend = azx_suspend,
2842 .resume = azx_resume,
2843 #endif
2844 };
2845
2846 static int __init alsa_card_azx_init(void)
2847 {
2848 return pci_register_driver(&driver);
2849 }
2850
2851 static void __exit alsa_card_azx_exit(void)
2852 {
2853 pci_unregister_driver(&driver);
2854 }
2855
2856 module_init(alsa_card_azx_init)
2857 module_exit(alsa_card_azx_exit)
linux-next