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Add linux-next specific files for 20110421
[linux-2.6/next.git] / sound / soc / codecs / wm8958-dsp2.c
blob74983ee2b87f52c0bebe8e168dc54f95e21805e7
1 /*
2 * wm8958-dsp2.c -- WM8958 DSP2 support
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <trace/events/asoc.h>
25
26 #include <linux/mfd/wm8994/core.h>
27 #include <linux/mfd/wm8994/registers.h>
28 #include <linux/mfd/wm8994/pdata.h>
29 #include <linux/mfd/wm8994/gpio.h>
30
31 #include "wm8994.h"
32
33 #define WM_FW_BLOCK_INFO 0xff
34 #define WM_FW_BLOCK_PM 0x00
35 #define WM_FW_BLOCK_X 0x01
36 #define WM_FW_BLOCK_Y 0x02
37 #define WM_FW_BLOCK_Z 0x03
38 #define WM_FW_BLOCK_I 0x06
39 #define WM_FW_BLOCK_A 0x08
40 #define WM_FW_BLOCK_C 0x0c
41
42 static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
43 const struct firmware *fw, bool check)
44 {
45 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
46 u64 data64;
47 u32 data32;
48 const u8 *data;
49 char *str;
50 size_t block_len, len;
51 int ret = 0;
52
53 /* Suppress unneeded downloads */
54 if (wm8994->cur_fw == fw)
55 return 0;
56
57 if (fw->size < 32) {
58 dev_err(codec->dev, "%s: firmware too short\n", name);
59 goto err;
60 }
61
62 if (memcmp(fw->data, "WMFW", 4) != 0) {
63 dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
64 name, data32);
65 goto err;
66 }
67
68 memcpy(&data32, fw->data + 4, sizeof(data32));
69 len = be32_to_cpu(data32);
70
71 memcpy(&data32, fw->data + 8, sizeof(data32));
72 data32 = be32_to_cpu(data32);
73 if ((data32 >> 24) & 0xff) {
74 dev_err(codec->dev, "%s: unsupported firmware version %d\n",
75 name, (data32 >> 24) & 0xff);
76 goto err;
77 }
78 if ((data32 & 0xffff) != 8958) {
79 dev_err(codec->dev, "%s: unsupported target device %d\n",
80 name, data32 & 0xffff);
81 goto err;
82 }
83 if (((data32 >> 16) & 0xff) != 0xc) {
84 dev_err(codec->dev, "%s: unsupported target core %d\n",
85 name, (data32 >> 16) & 0xff);
86 goto err;
87 }
88
89 if (check) {
90 memcpy(&data64, fw->data + 24, sizeof(u64));
91 dev_info(codec->dev, "%s timestamp %llx\n",
92 name, be64_to_cpu(data64));
93 } else {
94 snd_soc_write(codec, 0x102, 0x2);
95 snd_soc_write(codec, 0x900, 0x2);
96 }
97
98 data = fw->data + len;
99 len = fw->size - len;
100 while (len) {
101 if (len < 12) {
102 dev_err(codec->dev, "%s short data block of %d\n",
103 name, len);
104 goto err;
105 }
106
107 memcpy(&data32, data + 4, sizeof(data32));
108 block_len = be32_to_cpu(data32);
109 if (block_len + 8 > len) {
110 dev_err(codec->dev, "%d byte block longer than file\n",
111 block_len);
112 goto err;
113 }
114 if (block_len == 0) {
115 dev_err(codec->dev, "Zero length block\n");
116 goto err;
117 }
118
119 memcpy(&data32, data, sizeof(data32));
120 data32 = be32_to_cpu(data32);
121
122 switch ((data32 >> 24) & 0xff) {
123 case WM_FW_BLOCK_INFO:
124 /* Informational text */
125 if (!check)
126 break;
127
128 str = kzalloc(block_len + 1, GFP_KERNEL);
129 if (str) {
130 memcpy(str, data + 8, block_len);
131 dev_info(codec->dev, "%s: %s\n", name, str);
132 kfree(str);
133 } else {
134 dev_err(codec->dev, "Out of memory\n");
135 }
136 break;
137 case WM_FW_BLOCK_PM:
138 case WM_FW_BLOCK_X:
139 case WM_FW_BLOCK_Y:
140 case WM_FW_BLOCK_Z:
141 case WM_FW_BLOCK_I:
142 case WM_FW_BLOCK_A:
143 case WM_FW_BLOCK_C:
144 dev_dbg(codec->dev, "%s: %d bytes of %x@%x\n", name,
145 block_len, (data32 >> 24) & 0xff,
146 data32 & 0xffffff);
147
148 if (check)
149 break;
150
151 data32 &= 0xffffff;
152
153 wm8994_bulk_write(codec->control_data,
154 data32 & 0xffffff,
155 block_len / 2,
156 (void *)(data + 8));
157
158 break;
159 default:
160 dev_warn(codec->dev, "%s: unknown block type %d\n",
161 name, (data32 >> 24) & 0xff);
162 break;
163 }
164
165 /* Round up to the next 32 bit word */
166 block_len += block_len % 4;
167
168 data += block_len + 8;
169 len -= block_len + 8;
170 }
171
172 if (!check) {
173 dev_dbg(codec->dev, "%s: download done\n", name);
174 wm8994->cur_fw = fw;
175 } else {
176 dev_info(codec->dev, "%s: got firmware\n", name);
177 }
178
179 goto ok;
180
181 err:
182 ret = -EINVAL;
183 ok:
184 if (!check) {
185 snd_soc_write(codec, 0x900, 0x0);
186 snd_soc_write(codec, 0x102, 0x0);
187 }
188
189 return ret;
190 }
191
192 static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
193 {
194 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
195 struct wm8994_pdata *pdata = wm8994->pdata;
196 int i;
197
198 /* If the DSP is already running then noop */
199 if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
200 return;
201
202 /* If we have MBC firmware download it */
203 if (wm8994->mbc)
204 wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
205
206 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
207 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
208
209 /* If we've got user supplied MBC settings use them */
210 if (pdata && pdata->num_mbc_cfgs) {
211 struct wm8958_mbc_cfg *cfg
212 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
213
214 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
215 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
216 cfg->coeff_regs[i]);
217
218 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
219 snd_soc_write(codec,
220 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
221 cfg->cutoff_regs[i]);
222 }
223
224 /* Run the DSP */
225 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
226 WM8958_DSP2_RUNR);
227
228 /* And we're off! */
229 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
230 WM8958_MBC_ENA |
231 WM8958_MBC_SEL_MASK,
232 path << WM8958_MBC_SEL_SHIFT |
233 WM8958_MBC_ENA);
234 }
235
236 static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
237 {
238 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
239 struct wm8994_pdata *pdata = wm8994->pdata;
240 int i, ena;
241
242 if (wm8994->mbc_vss)
243 wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
244
245 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
246 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
247
248 /* If we've got user supplied settings use them */
249 if (pdata && pdata->num_mbc_cfgs) {
250 struct wm8958_mbc_cfg *cfg
251 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
252
253 for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
254 snd_soc_write(codec, i + 0x2800,
255 cfg->combined_regs[i]);
256 }
257
258 if (pdata && pdata->num_vss_cfgs) {
259 struct wm8958_vss_cfg *cfg
260 = &pdata->vss_cfgs[wm8994->vss_cfg];
261
262 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
263 snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
264 }
265
266 if (pdata && pdata->num_vss_hpf_cfgs) {
267 struct wm8958_vss_hpf_cfg *cfg
268 = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
269
270 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
271 snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
272 }
273
274 /* Run the DSP */
275 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
276 WM8958_DSP2_RUNR);
277
278 /* Enable the algorithms we've selected */
279 ena = 0;
280 if (wm8994->mbc_ena[path])
281 ena |= 0x8;
282 if (wm8994->hpf2_ena[path])
283 ena |= 0x4;
284 if (wm8994->hpf1_ena[path])
285 ena |= 0x2;
286 if (wm8994->vss_ena[path])
287 ena |= 0x1;
288
289 snd_soc_write(codec, 0x2201, ena);
290
291 /* Switch the DSP into the data path */
292 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
293 WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
294 path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
295 }
296
297 static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
298 {
299 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
300 struct wm8994_pdata *pdata = wm8994->pdata;
301 int i;
302
303 wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
304
305 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
306 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
307
308 /* If we've got user supplied settings use them */
309 if (pdata && pdata->num_enh_eq_cfgs) {
310 struct wm8958_enh_eq_cfg *cfg
311 = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
312
313 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
314 snd_soc_write(codec, i + 0x2200,
315 cfg->regs[i]);
316 }
317
318 /* Run the DSP */
319 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
320 WM8958_DSP2_RUNR);
321
322 /* Switch the DSP into the data path */
323 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
324 WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
325 path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
326 }
327
328 static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
329 {
330 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
331 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
332 int ena, reg, aif;
333
334 switch (path) {
335 case 0:
336 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
337 aif = 0;
338 break;
339 case 1:
340 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
341 aif = 0;
342 break;
343 case 2:
344 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
345 aif = 1;
346 break;
347 default:
348 BUG();
349 return;
350 }
351
352 /* Do we have both an active AIF and an active algorithm? */
353 ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
354 wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
355 wm8994->enh_eq_ena[path];
356 if (!pwr_reg)
357 ena = 0;
358
359 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
360
361 dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
362 path, wm8994->dsp_active, start, pwr_reg, reg);
363
364 if (start && ena) {
365 /* If either AIFnCLK is not yet enabled postpone */
366 if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
367 & WM8994_AIF1CLK_ENA_MASK) &&
368 !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
369 & WM8994_AIF2CLK_ENA_MASK))
370 return;
371
372 /* Switch the clock over to the appropriate AIF */
373 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
374 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
375 aif << WM8958_DSP2CLK_SRC_SHIFT |
376 WM8958_DSP2CLK_ENA);
377
378 if (wm8994->enh_eq_ena[path])
379 wm8958_dsp_start_enh_eq(codec, path);
380 else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
381 wm8994->hpf2_ena[path])
382 wm8958_dsp_start_vss(codec, path);
383 else if (wm8994->mbc_ena[path])
384 wm8958_dsp_start_mbc(codec, path);
385
386 wm8994->dsp_active = path;
387
388 dev_dbg(codec->dev, "DSP running in path %d\n", path);
389 }
390
391 if (!start && wm8994->dsp_active == path) {
392 /* If the DSP is already stopped then noop */
393 if (!(reg & WM8958_DSP2_ENA))
394 return;
395
396 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
397 WM8958_MBC_ENA, 0);
398 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
399 WM8958_DSP2_STOP);
400 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
401 WM8958_DSP2_ENA, 0);
402 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
403 WM8958_DSP2CLK_ENA, 0);
404
405 wm8994->dsp_active = -1;
406
407 dev_dbg(codec->dev, "DSP stopped\n");
408 }
409 }
410
411 int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
412 struct snd_kcontrol *kcontrol, int event)
413 {
414 struct snd_soc_codec *codec = w->codec;
415 int i;
416
417 switch (event) {
418 case SND_SOC_DAPM_POST_PMU:
419 case SND_SOC_DAPM_PRE_PMU:
420 for (i = 0; i < 3; i++)
421 wm8958_dsp_apply(codec, i, 1);
422 break;
423 case SND_SOC_DAPM_POST_PMD:
424 case SND_SOC_DAPM_PRE_PMD:
425 for (i = 0; i < 3; i++)
426 wm8958_dsp_apply(codec, i, 0);
427 break;
428 }
429
430 return 0;
431 }
432
433 /* Check if DSP2 is in use on another AIF */
434 static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
435 {
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
439 if (i == aif)
440 continue;
441 if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
442 wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
443 return 1;
444 }
445
446 return 0;
447 }
448
449 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451 {
452 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
453 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
454 struct wm8994_pdata *pdata = wm8994->pdata;
455 int value = ucontrol->value.integer.value[0];
456 int reg;
457
458 /* Don't allow on the fly reconfiguration */
459 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
460 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
461 return -EBUSY;
462
463 if (value >= pdata->num_mbc_cfgs)
464 return -EINVAL;
465
466 wm8994->mbc_cfg = value;
467
468 return 0;
469 }
470
471 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473 {
474 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
475 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
476
477 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
478
479 return 0;
480 }
481
482 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_info *uinfo)
484 {
485 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
486 uinfo->count = 1;
487 uinfo->value.integer.min = 0;
488 uinfo->value.integer.max = 1;
489 return 0;
490 }
491
492 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494 {
495 int mbc = kcontrol->private_value;
496 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
497 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
498
499 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
500
501 return 0;
502 }
503
504 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506 {
507 int mbc = kcontrol->private_value;
508 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
509 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
510
511 if (ucontrol->value.integer.value[0] > 1)
512 return -EINVAL;
513
514 if (wm8958_dsp2_busy(wm8994, mbc)) {
515 dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
516 return -EBUSY;
517 }
518
519 if (wm8994->enh_eq_ena[mbc])
520 return -EBUSY;
521
522 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
523
524 wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
525
526 return 0;
527 }
528
529 #define WM8958_MBC_SWITCH(xname, xval) {\
530 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
531 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
532 .info = wm8958_mbc_info, \
533 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
534 .private_value = xval }
535
536 static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
537 struct snd_ctl_elem_value *ucontrol)
538 {
539 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
540 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
541 struct wm8994_pdata *pdata = wm8994->pdata;
542 int value = ucontrol->value.integer.value[0];
543 int reg;
544
545 /* Don't allow on the fly reconfiguration */
546 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
547 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
548 return -EBUSY;
549
550 if (value >= pdata->num_vss_cfgs)
551 return -EINVAL;
552
553 wm8994->vss_cfg = value;
554
555 return 0;
556 }
557
558 static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
559 struct snd_ctl_elem_value *ucontrol)
560 {
561 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
562 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
563
564 ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
565
566 return 0;
567 }
568
569 static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
570 struct snd_ctl_elem_value *ucontrol)
571 {
572 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
573 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
574 struct wm8994_pdata *pdata = wm8994->pdata;
575 int value = ucontrol->value.integer.value[0];
576 int reg;
577
578 /* Don't allow on the fly reconfiguration */
579 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
580 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
581 return -EBUSY;
582
583 if (value >= pdata->num_vss_hpf_cfgs)
584 return -EINVAL;
585
586 wm8994->vss_hpf_cfg = value;
587
588 return 0;
589 }
590
591 static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
592 struct snd_ctl_elem_value *ucontrol)
593 {
594 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
595 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
596
597 ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
598
599 return 0;
600 }
601
602 static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
603 struct snd_ctl_elem_info *uinfo)
604 {
605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
606 uinfo->count = 1;
607 uinfo->value.integer.min = 0;
608 uinfo->value.integer.max = 1;
609 return 0;
610 }
611
612 static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
613 struct snd_ctl_elem_value *ucontrol)
614 {
615 int vss = kcontrol->private_value;
616 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
617 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
618
619 ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
620
621 return 0;
622 }
623
624 static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
625 struct snd_ctl_elem_value *ucontrol)
626 {
627 int vss = kcontrol->private_value;
628 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
629 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
630
631 if (ucontrol->value.integer.value[0] > 1)
632 return -EINVAL;
633
634 if (!wm8994->mbc_vss)
635 return -ENODEV;
636
637 if (wm8958_dsp2_busy(wm8994, vss)) {
638 dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
639 return -EBUSY;
640 }
641
642 if (wm8994->enh_eq_ena[vss])
643 return -EBUSY;
644
645 wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
646
647 wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
648
649 return 0;
650 }
651
652
653 #define WM8958_VSS_SWITCH(xname, xval) {\
654 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
655 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
656 .info = wm8958_vss_info, \
657 .get = wm8958_vss_get, .put = wm8958_vss_put, \
658 .private_value = xval }
659
660 static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
661 struct snd_ctl_elem_info *uinfo)
662 {
663 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
664 uinfo->count = 1;
665 uinfo->value.integer.min = 0;
666 uinfo->value.integer.max = 1;
667 return 0;
668 }
669
670 static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
671 struct snd_ctl_elem_value *ucontrol)
672 {
673 int hpf = kcontrol->private_value;
674 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
675 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
676
677 if (hpf < 3)
678 ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
679 else
680 ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
681
682 return 0;
683 }
684
685 static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
686 struct snd_ctl_elem_value *ucontrol)
687 {
688 int hpf = kcontrol->private_value;
689 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
690 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
691
692 if (ucontrol->value.integer.value[0] > 1)
693 return -EINVAL;
694
695 if (!wm8994->mbc_vss)
696 return -ENODEV;
697
698 if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
699 dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
700 return -EBUSY;
701 }
702
703 if (wm8994->enh_eq_ena[hpf % 3])
704 return -EBUSY;
705
706 if (hpf < 3)
707 wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
708 else
709 wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
710
711 wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
712
713 return 0;
714 }
715
716 #define WM8958_HPF_SWITCH(xname, xval) {\
717 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
718 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
719 .info = wm8958_hpf_info, \
720 .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
721 .private_value = xval }
722
723 static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
724 struct snd_ctl_elem_value *ucontrol)
725 {
726 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
727 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
728 struct wm8994_pdata *pdata = wm8994->pdata;
729 int value = ucontrol->value.integer.value[0];
730 int reg;
731
732 /* Don't allow on the fly reconfiguration */
733 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
734 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
735 return -EBUSY;
736
737 if (value >= pdata->num_enh_eq_cfgs)
738 return -EINVAL;
739
740 wm8994->enh_eq_cfg = value;
741
742 return 0;
743 }
744
745 static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
746 struct snd_ctl_elem_value *ucontrol)
747 {
748 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
749 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
750
751 ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
752
753 return 0;
754 }
755
756 static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_info *uinfo)
758 {
759 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
760 uinfo->count = 1;
761 uinfo->value.integer.min = 0;
762 uinfo->value.integer.max = 1;
763 return 0;
764 }
765
766 static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
767 struct snd_ctl_elem_value *ucontrol)
768 {
769 int eq = kcontrol->private_value;
770 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
773 ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
774
775 return 0;
776 }
777
778 static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
779 struct snd_ctl_elem_value *ucontrol)
780 {
781 int eq = kcontrol->private_value;
782 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
783 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784
785 if (ucontrol->value.integer.value[0] > 1)
786 return -EINVAL;
787
788 if (!wm8994->enh_eq)
789 return -ENODEV;
790
791 if (wm8958_dsp2_busy(wm8994, eq)) {
792 dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
793 return -EBUSY;
794 }
795
796 if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
797 wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
798 return -EBUSY;
799
800 wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
801
802 wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
803
804 return 0;
805 }
806
807 #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
808 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
809 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
810 .info = wm8958_enh_eq_info, \
811 .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
812 .private_value = xval }
813
814 static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
815 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
816 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
817 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
818 };
819
820 static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
821 WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
822 WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
823 WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
824 WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
825 WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
826 WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
827 WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
828 WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
829 WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
830 };
831
832 static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
833 WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
834 WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
835 WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
836 };
837
838 static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
839 {
840 struct snd_soc_codec *codec = context;
841 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
842
843 if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
844 mutex_lock(&codec->mutex);
845 wm8994->enh_eq = fw;
846 mutex_unlock(&codec->mutex);
847 }
848 }
849
850 static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
851 {
852 struct snd_soc_codec *codec = context;
853 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
854
855 if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
856 mutex_lock(&codec->mutex);
857 wm8994->mbc_vss = fw;
858 mutex_unlock(&codec->mutex);
859 }
860
861 /* We can't have more than one request outstanding at once so
862 * we daisy chain.
863 */
864 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
865 "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
866 codec, wm8958_enh_eq_loaded);
867 }
868
869 static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
870 {
871 struct snd_soc_codec *codec = context;
872 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
873
874 if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
875 return;
876
877 mutex_lock(&codec->mutex);
878 wm8994->mbc = fw;
879 mutex_unlock(&codec->mutex);
880
881 /* We can't have more than one request outstanding at once so
882 * we daisy chain.
883 */
884 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
885 "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
886 codec, wm8958_mbc_vss_loaded);
887 }
888
889 void wm8958_dsp2_init(struct snd_soc_codec *codec)
890 {
891 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
892 struct wm8994_pdata *pdata = wm8994->pdata;
893 int ret, i;
894
895 wm8994->dsp_active = -1;
896
897 snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
898 ARRAY_SIZE(wm8958_mbc_snd_controls));
899 snd_soc_add_controls(codec, wm8958_vss_snd_controls,
900 ARRAY_SIZE(wm8958_vss_snd_controls));
901 snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
902 ARRAY_SIZE(wm8958_enh_eq_snd_controls));
903
904
905 /* We don't *require* firmware and don't want to delay boot */
906 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
907 "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
908 codec, wm8958_mbc_loaded);
909
910 if (!pdata)
911 return;
912
913 if (pdata->num_mbc_cfgs) {
914 struct snd_kcontrol_new control[] = {
915 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
916 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
917 };
918
919 /* We need an array of texts for the enum API */
920 wm8994->mbc_texts = kmalloc(sizeof(char *)
921 * pdata->num_mbc_cfgs, GFP_KERNEL);
922 if (!wm8994->mbc_texts) {
923 dev_err(wm8994->codec->dev,
924 "Failed to allocate %d MBC config texts\n",
925 pdata->num_mbc_cfgs);
926 return;
927 }
928
929 for (i = 0; i < pdata->num_mbc_cfgs; i++)
930 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
931
932 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
933 wm8994->mbc_enum.texts = wm8994->mbc_texts;
934
935 ret = snd_soc_add_controls(wm8994->codec, control, 1);
936 if (ret != 0)
937 dev_err(wm8994->codec->dev,
938 "Failed to add MBC mode controls: %d\n", ret);
939 }
940
941 if (pdata->num_vss_cfgs) {
942 struct snd_kcontrol_new control[] = {
943 SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
944 wm8958_get_vss_enum, wm8958_put_vss_enum),
945 };
946
947 /* We need an array of texts for the enum API */
948 wm8994->vss_texts = kmalloc(sizeof(char *)
949 * pdata->num_vss_cfgs, GFP_KERNEL);
950 if (!wm8994->vss_texts) {
951 dev_err(wm8994->codec->dev,
952 "Failed to allocate %d VSS config texts\n",
953 pdata->num_vss_cfgs);
954 return;
955 }
956
957 for (i = 0; i < pdata->num_vss_cfgs; i++)
958 wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
959
960 wm8994->vss_enum.max = pdata->num_vss_cfgs;
961 wm8994->vss_enum.texts = wm8994->vss_texts;
962
963 ret = snd_soc_add_controls(wm8994->codec, control, 1);
964 if (ret != 0)
965 dev_err(wm8994->codec->dev,
966 "Failed to add VSS mode controls: %d\n", ret);
967 }
968
969 if (pdata->num_vss_hpf_cfgs) {
970 struct snd_kcontrol_new control[] = {
971 SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
972 wm8958_get_vss_hpf_enum,
973 wm8958_put_vss_hpf_enum),
974 };
975
976 /* We need an array of texts for the enum API */
977 wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
978 * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
979 if (!wm8994->vss_hpf_texts) {
980 dev_err(wm8994->codec->dev,
981 "Failed to allocate %d VSS HPF config texts\n",
982 pdata->num_vss_hpf_cfgs);
983 return;
984 }
985
986 for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
987 wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
988
989 wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
990 wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
991
992 ret = snd_soc_add_controls(wm8994->codec, control, 1);
993 if (ret != 0)
994 dev_err(wm8994->codec->dev,
995 "Failed to add VSS HPFmode controls: %d\n",
996 ret);
997 }
998
999 if (pdata->num_enh_eq_cfgs) {
1000 struct snd_kcontrol_new control[] = {
1001 SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
1002 wm8958_get_enh_eq_enum,
1003 wm8958_put_enh_eq_enum),
1004 };
1005
1006 /* We need an array of texts for the enum API */
1007 wm8994->enh_eq_texts = kmalloc(sizeof(char *)
1008 * pdata->num_enh_eq_cfgs, GFP_KERNEL);
1009 if (!wm8994->enh_eq_texts) {
1010 dev_err(wm8994->codec->dev,
1011 "Failed to allocate %d enhanced EQ config texts\n",
1012 pdata->num_enh_eq_cfgs);
1013 return;
1014 }
1015
1016 for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
1017 wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
1018
1019 wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
1020 wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
1021
1022 ret = snd_soc_add_controls(wm8994->codec, control, 1);
1023 if (ret != 0)
1024 dev_err(wm8994->codec->dev,
1025 "Failed to add enhanced EQ controls: %d\n",
1026 ret);
1027 }
1028 }
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