include/linux/usb/r8a66597.h

   1 /*
   2  * R8A66597 driver platform data
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  *
   6  * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  *
  21  */
  22
  23 #ifndef __LINUX_USB_R8A66597_H
  24 #define __LINUX_USB_R8A66597_H
  25
  26 #define R8A66597_PLATDATA_XTAL_12MHZ    0x01
  27 #define R8A66597_PLATDATA_XTAL_24MHZ    0x02
  28 #define R8A66597_PLATDATA_XTAL_48MHZ    0x03
  29
  30 struct r8a66597_platdata {
  31         /* This callback can control port power instead of DVSTCTR register. */
  32         void (*port_power)(int port, int power);
  33
  34         /* set one = on chip controller, set zero = external controller */
  35         unsigned        on_chip:1;
  36
  37         /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
  38         unsigned        xtal:2;
  39
  40         /* set one = 3.3V, set zero = 1.5V */
  41         unsigned        vif:1;
  42
  43         /* set one = big endian, set zero = little endian */
  44         unsigned        endian:1;
  45 };
  46
  47 /* Register definitions */
  48 #define SYSCFG0         0x00
  49 #define SYSCFG1         0x02
  50 #define SYSSTS0         0x04
  51 #define SYSSTS1         0x06
  52 #define DVSTCTR0        0x08
  53 #define DVSTCTR1        0x0A
  54 #define TESTMODE        0x0C
  55 #define PINCFG          0x0E
  56 #define DMA0CFG         0x10
  57 #define DMA1CFG         0x12
  58 #define CFIFO           0x14
  59 #define D0FIFO          0x18
  60 #define D1FIFO          0x1C
  61 #define CFIFOSEL        0x20
  62 #define CFIFOCTR        0x22
  63 #define CFIFOSIE        0x24
  64 #define D0FIFOSEL       0x28
  65 #define D0FIFOCTR       0x2A
  66 #define D1FIFOSEL       0x2C
  67 #define D1FIFOCTR       0x2E
  68 #define INTENB0         0x30
  69 #define INTENB1         0x32
  70 #define INTENB2         0x34
  71 #define BRDYENB         0x36
  72 #define NRDYENB         0x38
  73 #define BEMPENB         0x3A
  74 #define SOFCFG          0x3C
  75 #define INTSTS0         0x40
  76 #define INTSTS1         0x42
  77 #define INTSTS2         0x44
  78 #define BRDYSTS         0x46
  79 #define NRDYSTS         0x48
  80 #define BEMPSTS         0x4A
  81 #define FRMNUM          0x4C
  82 #define UFRMNUM         0x4E
  83 #define USBADDR         0x50
  84 #define USBREQ          0x54
  85 #define USBVAL          0x56
  86 #define USBINDX         0x58
  87 #define USBLENG         0x5A
  88 #define DCPCFG          0x5C
  89 #define DCPMAXP         0x5E
  90 #define DCPCTR          0x60
  91 #define PIPESEL         0x64
  92 #define PIPECFG         0x68
  93 #define PIPEBUF         0x6A
  94 #define PIPEMAXP        0x6C
  95 #define PIPEPERI        0x6E
  96 #define PIPE1CTR        0x70
  97 #define PIPE2CTR        0x72
  98 #define PIPE3CTR        0x74
  99 #define PIPE4CTR        0x76
 100 #define PIPE5CTR        0x78
 101 #define PIPE6CTR        0x7A
 102 #define PIPE7CTR        0x7C
 103 #define PIPE8CTR        0x7E
 104 #define PIPE9CTR        0x80
 105 #define PIPE1TRE        0x90
 106 #define PIPE1TRN        0x92
 107 #define PIPE2TRE        0x94
 108 #define PIPE2TRN        0x96
 109 #define PIPE3TRE        0x98
 110 #define PIPE3TRN        0x9A
 111 #define PIPE4TRE        0x9C
 112 #define PIPE4TRN        0x9E
 113 #define PIPE5TRE        0xA0
 114 #define PIPE5TRN        0xA2
 115 #define DEVADD0         0xD0
 116 #define DEVADD1         0xD2
 117 #define DEVADD2         0xD4
 118 #define DEVADD3         0xD6
 119 #define DEVADD4         0xD8
 120 #define DEVADD5         0xDA
 121 #define DEVADD6         0xDC
 122 #define DEVADD7         0xDE
 123 #define DEVADD8         0xE0
 124 #define DEVADD9         0xE2
 125 #define DEVADDA         0xE4
 126
 127 /* System Configuration Control Register */
 128 #define XTAL            0xC000  /* b15-14: Crystal selection */
 129 #define   XTAL48         0x8000   /* 48MHz */
 130 #define   XTAL24         0x4000   /* 24MHz */
 131 #define   XTAL12         0x0000   /* 12MHz */
 132 #define XCKE            0x2000  /* b13: External clock enable */
 133 #define PLLC            0x0800  /* b11: PLL control */
 134 #define SCKE            0x0400  /* b10: USB clock enable */
 135 #define PCSDIS          0x0200  /* b9: not CS wakeup */
 136 #define LPSME           0x0100  /* b8: Low power sleep mode */
 137 #define HSE             0x0080  /* b7: Hi-speed enable */
 138 #define DCFM            0x0040  /* b6: Controller function select  */
 139 #define DRPD            0x0020  /* b5: D+/- pull down control */
 140 #define DPRPU           0x0010  /* b4: D+ pull up control */
 141 #define USBE            0x0001  /* b0: USB module operation enable */
 142
 143 /* System Configuration Status Register */
 144 #define OVCBIT          0x8000  /* b15-14: Over-current bit */
 145 #define OVCMON          0xC000  /* b15-14: Over-current monitor */
 146 #define SOFEA           0x0020  /* b5: SOF monitor */
 147 #define IDMON           0x0004  /* b3: ID-pin monitor */
 148 #define LNST            0x0003  /* b1-0: D+, D- line status */
 149 #define   SE1            0x0003   /* SE1 */
 150 #define   FS_KSTS        0x0002   /* Full-Speed K State */
 151 #define   FS_JSTS        0x0001   /* Full-Speed J State */
 152 #define   LS_JSTS        0x0002   /* Low-Speed J State */
 153 #define   LS_KSTS        0x0001   /* Low-Speed K State */
 154 #define   SE0            0x0000   /* SE0 */
 155
 156 /* Device State Control Register */
 157 #define EXTLP0          0x0400  /* b10: External port */
 158 #define VBOUT           0x0200  /* b9: VBUS output */
 159 #define WKUP            0x0100  /* b8: Remote wakeup */
 160 #define RWUPE           0x0080  /* b7: Remote wakeup sense */
 161 #define USBRST          0x0040  /* b6: USB reset enable */
 162 #define RESUME          0x0020  /* b5: Resume enable */
 163 #define UACT            0x0010  /* b4: USB bus enable */
 164 #define RHST            0x0007  /* b1-0: Reset handshake status */
 165 #define   HSPROC         0x0004   /* HS handshake is processing */
 166 #define   HSMODE         0x0003   /* Hi-Speed mode */
 167 #define   FSMODE         0x0002   /* Full-Speed mode */
 168 #define   LSMODE         0x0001   /* Low-Speed mode */
 169 #define   UNDECID        0x0000   /* Undecided */
 170
 171 /* Test Mode Register */
 172 #define UTST                    0x000F  /* b3-0: Test select */
 173 #define   H_TST_PACKET           0x000C   /* HOST TEST Packet */
 174 #define   H_TST_SE0_NAK          0x000B   /* HOST TEST SE0 NAK */
 175 #define   H_TST_K                0x000A   /* HOST TEST K */
 176 #define   H_TST_J                0x0009   /* HOST TEST J */
 177 #define   H_TST_NORMAL           0x0000   /* HOST Normal Mode */
 178 #define   P_TST_PACKET           0x0004   /* PERI TEST Packet */
 179 #define   P_TST_SE0_NAK          0x0003   /* PERI TEST SE0 NAK */
 180 #define   P_TST_K                0x0002   /* PERI TEST K */
 181 #define   P_TST_J                0x0001   /* PERI TEST J */
 182 #define   P_TST_NORMAL           0x0000   /* PERI Normal Mode */
 183
 184 /* Data Pin Configuration Register */
 185 #define LDRV                    0x8000  /* b15: Drive Current Adjust */
 186 #define   VIF1                    0x0000                /* VIF = 1.8V */
 187 #define   VIF3                    0x8000                /* VIF = 3.3V */
 188 #define INTA                    0x0001  /* b1: USB INT-pin active */
 189
 190 /* DMAx Pin Configuration Register */
 191 #define DREQA                   0x4000  /* b14: Dreq active select */
 192 #define BURST                   0x2000  /* b13: Burst mode */
 193 #define DACKA                   0x0400  /* b10: Dack active select */
 194 #define DFORM                   0x0380  /* b9-7: DMA mode select */
 195 #define   CPU_ADR_RD_WR          0x0000   /* Address + RD/WR mode (CPU bus) */
 196 #define   CPU_DACK_RD_WR         0x0100   /* DACK + RD/WR mode (CPU bus) */
 197 #define   CPU_DACK_ONLY          0x0180   /* DACK only mode (CPU bus) */
 198 #define   SPLIT_DACK_ONLY        0x0200   /* DACK only mode (SPLIT bus) */
 199 #define DENDA                   0x0040  /* b6: Dend active select */
 200 #define PKTM                    0x0020  /* b5: Packet mode */
 201 #define DENDE                   0x0010  /* b4: Dend enable */
 202 #define OBUS                    0x0004  /* b2: OUTbus mode */
 203
 204 /* CFIFO/DxFIFO Port Select Register */
 205 #define RCNT            0x8000  /* b15: Read count mode */
 206 #define REW             0x4000  /* b14: Buffer rewind */
 207 #define DCLRM           0x2000  /* b13: DMA buffer clear mode */
 208 #define DREQE           0x1000  /* b12: DREQ output enable */
 209 #define   MBW_8          0x0000   /*  8bit */
 210 #define   MBW_16         0x0400   /* 16bit */
 211 #define   MBW_32         0x0800   /* 32bit */
 212 #define BIGEND          0x0100  /* b8: Big endian mode */
 213 #define   BYTE_LITTLE    0x0000         /* little dendian */
 214 #define   BYTE_BIG       0x0100         /* big endifan */
 215 #define ISEL            0x0020  /* b5: DCP FIFO port direction select */
 216 #define CURPIPE         0x000F  /* b2-0: PIPE select */
 217
 218 /* CFIFO/DxFIFO Port Control Register */
 219 #define BVAL            0x8000  /* b15: Buffer valid flag */
 220 #define BCLR            0x4000  /* b14: Buffer clear */
 221 #define FRDY            0x2000  /* b13: FIFO ready */
 222 #define DTLN            0x0FFF  /* b11-0: FIFO received data length */
 223
 224 /* Interrupt Enable Register 0 */
 225 #define VBSE    0x8000  /* b15: VBUS interrupt */
 226 #define RSME    0x4000  /* b14: Resume interrupt */
 227 #define SOFE    0x2000  /* b13: Frame update interrupt */
 228 #define DVSE    0x1000  /* b12: Device state transition interrupt */
 229 #define CTRE    0x0800  /* b11: Control transfer stage transition interrupt */
 230 #define BEMPE   0x0400  /* b10: Buffer empty interrupt */
 231 #define NRDYE   0x0200  /* b9: Buffer not ready interrupt */
 232 #define BRDYE   0x0100  /* b8: Buffer ready interrupt */
 233
 234 /* Interrupt Enable Register 1 */
 235 #define OVRCRE          0x8000  /* b15: Over-current interrupt */
 236 #define BCHGE           0x4000  /* b14: USB us chenge interrupt */
 237 #define DTCHE           0x1000  /* b12: Detach sense interrupt */
 238 #define ATTCHE          0x0800  /* b11: Attach sense interrupt */
 239 #define EOFERRE         0x0040  /* b6: EOF error interrupt */
 240 #define SIGNE           0x0020  /* b5: SETUP IGNORE interrupt */
 241 #define SACKE           0x0010  /* b4: SETUP ACK interrupt */
 242
 243 /* BRDY Interrupt Enable/Status Register */
 244 #define BRDY9           0x0200  /* b9: PIPE9 */
 245 #define BRDY8           0x0100  /* b8: PIPE8 */
 246 #define BRDY7           0x0080  /* b7: PIPE7 */
 247 #define BRDY6           0x0040  /* b6: PIPE6 */
 248 #define BRDY5           0x0020  /* b5: PIPE5 */
 249 #define BRDY4           0x0010  /* b4: PIPE4 */
 250 #define BRDY3           0x0008  /* b3: PIPE3 */
 251 #define BRDY2           0x0004  /* b2: PIPE2 */
 252 #define BRDY1           0x0002  /* b1: PIPE1 */
 253 #define BRDY0           0x0001  /* b1: PIPE0 */
 254
 255 /* NRDY Interrupt Enable/Status Register */
 256 #define NRDY9           0x0200  /* b9: PIPE9 */
 257 #define NRDY8           0x0100  /* b8: PIPE8 */
 258 #define NRDY7           0x0080  /* b7: PIPE7 */
 259 #define NRDY6           0x0040  /* b6: PIPE6 */
 260 #define NRDY5           0x0020  /* b5: PIPE5 */
 261 #define NRDY4           0x0010  /* b4: PIPE4 */
 262 #define NRDY3           0x0008  /* b3: PIPE3 */
 263 #define NRDY2           0x0004  /* b2: PIPE2 */
 264 #define NRDY1           0x0002  /* b1: PIPE1 */
 265 #define NRDY0           0x0001  /* b1: PIPE0 */
 266
 267 /* BEMP Interrupt Enable/Status Register */
 268 #define BEMP9           0x0200  /* b9: PIPE9 */
 269 #define BEMP8           0x0100  /* b8: PIPE8 */
 270 #define BEMP7           0x0080  /* b7: PIPE7 */
 271 #define BEMP6           0x0040  /* b6: PIPE6 */
 272 #define BEMP5           0x0020  /* b5: PIPE5 */
 273 #define BEMP4           0x0010  /* b4: PIPE4 */
 274 #define BEMP3           0x0008  /* b3: PIPE3 */
 275 #define BEMP2           0x0004  /* b2: PIPE2 */
 276 #define BEMP1           0x0002  /* b1: PIPE1 */
 277 #define BEMP0           0x0001  /* b0: PIPE0 */
 278
 279 /* SOF Pin Configuration Register */
 280 #define TRNENSEL        0x0100  /* b8: Select transaction enable period */
 281 #define BRDYM           0x0040  /* b6: BRDY clear timing */
 282 #define INTL            0x0020  /* b5: Interrupt sense select */
 283 #define EDGESTS         0x0010  /* b4:  */
 284 #define SOFMODE         0x000C  /* b3-2: SOF pin select */
 285 #define   SOF_125US      0x0008   /* SOF OUT 125us Frame Signal */
 286 #define   SOF_1MS        0x0004   /* SOF OUT 1ms Frame Signal */
 287 #define   SOF_DISABLE    0x0000   /* SOF OUT Disable */
 288
 289 /* Interrupt Status Register 0 */
 290 #define VBINT   0x8000  /* b15: VBUS interrupt */
 291 #define RESM    0x4000  /* b14: Resume interrupt */
 292 #define SOFR    0x2000  /* b13: SOF frame update interrupt */
 293 #define DVST    0x1000  /* b12: Device state transition interrupt */
 294 #define CTRT    0x0800  /* b11: Control transfer stage transition interrupt */
 295 #define BEMP    0x0400  /* b10: Buffer empty interrupt */
 296 #define NRDY    0x0200  /* b9: Buffer not ready interrupt */
 297 #define BRDY    0x0100  /* b8: Buffer ready interrupt */
 298 #define VBSTS   0x0080  /* b7: VBUS input port */
 299 #define DVSQ    0x0070  /* b6-4: Device state */
 300 #define   DS_SPD_CNFG    0x0070   /* Suspend Configured */
 301 #define   DS_SPD_ADDR    0x0060   /* Suspend Address */
 302 #define   DS_SPD_DFLT    0x0050   /* Suspend Default */
 303 #define   DS_SPD_POWR    0x0040   /* Suspend Powered */
 304 #define   DS_SUSP        0x0040   /* Suspend */
 305 #define   DS_CNFG        0x0030   /* Configured */
 306 #define   DS_ADDS        0x0020   /* Address */
 307 #define   DS_DFLT        0x0010   /* Default */
 308 #define   DS_POWR        0x0000   /* Powered */
 309 #define DVSQS           0x0030  /* b5-4: Device state */
 310 #define VALID           0x0008  /* b3: Setup packet detected flag */
 311 #define CTSQ            0x0007  /* b2-0: Control transfer stage */
 312 #define   CS_SQER        0x0006   /* Sequence error */
 313 #define   CS_WRND        0x0005   /* Control write nodata status stage */
 314 #define   CS_WRSS        0x0004   /* Control write status stage */
 315 #define   CS_WRDS        0x0003   /* Control write data stage */
 316 #define   CS_RDSS        0x0002   /* Control read status stage */
 317 #define   CS_RDDS        0x0001   /* Control read data stage */
 318 #define   CS_IDST        0x0000   /* Idle or setup stage */
 319
 320 /* Interrupt Status Register 1 */
 321 #define OVRCR           0x8000  /* b15: Over-current interrupt */
 322 #define BCHG            0x4000  /* b14: USB bus chenge interrupt */
 323 #define DTCH            0x1000  /* b12: Detach sense interrupt */
 324 #define ATTCH           0x0800  /* b11: Attach sense interrupt */
 325 #define EOFERR          0x0040  /* b6: EOF-error interrupt */
 326 #define SIGN            0x0020  /* b5: Setup ignore interrupt */
 327 #define SACK            0x0010  /* b4: Setup acknowledge interrupt */
 328
 329 /* Frame Number Register */
 330 #define OVRN            0x8000  /* b15: Overrun error */
 331 #define CRCE            0x4000  /* b14: Received data error */
 332 #define FRNM            0x07FF  /* b10-0: Frame number */
 333
 334 /* Micro Frame Number Register */
 335 #define UFRNM           0x0007  /* b2-0: Micro frame number */
 336
 337 /* Default Control Pipe Maxpacket Size Register */
 338 /* Pipe Maxpacket Size Register */
 339 #define DEVSEL  0xF000  /* b15-14: Device address select */
 340 #define MAXP    0x007F  /* b6-0: Maxpacket size of default control pipe */
 341
 342 /* Default Control Pipe Control Register */
 343 #define BSTS            0x8000  /* b15: Buffer status */
 344 #define SUREQ           0x4000  /* b14: Send USB request  */
 345 #define CSCLR           0x2000  /* b13: complete-split status clear */
 346 #define CSSTS           0x1000  /* b12: complete-split status */
 347 #define SUREQCLR        0x0800  /* b11: stop setup request */
 348 #define SQCLR           0x0100  /* b8: Sequence toggle bit clear */
 349 #define SQSET           0x0080  /* b7: Sequence toggle bit set */
 350 #define SQMON           0x0040  /* b6: Sequence toggle bit monitor */
 351 #define PBUSY           0x0020  /* b5: pipe busy */
 352 #define PINGE           0x0010  /* b4: ping enable */
 353 #define CCPL            0x0004  /* b2: Enable control transfer complete */
 354 #define PID             0x0003  /* b1-0: Response PID */
 355 #define   PID_STALL11    0x0003   /* STALL */
 356 #define   PID_STALL      0x0002   /* STALL */
 357 #define   PID_BUF        0x0001   /* BUF */
 358 #define   PID_NAK        0x0000   /* NAK */
 359
 360 /* Pipe Window Select Register */
 361 #define PIPENM          0x0007  /* b2-0: Pipe select */
 362
 363 /* Pipe Configuration Register */
 364 #define R8A66597_TYP    0xC000  /* b15-14: Transfer type */
 365 #define   R8A66597_ISO   0xC000           /* Isochronous */
 366 #define   R8A66597_INT   0x8000           /* Interrupt */
 367 #define   R8A66597_BULK  0x4000           /* Bulk */
 368 #define R8A66597_BFRE   0x0400  /* b10: Buffer ready interrupt mode select */
 369 #define R8A66597_DBLB   0x0200  /* b9: Double buffer mode select */
 370 #define R8A66597_CNTMD  0x0100  /* b8: Continuous transfer mode select */
 371 #define R8A66597_SHTNAK 0x0080  /* b7: Transfer end NAK */
 372 #define R8A66597_DIR    0x0010  /* b4: Transfer direction select */
 373 #define R8A66597_EPNUM  0x000F  /* b3-0: Eendpoint number select */
 374
 375 /* Pipe Buffer Configuration Register */
 376 #define BUFSIZE         0x7C00  /* b14-10: Pipe buffer size */
 377 #define BUFNMB          0x007F  /* b6-0: Pipe buffer number */
 378 #define PIPE0BUF        256
 379 #define PIPExBUF        64
 380
 381 /* Pipe Maxpacket Size Register */
 382 #define MXPS            0x07FF  /* b10-0: Maxpacket size */
 383
 384 /* Pipe Cycle Configuration Register */
 385 #define IFIS    0x1000  /* b12: Isochronous in-buffer flush mode select */
 386 #define IITV    0x0007  /* b2-0: Isochronous interval */
 387
 388 /* Pipex Control Register */
 389 #define BSTS    0x8000  /* b15: Buffer status */
 390 #define INBUFM  0x4000  /* b14: IN buffer monitor (Only for PIPE1 to 5) */
 391 #define CSCLR   0x2000  /* b13: complete-split status clear */
 392 #define CSSTS   0x1000  /* b12: complete-split status */
 393 #define ATREPM  0x0400  /* b10: Auto repeat mode */
 394 #define ACLRM   0x0200  /* b9: Out buffer auto clear mode */
 395 #define SQCLR   0x0100  /* b8: Sequence toggle bit clear */
 396 #define SQSET   0x0080  /* b7: Sequence toggle bit set */
 397 #define SQMON   0x0040  /* b6: Sequence toggle bit monitor */
 398 #define PBUSY   0x0020  /* b5: pipe busy */
 399 #define PID     0x0003  /* b1-0: Response PID */
 400
 401 /* PIPExTRE */
 402 #define TRENB           0x0200  /* b9: Transaction counter enable */
 403 #define TRCLR           0x0100  /* b8: Transaction counter clear */
 404
 405 /* PIPExTRN */
 406 #define TRNCNT          0xFFFF  /* b15-0: Transaction counter */
 407
 408 /* DEVADDx */
 409 #define UPPHUB          0x7800
 410 #define HUBPORT         0x0700
 411 #define USBSPD          0x00C0
 412 #define RTPORT          0x0001
 413
 414 #endif /* __LINUX_USB_R8A66597_H */
 415