The x86 timer interrupt handler is the only handler not traced in the
[linux-2.6/next.git] / arch / mips / include / asm / cachectl.h
blobf3ce721861d3859a2624669c1928cf4a91c1ca2f
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
7 */
8 #ifndef _ASM_CACHECTL
9 #define _ASM_CACHECTL
12 * Options for cacheflush system call
14 #define ICACHE (1<<0) /* flush instruction cache */
15 #define DCACHE (1<<1) /* writeback and flush data cache */
16 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
19 * Caching modes for the cachectl(2) call
21 * cachectl(2) is currently not supported and returns ENOSYS.
23 #define CACHEABLE 0 /* make pages cacheable */
24 #define UNCACHEABLE 1 /* make pages uncacheable */
26 #endif /* _ASM_CACHECTL */