The x86 timer interrupt handler is the only handler not traced in the
[linux-2.6/next.git] / arch / mips / include / asm / mach-powertv / war.h
blob7ac05ecc512be2fd0cb9dea3e7fc2c8800972733
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * This version for the PowerTV platform copied from the Malta version.
8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
11 #ifndef __ASM_MACH_POWERTV_WAR_H
12 #define __ASM_MACH_POWERTV_WAR_H
14 #define R4600_V1_INDEX_ICACHEOP_WAR 0
15 #define R4600_V1_HIT_CACHEOP_WAR 0
16 #define R4600_V2_HIT_CACHEOP_WAR 0
17 #define R5432_CP0_INTERRUPT_WAR 0
18 #define BCM1250_M3_WAR 0
19 #define SIBYTE_1956_WAR 0
20 #define MIPS4K_ICACHE_REFILL_WAR 1
21 #define MIPS_CACHE_SYNC_WAR 1
22 #define TX49XX_ICACHE_INDEX_INV_WAR 0
23 #define RM9000_CDEX_SMP_WAR 0
24 #define ICACHE_REFILLS_WORKAROUND_WAR 1
25 #define R10000_LLSC_WAR 0
26 #define MIPS34K_MISSED_ITLB_WAR 0
28 #endif /* __ASM_MACH_POWERTV_WAR_H */