2 * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
4 * This file define the irq handler for MSP PER subsystem interrupts.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <asm/mipsregs.h>
19 #include <asm/system.h>
21 #include <msp_cic_int.h>
26 * Convenience Macro. Should be somewhere generic.
28 #define get_current_vpe() \
29 ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
33 * The PER registers must be protected from concurrent access.
36 static DEFINE_SPINLOCK(per_lock
);
39 /* ensure writes to per are completed */
41 static inline void per_wmb(void)
43 const volatile void __iomem
*per_mem
= PER_INT_MSK_REG
;
44 volatile u32 dummy_read
;
47 dummy_read
= __raw_readl(per_mem
);
51 static inline void unmask_per_irq(struct irq_data
*d
)
55 spin_lock_irqsave(&per_lock
, flags
);
56 *PER_INT_MSK_REG
|= (1 << (d
->irq
- MSP_PER_INTBASE
));
57 spin_unlock_irqrestore(&per_lock
, flags
);
59 *PER_INT_MSK_REG
|= (1 << (d
->irq
- MSP_PER_INTBASE
));
64 static inline void mask_per_irq(struct irq_data
*d
)
68 spin_lock_irqsave(&per_lock
, flags
);
69 *PER_INT_MSK_REG
&= ~(1 << (d
->irq
- MSP_PER_INTBASE
));
70 spin_unlock_irqrestore(&per_lock
, flags
);
72 *PER_INT_MSK_REG
&= ~(1 << (d
->irq
- MSP_PER_INTBASE
));
77 static inline void msp_per_irq_ack(struct irq_data
*d
)
81 * In the PER interrupt controller, only bits 11 and 10
82 * are write-to-clear, (SPI TX complete, SPI RX complete).
83 * It does nothing for any others.
85 *PER_INT_STS_REG
= (1 << (d
->irq
- MSP_PER_INTBASE
));
89 static int msp_per_irq_set_affinity(struct irq_data
*d
,
90 const struct cpumask
*affinity
, bool force
)
92 /* WTF is this doing ????? */
98 static struct irq_chip msp_per_irq_controller
= {
100 .irq_enable
= unmask_per_irq
,
101 .irq_disable
= mask_per_irq
,
102 .irq_ack
= msp_per_irq_ack
,
104 .irq_set_affinity
= msp_per_irq_set_affinity
,
108 void __init
msp_per_irq_init(void)
111 /* Mask/clear interrupts. */
112 *PER_INT_MSK_REG
= 0x00000000;
113 *PER_INT_STS_REG
= 0xFFFFFFFF;
114 /* initialize all the IRQ descriptors */
115 for (i
= MSP_PER_INTBASE
; i
< MSP_PER_INTBASE
+ 32; i
++) {
116 irq_set_chip(i
, &msp_per_irq_controller
);
117 #ifdef CONFIG_MIPS_MT_SMTC
118 irq_hwmask
[i
] = C_IRQ4
;
123 void msp_per_irq_dispatch(void)
125 u32 per_mask
= *PER_INT_MSK_REG
;
126 u32 per_status
= *PER_INT_STS_REG
;
129 pending
= per_status
& per_mask
;
131 do_IRQ(ffs(pending
) + MSP_PER_INTBASE
- 1);
133 spurious_interrupt();