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The discovered bit in PGCCSR register indicates if the device has been
[linux-2.6/next.git] / arch / blackfin / mach-common / ints-priority.c
blob332dace6af3438ed8156178817df718e6feaab65
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #ifdef CONFIG_IPIPE
20 #include <linux/ipipe.h>
21 #endif
22 #include <asm/traps.h>
23 #include <asm/blackfin.h>
24 #include <asm/gpio.h>
25 #include <asm/irq_handler.h>
26 #include <asm/dpmc.h>
27
28 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
29
30 /*
31 * NOTES:
32 * - we have separated the physical Hardware interrupt from the
33 * levels that the LINUX kernel sees (see the description in irq.h)
34 * -
35 */
36
37 #ifndef CONFIG_SMP
38 /* Initialize this to an actual value to force it into the .data
39 * section so that we know it is properly initialized at entry into
40 * the kernel but before bss is initialized to zero (which is where
41 * it would live otherwise). The 0x1f magic represents the IRQs we
42 * cannot actually mask out in hardware.
43 */
44 unsigned long bfin_irq_flags = 0x1f;
45 EXPORT_SYMBOL(bfin_irq_flags);
46 #endif
47
48 #ifdef CONFIG_PM
49 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
50 unsigned vr_wakeup;
51 #endif
52
53 static struct ivgx {
54 /* irq number for request_irq, available in mach-bf5xx/irq.h */
55 unsigned int irqno;
56 /* corresponding bit in the SIC_ISR register */
57 unsigned int isrflag;
58 } ivg_table[NR_PERI_INTS];
59
60 static struct ivg_slice {
61 /* position of first irq in ivg_table for given ivg */
62 struct ivgx *ifirst;
63 struct ivgx *istop;
64 } ivg7_13[IVG13 - IVG7 + 1];
65
66
67 /*
68 * Search SIC_IAR and fill tables with the irqvalues
69 * and their positions in the SIC_ISR register.
70 */
71 static void __init search_IAR(void)
72 {
73 unsigned ivg, irq_pos = 0;
74 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
75 int irqN;
76
77 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
78
79 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
80 int irqn;
81 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
82 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
83 defined(CONFIG_BF538) || defined(CONFIG_BF539)
84 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
85 #else
86 (irqN >> 3)
87 #endif
88 );
89
90 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
91 int iar_shift = (irqn & 7) * 4;
92 if (ivg == (0xf & (iar >> iar_shift))) {
93 ivg_table[irq_pos].irqno = IVG7 + irqn;
94 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
95 ivg7_13[ivg].istop++;
96 irq_pos++;
97 }
98 }
99 }
100 }
101 }
102
103 /*
104 * This is for core internal IRQs
105 */
106
107 void bfin_ack_noop(struct irq_data *d)
108 {
109 /* Dummy function. */
110 }
111
112 static void bfin_core_mask_irq(struct irq_data *d)
113 {
114 bfin_irq_flags &= ~(1 << d->irq);
115 if (!hard_irqs_disabled())
116 hard_local_irq_enable();
117 }
118
119 static void bfin_core_unmask_irq(struct irq_data *d)
120 {
121 bfin_irq_flags |= 1 << d->irq;
122 /*
123 * If interrupts are enabled, IMASK must contain the same value
124 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
125 * are currently disabled we need not do anything; one of the
126 * callers will take care of setting IMASK to the proper value
127 * when reenabling interrupts.
128 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
129 * what we need.
130 */
131 if (!hard_irqs_disabled())
132 hard_local_irq_enable();
133 return;
134 }
135
136 void bfin_internal_mask_irq(unsigned int irq)
137 {
138 unsigned long flags = hard_local_irq_save();
139
140 #ifdef SIC_IMASK0
141 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
142 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
143 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
144 ~(1 << mask_bit));
145 # ifdef CONFIG_SMP
146 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
147 ~(1 << mask_bit));
148 # endif
149 #else
150 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
151 ~(1 << SIC_SYSIRQ(irq)));
152 #endif
153
154 hard_local_irq_restore(flags);
155 }
156
157 static void bfin_internal_mask_irq_chip(struct irq_data *d)
158 {
159 bfin_internal_mask_irq(d->irq);
160 }
161
162 #ifdef CONFIG_SMP
163 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
164 const struct cpumask *affinity)
165 #else
166 void bfin_internal_unmask_irq(unsigned int irq)
167 #endif
168 {
169 unsigned long flags = hard_local_irq_save();
170
171 #ifdef SIC_IMASK0
172 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
173 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
174 # ifdef CONFIG_SMP
175 if (cpumask_test_cpu(0, affinity))
176 # endif
177 bfin_write_SIC_IMASK(mask_bank,
178 bfin_read_SIC_IMASK(mask_bank) |
179 (1 << mask_bit));
180 # ifdef CONFIG_SMP
181 if (cpumask_test_cpu(1, affinity))
182 bfin_write_SICB_IMASK(mask_bank,
183 bfin_read_SICB_IMASK(mask_bank) |
184 (1 << mask_bit));
185 # endif
186 #else
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq)));
189 #endif
190
191 hard_local_irq_restore(flags);
192 }
193
194 #ifdef CONFIG_SMP
195 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
196 {
197 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
198 }
199
200 static int bfin_internal_set_affinity(struct irq_data *d,
201 const struct cpumask *mask, bool force)
202 {
203 bfin_internal_mask_irq(d->irq);
204 bfin_internal_unmask_irq_affinity(d->irq, mask);
205
206 return 0;
207 }
208 #else
209 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
210 {
211 bfin_internal_unmask_irq(d->irq);
212 }
213 #endif
214
215 #ifdef CONFIG_PM
216 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
217 {
218 u32 bank, bit, wakeup = 0;
219 unsigned long flags;
220 bank = SIC_SYSIRQ(irq) / 32;
221 bit = SIC_SYSIRQ(irq) % 32;
222
223 switch (irq) {
224 #ifdef IRQ_RTC
225 case IRQ_RTC:
226 wakeup |= WAKE;
227 break;
228 #endif
229 #ifdef IRQ_CAN0_RX
230 case IRQ_CAN0_RX:
231 wakeup |= CANWE;
232 break;
233 #endif
234 #ifdef IRQ_CAN1_RX
235 case IRQ_CAN1_RX:
236 wakeup |= CANWE;
237 break;
238 #endif
239 #ifdef IRQ_USB_INT0
240 case IRQ_USB_INT0:
241 wakeup |= USBWE;
242 break;
243 #endif
244 #ifdef CONFIG_BF54x
245 case IRQ_CNT:
246 wakeup |= ROTWE;
247 break;
248 #endif
249 default:
250 break;
251 }
252
253 flags = hard_local_irq_save();
254
255 if (state) {
256 bfin_sic_iwr[bank] |= (1 << bit);
257 vr_wakeup |= wakeup;
258
259 } else {
260 bfin_sic_iwr[bank] &= ~(1 << bit);
261 vr_wakeup &= ~wakeup;
262 }
263
264 hard_local_irq_restore(flags);
265
266 return 0;
267 }
268
269 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
270 {
271 return bfin_internal_set_wake(d->irq, state);
272 }
273 #else
274 # define bfin_internal_set_wake_chip NULL
275 #endif
276
277 static struct irq_chip bfin_core_irqchip = {
278 .name = "CORE",
279 .irq_ack = bfin_ack_noop,
280 .irq_mask = bfin_core_mask_irq,
281 .irq_unmask = bfin_core_unmask_irq,
282 };
283
284 static struct irq_chip bfin_internal_irqchip = {
285 .name = "INTN",
286 .irq_ack = bfin_ack_noop,
287 .irq_mask = bfin_internal_mask_irq_chip,
288 .irq_unmask = bfin_internal_unmask_irq_chip,
289 .irq_mask_ack = bfin_internal_mask_irq_chip,
290 .irq_disable = bfin_internal_mask_irq_chip,
291 .irq_enable = bfin_internal_unmask_irq_chip,
292 #ifdef CONFIG_SMP
293 .irq_set_affinity = bfin_internal_set_affinity,
294 #endif
295 .irq_set_wake = bfin_internal_set_wake_chip,
296 };
297
298 void bfin_handle_irq(unsigned irq)
299 {
300 #ifdef CONFIG_IPIPE
301 struct pt_regs regs; /* Contents not used. */
302 ipipe_trace_irq_entry(irq);
303 __ipipe_handle_irq(irq, &regs);
304 ipipe_trace_irq_exit(irq);
305 #else /* !CONFIG_IPIPE */
306 generic_handle_irq(irq);
307 #endif /* !CONFIG_IPIPE */
308 }
309
310 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
311 static int mac_stat_int_mask;
312
313 static void bfin_mac_status_ack_irq(unsigned int irq)
314 {
315 switch (irq) {
316 case IRQ_MAC_MMCINT:
317 bfin_write_EMAC_MMC_TIRQS(
318 bfin_read_EMAC_MMC_TIRQE() &
319 bfin_read_EMAC_MMC_TIRQS());
320 bfin_write_EMAC_MMC_RIRQS(
321 bfin_read_EMAC_MMC_RIRQE() &
322 bfin_read_EMAC_MMC_RIRQS());
323 break;
324 case IRQ_MAC_RXFSINT:
325 bfin_write_EMAC_RX_STKY(
326 bfin_read_EMAC_RX_IRQE() &
327 bfin_read_EMAC_RX_STKY());
328 break;
329 case IRQ_MAC_TXFSINT:
330 bfin_write_EMAC_TX_STKY(
331 bfin_read_EMAC_TX_IRQE() &
332 bfin_read_EMAC_TX_STKY());
333 break;
334 case IRQ_MAC_WAKEDET:
335 bfin_write_EMAC_WKUP_CTL(
336 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
337 break;
338 default:
339 /* These bits are W1C */
340 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
341 break;
342 }
343 }
344
345 static void bfin_mac_status_mask_irq(struct irq_data *d)
346 {
347 unsigned int irq = d->irq;
348
349 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
350 #ifdef BF537_FAMILY
351 switch (irq) {
352 case IRQ_MAC_PHYINT:
353 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
354 break;
355 default:
356 break;
357 }
358 #else
359 if (!mac_stat_int_mask)
360 bfin_internal_mask_irq(IRQ_MAC_ERROR);
361 #endif
362 bfin_mac_status_ack_irq(irq);
363 }
364
365 static void bfin_mac_status_unmask_irq(struct irq_data *d)
366 {
367 unsigned int irq = d->irq;
368
369 #ifdef BF537_FAMILY
370 switch (irq) {
371 case IRQ_MAC_PHYINT:
372 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
373 break;
374 default:
375 break;
376 }
377 #else
378 if (!mac_stat_int_mask)
379 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
380 #endif
381 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
382 }
383
384 #ifdef CONFIG_PM
385 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
386 {
387 #ifdef BF537_FAMILY
388 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
389 #else
390 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
391 #endif
392 }
393 #else
394 # define bfin_mac_status_set_wake NULL
395 #endif
396
397 static struct irq_chip bfin_mac_status_irqchip = {
398 .name = "MACST",
399 .irq_ack = bfin_ack_noop,
400 .irq_mask_ack = bfin_mac_status_mask_irq,
401 .irq_mask = bfin_mac_status_mask_irq,
402 .irq_unmask = bfin_mac_status_unmask_irq,
403 .irq_set_wake = bfin_mac_status_set_wake,
404 };
405
406 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
407 struct irq_desc *inta_desc)
408 {
409 int i, irq = 0;
410 u32 status = bfin_read_EMAC_SYSTAT();
411
412 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
413 if (status & (1L << i)) {
414 irq = IRQ_MAC_PHYINT + i;
415 break;
416 }
417
418 if (irq) {
419 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
420 bfin_handle_irq(irq);
421 } else {
422 bfin_mac_status_ack_irq(irq);
423 pr_debug("IRQ %d:"
424 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
425 irq);
426 }
427 } else
428 printk(KERN_ERR
429 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
430 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
431 "(EMAC_SYSTAT=0x%X)\n",
432 __func__, __FILE__, __LINE__, status);
433 }
434 #endif
435
436 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
437 {
438 #ifdef CONFIG_IPIPE
439 handle = handle_level_irq;
440 #endif
441 __irq_set_handler_locked(irq, handle);
442 }
443
444 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
445 extern void bfin_gpio_irq_prepare(unsigned gpio);
446
447 #if !BFIN_GPIO_PINT
448
449 static void bfin_gpio_ack_irq(struct irq_data *d)
450 {
451 /* AFAIK ack_irq in case mask_ack is provided
452 * get's only called for edge sense irqs
453 */
454 set_gpio_data(irq_to_gpio(d->irq), 0);
455 }
456
457 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
458 {
459 unsigned int irq = d->irq;
460 u32 gpionr = irq_to_gpio(irq);
461
462 if (!irqd_is_level_type(d))
463 set_gpio_data(gpionr, 0);
464
465 set_gpio_maska(gpionr, 0);
466 }
467
468 static void bfin_gpio_mask_irq(struct irq_data *d)
469 {
470 set_gpio_maska(irq_to_gpio(d->irq), 0);
471 }
472
473 static void bfin_gpio_unmask_irq(struct irq_data *d)
474 {
475 set_gpio_maska(irq_to_gpio(d->irq), 1);
476 }
477
478 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
479 {
480 u32 gpionr = irq_to_gpio(d->irq);
481
482 if (__test_and_set_bit(gpionr, gpio_enabled))
483 bfin_gpio_irq_prepare(gpionr);
484
485 bfin_gpio_unmask_irq(d);
486
487 return 0;
488 }
489
490 static void bfin_gpio_irq_shutdown(struct irq_data *d)
491 {
492 u32 gpionr = irq_to_gpio(d->irq);
493
494 bfin_gpio_mask_irq(d);
495 __clear_bit(gpionr, gpio_enabled);
496 bfin_gpio_irq_free(gpionr);
497 }
498
499 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
500 {
501 unsigned int irq = d->irq;
502 int ret;
503 char buf[16];
504 u32 gpionr = irq_to_gpio(irq);
505
506 if (type == IRQ_TYPE_PROBE) {
507 /* only probe unenabled GPIO interrupt lines */
508 if (test_bit(gpionr, gpio_enabled))
509 return 0;
510 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
511 }
512
513 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
514 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
515
516 snprintf(buf, 16, "gpio-irq%d", irq);
517 ret = bfin_gpio_irq_request(gpionr, buf);
518 if (ret)
519 return ret;
520
521 if (__test_and_set_bit(gpionr, gpio_enabled))
522 bfin_gpio_irq_prepare(gpionr);
523
524 } else {
525 __clear_bit(gpionr, gpio_enabled);
526 return 0;
527 }
528
529 set_gpio_inen(gpionr, 0);
530 set_gpio_dir(gpionr, 0);
531
532 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
533 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
534 set_gpio_both(gpionr, 1);
535 else
536 set_gpio_both(gpionr, 0);
537
538 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
539 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
540 else
541 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
542
543 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
544 set_gpio_edge(gpionr, 1);
545 set_gpio_inen(gpionr, 1);
546 set_gpio_data(gpionr, 0);
547
548 } else {
549 set_gpio_edge(gpionr, 0);
550 set_gpio_inen(gpionr, 1);
551 }
552
553 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
554 bfin_set_irq_handler(irq, handle_edge_irq);
555 else
556 bfin_set_irq_handler(irq, handle_level_irq);
557
558 return 0;
559 }
560
561 #ifdef CONFIG_PM
562 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
563 {
564 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
565 }
566 #else
567 # define bfin_gpio_set_wake NULL
568 #endif
569
570 static void bfin_demux_gpio_block(unsigned int irq)
571 {
572 unsigned int gpio, mask;
573
574 gpio = irq_to_gpio(irq);
575 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
576
577 while (mask) {
578 if (mask & 1)
579 bfin_handle_irq(irq);
580 irq++;
581 mask >>= 1;
582 }
583 }
584
585 void bfin_demux_gpio_irq(unsigned int inta_irq,
586 struct irq_desc *desc)
587 {
588 unsigned int irq;
589
590 switch (inta_irq) {
591 #if defined(BF537_FAMILY)
592 case IRQ_PF_INTA_PG_INTA:
593 bfin_demux_gpio_block(IRQ_PF0);
594 irq = IRQ_PG0;
595 break;
596 case IRQ_PH_INTA_MAC_RX:
597 irq = IRQ_PH0;
598 break;
599 #elif defined(BF533_FAMILY)
600 case IRQ_PROG_INTA:
601 irq = IRQ_PF0;
602 break;
603 #elif defined(BF538_FAMILY)
604 case IRQ_PORTF_INTA:
605 irq = IRQ_PF0;
606 break;
607 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
608 case IRQ_PORTF_INTA:
609 irq = IRQ_PF0;
610 break;
611 case IRQ_PORTG_INTA:
612 irq = IRQ_PG0;
613 break;
614 case IRQ_PORTH_INTA:
615 irq = IRQ_PH0;
616 break;
617 #elif defined(CONFIG_BF561)
618 case IRQ_PROG0_INTA:
619 irq = IRQ_PF0;
620 break;
621 case IRQ_PROG1_INTA:
622 irq = IRQ_PF16;
623 break;
624 case IRQ_PROG2_INTA:
625 irq = IRQ_PF32;
626 break;
627 #endif
628 default:
629 BUG();
630 return;
631 }
632
633 bfin_demux_gpio_block(irq);
634 }
635
636 #else
637
638 #define NR_PINT_SYS_IRQS 4
639 #define NR_PINT_BITS 32
640 #define NR_PINTS 160
641 #define IRQ_NOT_AVAIL 0xFF
642
643 #define PINT_2_BANK(x) ((x) >> 5)
644 #define PINT_2_BIT(x) ((x) & 0x1F)
645 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
646
647 static unsigned char irq2pint_lut[NR_PINTS];
648 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
649
650 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
651 (struct bfin_pint_regs *)PINT0_MASK_SET,
652 (struct bfin_pint_regs *)PINT1_MASK_SET,
653 (struct bfin_pint_regs *)PINT2_MASK_SET,
654 (struct bfin_pint_regs *)PINT3_MASK_SET,
655 };
656
657 inline unsigned int get_irq_base(u32 bank, u8 bmap)
658 {
659 unsigned int irq_base;
660
661 if (bank < 2) { /*PA-PB */
662 irq_base = IRQ_PA0 + bmap * 16;
663 } else { /*PC-PJ */
664 irq_base = IRQ_PC0 + bmap * 16;
665 }
666
667 return irq_base;
668 }
669
670 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
671 void init_pint_lut(void)
672 {
673 u16 bank, bit, irq_base, bit_pos;
674 u32 pint_assign;
675 u8 bmap;
676
677 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
678
679 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
680
681 pint_assign = pint[bank]->assign;
682
683 for (bit = 0; bit < NR_PINT_BITS; bit++) {
684
685 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
686
687 irq_base = get_irq_base(bank, bmap);
688
689 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
690 bit_pos = bit + bank * NR_PINT_BITS;
691
692 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
693 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
694 }
695 }
696 }
697
698 static void bfin_gpio_ack_irq(struct irq_data *d)
699 {
700 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
701 u32 pintbit = PINT_BIT(pint_val);
702 u32 bank = PINT_2_BANK(pint_val);
703
704 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
705 if (pint[bank]->invert_set & pintbit)
706 pint[bank]->invert_clear = pintbit;
707 else
708 pint[bank]->invert_set = pintbit;
709 }
710 pint[bank]->request = pintbit;
711
712 }
713
714 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
715 {
716 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
717 u32 pintbit = PINT_BIT(pint_val);
718 u32 bank = PINT_2_BANK(pint_val);
719
720 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
721 if (pint[bank]->invert_set & pintbit)
722 pint[bank]->invert_clear = pintbit;
723 else
724 pint[bank]->invert_set = pintbit;
725 }
726
727 pint[bank]->request = pintbit;
728 pint[bank]->mask_clear = pintbit;
729 }
730
731 static void bfin_gpio_mask_irq(struct irq_data *d)
732 {
733 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
734
735 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
736 }
737
738 static void bfin_gpio_unmask_irq(struct irq_data *d)
739 {
740 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
741 u32 pintbit = PINT_BIT(pint_val);
742 u32 bank = PINT_2_BANK(pint_val);
743
744 pint[bank]->mask_set = pintbit;
745 }
746
747 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
748 {
749 unsigned int irq = d->irq;
750 u32 gpionr = irq_to_gpio(irq);
751 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
752
753 if (pint_val == IRQ_NOT_AVAIL) {
754 printk(KERN_ERR
755 "GPIO IRQ %d :Not in PINT Assign table "
756 "Reconfigure Interrupt to Port Assignemt\n", irq);
757 return -ENODEV;
758 }
759
760 if (__test_and_set_bit(gpionr, gpio_enabled))
761 bfin_gpio_irq_prepare(gpionr);
762
763 bfin_gpio_unmask_irq(d);
764
765 return 0;
766 }
767
768 static void bfin_gpio_irq_shutdown(struct irq_data *d)
769 {
770 u32 gpionr = irq_to_gpio(d->irq);
771
772 bfin_gpio_mask_irq(d);
773 __clear_bit(gpionr, gpio_enabled);
774 bfin_gpio_irq_free(gpionr);
775 }
776
777 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
778 {
779 unsigned int irq = d->irq;
780 int ret;
781 char buf[16];
782 u32 gpionr = irq_to_gpio(irq);
783 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
784 u32 pintbit = PINT_BIT(pint_val);
785 u32 bank = PINT_2_BANK(pint_val);
786
787 if (pint_val == IRQ_NOT_AVAIL)
788 return -ENODEV;
789
790 if (type == IRQ_TYPE_PROBE) {
791 /* only probe unenabled GPIO interrupt lines */
792 if (test_bit(gpionr, gpio_enabled))
793 return 0;
794 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
795 }
796
797 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
798 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
799
800 snprintf(buf, 16, "gpio-irq%d", irq);
801 ret = bfin_gpio_irq_request(gpionr, buf);
802 if (ret)
803 return ret;
804
805 if (__test_and_set_bit(gpionr, gpio_enabled))
806 bfin_gpio_irq_prepare(gpionr);
807
808 } else {
809 __clear_bit(gpionr, gpio_enabled);
810 return 0;
811 }
812
813 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
814 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
815 else
816 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
817
818 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
819 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
820 if (gpio_get_value(gpionr))
821 pint[bank]->invert_set = pintbit;
822 else
823 pint[bank]->invert_clear = pintbit;
824 }
825
826 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
827 pint[bank]->edge_set = pintbit;
828 bfin_set_irq_handler(irq, handle_edge_irq);
829 } else {
830 pint[bank]->edge_clear = pintbit;
831 bfin_set_irq_handler(irq, handle_level_irq);
832 }
833
834 return 0;
835 }
836
837 #ifdef CONFIG_PM
838 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
839 {
840 u32 pint_irq;
841 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
842 u32 bank = PINT_2_BANK(pint_val);
843
844 switch (bank) {
845 case 0:
846 pint_irq = IRQ_PINT0;
847 break;
848 case 2:
849 pint_irq = IRQ_PINT2;
850 break;
851 case 3:
852 pint_irq = IRQ_PINT3;
853 break;
854 case 1:
855 pint_irq = IRQ_PINT1;
856 break;
857 default:
858 return -EINVAL;
859 }
860
861 bfin_internal_set_wake(pint_irq, state);
862
863 return 0;
864 }
865 #else
866 # define bfin_gpio_set_wake NULL
867 #endif
868
869 void bfin_demux_gpio_irq(unsigned int inta_irq,
870 struct irq_desc *desc)
871 {
872 u32 bank, pint_val;
873 u32 request, irq;
874
875 switch (inta_irq) {
876 case IRQ_PINT0:
877 bank = 0;
878 break;
879 case IRQ_PINT2:
880 bank = 2;
881 break;
882 case IRQ_PINT3:
883 bank = 3;
884 break;
885 case IRQ_PINT1:
886 bank = 1;
887 break;
888 default:
889 return;
890 }
891
892 pint_val = bank * NR_PINT_BITS;
893
894 request = pint[bank]->request;
895
896 while (request) {
897 if (request & 1) {
898 irq = pint2irq_lut[pint_val] + SYS_IRQS;
899 bfin_handle_irq(irq);
900 }
901 pint_val++;
902 request >>= 1;
903 }
904
905 }
906 #endif
907
908 static struct irq_chip bfin_gpio_irqchip = {
909 .name = "GPIO",
910 .irq_ack = bfin_gpio_ack_irq,
911 .irq_mask = bfin_gpio_mask_irq,
912 .irq_mask_ack = bfin_gpio_mask_ack_irq,
913 .irq_unmask = bfin_gpio_unmask_irq,
914 .irq_disable = bfin_gpio_mask_irq,
915 .irq_enable = bfin_gpio_unmask_irq,
916 .irq_set_type = bfin_gpio_irq_type,
917 .irq_startup = bfin_gpio_irq_startup,
918 .irq_shutdown = bfin_gpio_irq_shutdown,
919 .irq_set_wake = bfin_gpio_set_wake,
920 };
921
922 void __cpuinit init_exception_vectors(void)
923 {
924 /* cannot program in software:
925 * evt0 - emulation (jtag)
926 * evt1 - reset
927 */
928 bfin_write_EVT2(evt_nmi);
929 bfin_write_EVT3(trap);
930 bfin_write_EVT5(evt_ivhw);
931 bfin_write_EVT6(evt_timer);
932 bfin_write_EVT7(evt_evt7);
933 bfin_write_EVT8(evt_evt8);
934 bfin_write_EVT9(evt_evt9);
935 bfin_write_EVT10(evt_evt10);
936 bfin_write_EVT11(evt_evt11);
937 bfin_write_EVT12(evt_evt12);
938 bfin_write_EVT13(evt_evt13);
939 bfin_write_EVT14(evt_evt14);
940 bfin_write_EVT15(evt_system_call);
941 CSYNC();
942 }
943
944 /*
945 * This function should be called during kernel startup to initialize
946 * the BFin IRQ handling routines.
947 */
948
949 int __init init_arch_irq(void)
950 {
951 int irq;
952 unsigned long ilat = 0;
953
954 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
955 #ifdef SIC_IMASK0
956 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
957 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
958 # ifdef SIC_IMASK2
959 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
960 # endif
961 # ifdef CONFIG_SMP
962 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
963 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
964 # endif
965 #else
966 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
967 #endif
968
969 local_irq_disable();
970
971 #if BFIN_GPIO_PINT
972 # ifdef CONFIG_PINTx_REASSIGN
973 pint[0]->assign = CONFIG_PINT0_ASSIGN;
974 pint[1]->assign = CONFIG_PINT1_ASSIGN;
975 pint[2]->assign = CONFIG_PINT2_ASSIGN;
976 pint[3]->assign = CONFIG_PINT3_ASSIGN;
977 # endif
978 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
979 init_pint_lut();
980 #endif
981
982 for (irq = 0; irq <= SYS_IRQS; irq++) {
983 if (irq <= IRQ_CORETMR)
984 irq_set_chip(irq, &bfin_core_irqchip);
985 else
986 irq_set_chip(irq, &bfin_internal_irqchip);
987
988 switch (irq) {
989 #if BFIN_GPIO_PINT
990 case IRQ_PINT0:
991 case IRQ_PINT1:
992 case IRQ_PINT2:
993 case IRQ_PINT3:
994 #elif defined(BF537_FAMILY)
995 case IRQ_PH_INTA_MAC_RX:
996 case IRQ_PF_INTA_PG_INTA:
997 #elif defined(BF533_FAMILY)
998 case IRQ_PROG_INTA:
999 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1000 case IRQ_PORTF_INTA:
1001 case IRQ_PORTG_INTA:
1002 case IRQ_PORTH_INTA:
1003 #elif defined(CONFIG_BF561)
1004 case IRQ_PROG0_INTA:
1005 case IRQ_PROG1_INTA:
1006 case IRQ_PROG2_INTA:
1007 #elif defined(BF538_FAMILY)
1008 case IRQ_PORTF_INTA:
1009 #endif
1010 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1011 break;
1012 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1013 case IRQ_MAC_ERROR:
1014 irq_set_chained_handler(irq,
1015 bfin_demux_mac_status_irq);
1016 break;
1017 #endif
1018 #ifdef CONFIG_SMP
1019 case IRQ_SUPPLE_0:
1020 case IRQ_SUPPLE_1:
1021 irq_set_handler(irq, handle_percpu_irq);
1022 break;
1023 #endif
1024
1025 #ifdef CONFIG_TICKSOURCE_CORETMR
1026 case IRQ_CORETMR:
1027 # ifdef CONFIG_SMP
1028 irq_set_handler(irq, handle_percpu_irq);
1029 # else
1030 irq_set_handler(irq, handle_simple_irq);
1031 # endif
1032 break;
1033 #endif
1034
1035 #ifdef CONFIG_TICKSOURCE_GPTMR0
1036 case IRQ_TIMER0:
1037 irq_set_handler(irq, handle_simple_irq);
1038 break;
1039 #endif
1040
1041 default:
1042 #ifdef CONFIG_IPIPE
1043 irq_set_handler(irq, handle_level_irq);
1044 #else
1045 irq_set_handler(irq, handle_simple_irq);
1046 #endif
1047 break;
1048 }
1049 }
1050
1051 init_mach_irq();
1052
1053 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1054 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1055 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1056 handle_level_irq);
1057 #endif
1058 /* if configured as edge, then will be changed to do_edge_IRQ */
1059 for (irq = GPIO_IRQ_BASE;
1060 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1061 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1062 handle_level_irq);
1063
1064 bfin_write_IMASK(0);
1065 CSYNC();
1066 ilat = bfin_read_ILAT();
1067 CSYNC();
1068 bfin_write_ILAT(ilat);
1069 CSYNC();
1070
1071 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1072 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1073 * local_irq_enable()
1074 */
1075 program_IAR();
1076 /* Therefore it's better to setup IARs before interrupts enabled */
1077 search_IAR();
1078
1079 /* Enable interrupts IVG7-15 */
1080 bfin_irq_flags |= IMASK_IVG15 |
1081 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1082 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1083
1084 /* This implicitly covers ANOMALY_05000171
1085 * Boot-ROM code modifies SICA_IWRx wakeup registers
1086 */
1087 #ifdef SIC_IWR0
1088 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1089 # ifdef SIC_IWR1
1090 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1091 * will screw up the bootrom as it relies on MDMA0/1 waking it
1092 * up from IDLE instructions. See this report for more info:
1093 * http://blackfin.uclinux.org/gf/tracker/4323
1094 */
1095 if (ANOMALY_05000435)
1096 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1097 else
1098 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1099 # endif
1100 # ifdef SIC_IWR2
1101 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1102 # endif
1103 #else
1104 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1105 #endif
1106
1107 return 0;
1108 }
1109
1110 #ifdef CONFIG_DO_IRQ_L1
1111 __attribute__((l1_text))
1112 #endif
1113 static int vec_to_irq(int vec)
1114 {
1115 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1116 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1117 unsigned long sic_status[3];
1118
1119 if (likely(vec == EVT_IVTMR_P))
1120 return IRQ_CORETMR;
1121
1122 #ifdef SIC_ISR
1123 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1124 #else
1125 if (smp_processor_id()) {
1126 # ifdef SICB_ISR0
1127 /* This will be optimized out in UP mode. */
1128 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1129 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1130 # endif
1131 } else {
1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1133 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1134 }
1135 #endif
1136 #ifdef SIC_ISR2
1137 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1138 #endif
1139
1140 for (;; ivg++) {
1141 if (ivg >= ivg_stop)
1142 return -1;
1143 #ifdef SIC_ISR
1144 if (sic_status[0] & ivg->isrflag)
1145 #else
1146 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1147 #endif
1148 return ivg->irqno;
1149 }
1150 }
1151
1152 #ifdef CONFIG_DO_IRQ_L1
1153 __attribute__((l1_text))
1154 #endif
1155 void do_irq(int vec, struct pt_regs *fp)
1156 {
1157 int irq = vec_to_irq(vec);
1158 if (irq == -1)
1159 return;
1160 asm_do_IRQ(irq, fp);
1161 }
1162
1163 #ifdef CONFIG_IPIPE
1164
1165 int __ipipe_get_irq_priority(unsigned irq)
1166 {
1167 int ient, prio;
1168
1169 if (irq <= IRQ_CORETMR)
1170 return irq;
1171
1172 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1173 struct ivgx *ivg = ivg_table + ient;
1174 if (ivg->irqno == irq) {
1175 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1176 if (ivg7_13[prio].ifirst <= ivg &&
1177 ivg7_13[prio].istop > ivg)
1178 return IVG7 + prio;
1179 }
1180 }
1181 }
1182
1183 return IVG15;
1184 }
1185
1186 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1187 #ifdef CONFIG_DO_IRQ_L1
1188 __attribute__((l1_text))
1189 #endif
1190 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1191 {
1192 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1193 struct ipipe_domain *this_domain = __ipipe_current_domain;
1194 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1195 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1196 int irq, s = 0;
1197
1198 irq = vec_to_irq(vec);
1199 if (irq == -1)
1200 return 0;
1201
1202 if (irq == IRQ_SYSTMR) {
1203 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1204 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1205 #endif
1206 /* This is basically what we need from the register frame. */
1207 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1208 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1209 if (this_domain != ipipe_root_domain)
1210 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1211 else
1212 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1213 }
1214
1215 /*
1216 * We don't want Linux interrupt handlers to run at the
1217 * current core priority level (i.e. < EVT15), since this
1218 * might delay other interrupts handled by a high priority
1219 * domain. Here is what we do instead:
1220 *
1221 * - we raise the SYNCDEFER bit to prevent
1222 * __ipipe_handle_irq() to sync the pipeline for the root
1223 * stage for the incoming interrupt. Upon return, that IRQ is
1224 * pending in the interrupt log.
1225 *
1226 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1227 * that _schedule_and_signal_from_int will eventually sync the
1228 * pipeline from EVT15.
1229 */
1230 if (this_domain == ipipe_root_domain) {
1231 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1232 barrier();
1233 }
1234
1235 ipipe_trace_irq_entry(irq);
1236 __ipipe_handle_irq(irq, regs);
1237 ipipe_trace_irq_exit(irq);
1238
1239 if (user_mode(regs) &&
1240 !ipipe_test_foreign_stack() &&
1241 (current->ipipe_flags & PF_EVTRET) != 0) {
1242 /*
1243 * Testing for user_regs() does NOT fully eliminate
1244 * foreign stack contexts, because of the forged
1245 * interrupt returns we do through
1246 * __ipipe_call_irqtail. In that case, we might have
1247 * preempted a foreign stack context in a high
1248 * priority domain, with a single interrupt level now
1249 * pending after the irqtail unwinding is done. In
1250 * which case user_mode() is now true, and the event
1251 * gets dispatched spuriously.
1252 */
1253 current->ipipe_flags &= ~PF_EVTRET;
1254 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1255 }
1256
1257 if (this_domain == ipipe_root_domain) {
1258 set_thread_flag(TIF_IRQ_SYNC);
1259 if (!s) {
1260 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1261 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1262 }
1263 }
1264
1265 return 0;
1266 }
1267
1268 #endif /* CONFIG_IPIPE */
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