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The discovered bit in PGCCSR register indicates if the device has been
[linux-2.6/next.git] / drivers / gpio / gpio-nomadik.c
blob740caed2b278bc4defd03dccb5444885ec6804d2
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/slab.h>
26
27 #include <asm/mach/irq.h>
28
29 #include <plat/pincfg.h>
30 #include <plat/gpio-nomadik.h>
31 #include <mach/hardware.h>
32 #include <asm/gpio.h>
33
34 /*
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
36 * AMBA device, managing 32 pins and alternate functions. The logic block
37 * is currently used in the Nomadik and ux500.
38 *
39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
40 */
41
42 #define NMK_GPIO_PER_CHIP 32
43
44 struct nmk_gpio_chip {
45 struct gpio_chip chip;
46 void __iomem *addr;
47 struct clk *clk;
48 unsigned int bank;
49 unsigned int parent_irq;
50 int secondary_parent_irq;
51 u32 (*get_secondary_status)(unsigned int bank);
52 void (*set_ioforce)(bool enable);
53 spinlock_t lock;
54 bool sleepmode;
55 /* Keep track of configured edges */
56 u32 edge_rising;
57 u32 edge_falling;
58 u32 real_wake;
59 u32 rwimsc;
60 u32 fwimsc;
61 u32 slpm;
62 u32 enabled;
63 u32 pull_up;
64 };
65
66 static struct nmk_gpio_chip *
67 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
68
69 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
70
71 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
72
73 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
74 unsigned offset, int gpio_mode)
75 {
76 u32 bit = 1 << offset;
77 u32 afunc, bfunc;
78
79 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
80 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
81 if (gpio_mode & NMK_GPIO_ALT_A)
82 afunc |= bit;
83 if (gpio_mode & NMK_GPIO_ALT_B)
84 bfunc |= bit;
85 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
86 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
87 }
88
89 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
90 unsigned offset, enum nmk_gpio_slpm mode)
91 {
92 u32 bit = 1 << offset;
93 u32 slpm;
94
95 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
96 if (mode == NMK_GPIO_SLPM_NOCHANGE)
97 slpm |= bit;
98 else
99 slpm &= ~bit;
100 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
101 }
102
103 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
104 unsigned offset, enum nmk_gpio_pull pull)
105 {
106 u32 bit = 1 << offset;
107 u32 pdis;
108
109 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
110 if (pull == NMK_GPIO_PULL_NONE) {
111 pdis |= bit;
112 nmk_chip->pull_up &= ~bit;
113 } else {
114 pdis &= ~bit;
115 }
116
117 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
118
119 if (pull == NMK_GPIO_PULL_UP) {
120 nmk_chip->pull_up |= bit;
121 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
122 } else if (pull == NMK_GPIO_PULL_DOWN) {
123 nmk_chip->pull_up &= ~bit;
124 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
125 }
126 }
127
128 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
129 unsigned offset)
130 {
131 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
132 }
133
134 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
135 unsigned offset, int val)
136 {
137 if (val)
138 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
139 else
140 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
141 }
142
143 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
144 unsigned offset, int val)
145 {
146 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
147 __nmk_gpio_set_output(nmk_chip, offset, val);
148 }
149
150 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
151 unsigned offset, int gpio_mode,
152 bool glitch)
153 {
154 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
155 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
156
157 if (glitch && nmk_chip->set_ioforce) {
158 u32 bit = BIT(offset);
159
160 /* Prevent spurious wakeups */
161 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
162 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
163
164 nmk_chip->set_ioforce(true);
165 }
166
167 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
168
169 if (glitch && nmk_chip->set_ioforce) {
170 nmk_chip->set_ioforce(false);
171
172 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
173 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
174 }
175 }
176
177 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
178 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
179 {
180 static const char *afnames[] = {
181 [NMK_GPIO_ALT_GPIO] = "GPIO",
182 [NMK_GPIO_ALT_A] = "A",
183 [NMK_GPIO_ALT_B] = "B",
184 [NMK_GPIO_ALT_C] = "C"
185 };
186 static const char *pullnames[] = {
187 [NMK_GPIO_PULL_NONE] = "none",
188 [NMK_GPIO_PULL_UP] = "up",
189 [NMK_GPIO_PULL_DOWN] = "down",
190 [3] /* illegal */ = "??"
191 };
192 static const char *slpmnames[] = {
193 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
194 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
195 };
196
197 int pin = PIN_NUM(cfg);
198 int pull = PIN_PULL(cfg);
199 int af = PIN_ALT(cfg);
200 int slpm = PIN_SLPM(cfg);
201 int output = PIN_DIR(cfg);
202 int val = PIN_VAL(cfg);
203 bool glitch = af == NMK_GPIO_ALT_C;
204
205 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
206 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
207 output ? "output " : "input",
208 output ? (val ? "high" : "low") : "");
209
210 if (sleep) {
211 int slpm_pull = PIN_SLPM_PULL(cfg);
212 int slpm_output = PIN_SLPM_DIR(cfg);
213 int slpm_val = PIN_SLPM_VAL(cfg);
214
215 af = NMK_GPIO_ALT_GPIO;
216
217 /*
218 * The SLPM_* values are normal values + 1 to allow zero to
219 * mean "same as normal".
220 */
221 if (slpm_pull)
222 pull = slpm_pull - 1;
223 if (slpm_output)
224 output = slpm_output - 1;
225 if (slpm_val)
226 val = slpm_val - 1;
227
228 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
229 pin,
230 slpm_pull ? pullnames[pull] : "same",
231 slpm_output ? (output ? "output" : "input") : "same",
232 slpm_val ? (val ? "high" : "low") : "same");
233 }
234
235 if (output)
236 __nmk_gpio_make_output(nmk_chip, offset, val);
237 else {
238 __nmk_gpio_make_input(nmk_chip, offset);
239 __nmk_gpio_set_pull(nmk_chip, offset, pull);
240 }
241
242 /*
243 * If we've backed up the SLPM registers (glitch workaround), modify
244 * the backups since they will be restored.
245 */
246 if (slpmregs) {
247 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
248 slpmregs[nmk_chip->bank] |= BIT(offset);
249 else
250 slpmregs[nmk_chip->bank] &= ~BIT(offset);
251 } else
252 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
253
254 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
255 }
256
257 /*
258 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
259 * - Save SLPM registers
260 * - Set SLPM=0 for the IOs you want to switch and others to 1
261 * - Configure the GPIO registers for the IOs that are being switched
262 * - Set IOFORCE=1
263 * - Modify the AFLSA/B registers for the IOs that are being switched
264 * - Set IOFORCE=0
265 * - Restore SLPM registers
266 * - Any spurious wake up event during switch sequence to be ignored and
267 * cleared
268 */
269 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
270 {
271 int i;
272
273 for (i = 0; i < NUM_BANKS; i++) {
274 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
275 unsigned int temp = slpm[i];
276
277 if (!chip)
278 break;
279
280 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
281 writel(temp, chip->addr + NMK_GPIO_SLPC);
282 }
283 }
284
285 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
286 {
287 int i;
288
289 for (i = 0; i < NUM_BANKS; i++) {
290 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
291
292 if (!chip)
293 break;
294
295 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
296 }
297 }
298
299 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
300 {
301 static unsigned int slpm[NUM_BANKS];
302 unsigned long flags;
303 bool glitch = false;
304 int ret = 0;
305 int i;
306
307 for (i = 0; i < num; i++) {
308 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
309 glitch = true;
310 break;
311 }
312 }
313
314 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
315
316 if (glitch) {
317 memset(slpm, 0xff, sizeof(slpm));
318
319 for (i = 0; i < num; i++) {
320 int pin = PIN_NUM(cfgs[i]);
321 int offset = pin % NMK_GPIO_PER_CHIP;
322
323 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
324 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
325 }
326
327 nmk_gpio_glitch_slpm_init(slpm);
328 }
329
330 for (i = 0; i < num; i++) {
331 struct nmk_gpio_chip *nmk_chip;
332 int pin = PIN_NUM(cfgs[i]);
333
334 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
335 if (!nmk_chip) {
336 ret = -EINVAL;
337 break;
338 }
339
340 spin_lock(&nmk_chip->lock);
341 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
342 cfgs[i], sleep, glitch ? slpm : NULL);
343 spin_unlock(&nmk_chip->lock);
344 }
345
346 if (glitch)
347 nmk_gpio_glitch_slpm_restore(slpm);
348
349 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
350
351 return ret;
352 }
353
354 /**
355 * nmk_config_pin - configure a pin's mux attributes
356 * @cfg: pin confguration
357 *
358 * Configures a pin's mode (alternate function or GPIO), its pull up status,
359 * and its sleep mode based on the specified configuration. The @cfg is
360 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
361 * are constructed using, and can be further enhanced with, the macros in
362 * plat/pincfg.h.
363 *
364 * If a pin's mode is set to GPIO, it is configured as an input to avoid
365 * side-effects. The gpio can be manipulated later using standard GPIO API
366 * calls.
367 */
368 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
369 {
370 return __nmk_config_pins(&cfg, 1, sleep);
371 }
372 EXPORT_SYMBOL(nmk_config_pin);
373
374 /**
375 * nmk_config_pins - configure several pins at once
376 * @cfgs: array of pin configurations
377 * @num: number of elments in the array
378 *
379 * Configures several pins using nmk_config_pin(). Refer to that function for
380 * further information.
381 */
382 int nmk_config_pins(pin_cfg_t *cfgs, int num)
383 {
384 return __nmk_config_pins(cfgs, num, false);
385 }
386 EXPORT_SYMBOL(nmk_config_pins);
387
388 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
389 {
390 return __nmk_config_pins(cfgs, num, true);
391 }
392 EXPORT_SYMBOL(nmk_config_pins_sleep);
393
394 /**
395 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
396 * @gpio: pin number
397 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
398 *
399 * This register is actually in the pinmux layer, not the GPIO block itself.
400 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
401 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
402 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
403 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
404 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
405 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
406 *
407 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
408 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
409 * entered) regardless of the altfunction selected. Also wake-up detection is
410 * ENABLED.
411 *
412 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
413 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
414 * (for altfunction GPIO) or respective on-chip peripherals (for other
415 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
416 *
417 * Note that enable_irq_wake() will automatically enable wakeup detection.
418 */
419 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
420 {
421 struct nmk_gpio_chip *nmk_chip;
422 unsigned long flags;
423
424 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
425 if (!nmk_chip)
426 return -EINVAL;
427
428 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
429 spin_lock(&nmk_chip->lock);
430
431 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
432
433 spin_unlock(&nmk_chip->lock);
434 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
435
436 return 0;
437 }
438
439 /**
440 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
441 * @gpio: pin number
442 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
443 *
444 * Enables/disables pull up/down on a specified pin. This only takes effect if
445 * the pin is configured as an input (either explicitly or by the alternate
446 * function).
447 *
448 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
449 * configured as an input. Otherwise, due to the way the controller registers
450 * work, this function will change the value output on the pin.
451 */
452 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
453 {
454 struct nmk_gpio_chip *nmk_chip;
455 unsigned long flags;
456
457 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
458 if (!nmk_chip)
459 return -EINVAL;
460
461 spin_lock_irqsave(&nmk_chip->lock, flags);
462 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
463 spin_unlock_irqrestore(&nmk_chip->lock, flags);
464
465 return 0;
466 }
467
468 /* Mode functions */
469 /**
470 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
471 * @gpio: pin number
472 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
473 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
474 *
475 * Sets the mode of the specified pin to one of the alternate functions or
476 * plain GPIO.
477 */
478 int nmk_gpio_set_mode(int gpio, int gpio_mode)
479 {
480 struct nmk_gpio_chip *nmk_chip;
481 unsigned long flags;
482
483 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
484 if (!nmk_chip)
485 return -EINVAL;
486
487 spin_lock_irqsave(&nmk_chip->lock, flags);
488 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
489 spin_unlock_irqrestore(&nmk_chip->lock, flags);
490
491 return 0;
492 }
493 EXPORT_SYMBOL(nmk_gpio_set_mode);
494
495 int nmk_gpio_get_mode(int gpio)
496 {
497 struct nmk_gpio_chip *nmk_chip;
498 u32 afunc, bfunc, bit;
499
500 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
501 if (!nmk_chip)
502 return -EINVAL;
503
504 bit = 1 << (gpio - nmk_chip->chip.base);
505
506 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
507 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
508
509 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
510 }
511 EXPORT_SYMBOL(nmk_gpio_get_mode);
512
513
514 /* IRQ functions */
515 static inline int nmk_gpio_get_bitmask(int gpio)
516 {
517 return 1 << (gpio % 32);
518 }
519
520 static void nmk_gpio_irq_ack(struct irq_data *d)
521 {
522 int gpio;
523 struct nmk_gpio_chip *nmk_chip;
524
525 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
526 nmk_chip = irq_data_get_irq_chip_data(d);
527 if (!nmk_chip)
528 return;
529 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
530 }
531
532 enum nmk_gpio_irq_type {
533 NORMAL,
534 WAKE,
535 };
536
537 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
538 int gpio, enum nmk_gpio_irq_type which,
539 bool enable)
540 {
541 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
542 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
543 u32 bitmask = nmk_gpio_get_bitmask(gpio);
544 u32 reg;
545
546 /* we must individually set/clear the two edges */
547 if (nmk_chip->edge_rising & bitmask) {
548 reg = readl(nmk_chip->addr + rimsc);
549 if (enable)
550 reg |= bitmask;
551 else
552 reg &= ~bitmask;
553 writel(reg, nmk_chip->addr + rimsc);
554 }
555 if (nmk_chip->edge_falling & bitmask) {
556 reg = readl(nmk_chip->addr + fimsc);
557 if (enable)
558 reg |= bitmask;
559 else
560 reg &= ~bitmask;
561 writel(reg, nmk_chip->addr + fimsc);
562 }
563 }
564
565 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
566 int gpio, bool on)
567 {
568 if (nmk_chip->sleepmode) {
569 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
570 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
571 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
572 }
573
574 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
575 }
576
577 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
578 {
579 int gpio;
580 struct nmk_gpio_chip *nmk_chip;
581 unsigned long flags;
582 u32 bitmask;
583
584 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
585 nmk_chip = irq_data_get_irq_chip_data(d);
586 bitmask = nmk_gpio_get_bitmask(gpio);
587 if (!nmk_chip)
588 return -EINVAL;
589
590 if (enable)
591 nmk_chip->enabled |= bitmask;
592 else
593 nmk_chip->enabled &= ~bitmask;
594
595 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
596 spin_lock(&nmk_chip->lock);
597
598 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
599
600 if (!(nmk_chip->real_wake & bitmask))
601 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
602
603 spin_unlock(&nmk_chip->lock);
604 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
605
606 return 0;
607 }
608
609 static void nmk_gpio_irq_mask(struct irq_data *d)
610 {
611 nmk_gpio_irq_maskunmask(d, false);
612 }
613
614 static void nmk_gpio_irq_unmask(struct irq_data *d)
615 {
616 nmk_gpio_irq_maskunmask(d, true);
617 }
618
619 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
620 {
621 struct nmk_gpio_chip *nmk_chip;
622 unsigned long flags;
623 u32 bitmask;
624 int gpio;
625
626 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
627 nmk_chip = irq_data_get_irq_chip_data(d);
628 if (!nmk_chip)
629 return -EINVAL;
630 bitmask = nmk_gpio_get_bitmask(gpio);
631
632 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
633 spin_lock(&nmk_chip->lock);
634
635 if (!(nmk_chip->enabled & bitmask))
636 __nmk_gpio_set_wake(nmk_chip, gpio, on);
637
638 if (on)
639 nmk_chip->real_wake |= bitmask;
640 else
641 nmk_chip->real_wake &= ~bitmask;
642
643 spin_unlock(&nmk_chip->lock);
644 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
645
646 return 0;
647 }
648
649 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
650 {
651 bool enabled, wake = irqd_is_wakeup_set(d);
652 int gpio;
653 struct nmk_gpio_chip *nmk_chip;
654 unsigned long flags;
655 u32 bitmask;
656
657 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
658 nmk_chip = irq_data_get_irq_chip_data(d);
659 bitmask = nmk_gpio_get_bitmask(gpio);
660 if (!nmk_chip)
661 return -EINVAL;
662
663 if (type & IRQ_TYPE_LEVEL_HIGH)
664 return -EINVAL;
665 if (type & IRQ_TYPE_LEVEL_LOW)
666 return -EINVAL;
667
668 enabled = nmk_chip->enabled & bitmask;
669
670 spin_lock_irqsave(&nmk_chip->lock, flags);
671
672 if (enabled)
673 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
674
675 if (enabled || wake)
676 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
677
678 nmk_chip->edge_rising &= ~bitmask;
679 if (type & IRQ_TYPE_EDGE_RISING)
680 nmk_chip->edge_rising |= bitmask;
681
682 nmk_chip->edge_falling &= ~bitmask;
683 if (type & IRQ_TYPE_EDGE_FALLING)
684 nmk_chip->edge_falling |= bitmask;
685
686 if (enabled)
687 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
688
689 if (enabled || wake)
690 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
691
692 spin_unlock_irqrestore(&nmk_chip->lock, flags);
693
694 return 0;
695 }
696
697 static struct irq_chip nmk_gpio_irq_chip = {
698 .name = "Nomadik-GPIO",
699 .irq_ack = nmk_gpio_irq_ack,
700 .irq_mask = nmk_gpio_irq_mask,
701 .irq_unmask = nmk_gpio_irq_unmask,
702 .irq_set_type = nmk_gpio_irq_set_type,
703 .irq_set_wake = nmk_gpio_irq_set_wake,
704 };
705
706 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
707 u32 status)
708 {
709 struct nmk_gpio_chip *nmk_chip;
710 struct irq_chip *host_chip = irq_get_chip(irq);
711 unsigned int first_irq;
712
713 chained_irq_enter(host_chip, desc);
714
715 nmk_chip = irq_get_handler_data(irq);
716 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
717 while (status) {
718 int bit = __ffs(status);
719
720 generic_handle_irq(first_irq + bit);
721 status &= ~BIT(bit);
722 }
723
724 chained_irq_exit(host_chip, desc);
725 }
726
727 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
728 {
729 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
730 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
731
732 __nmk_gpio_irq_handler(irq, desc, status);
733 }
734
735 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
736 struct irq_desc *desc)
737 {
738 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
739 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
740
741 __nmk_gpio_irq_handler(irq, desc, status);
742 }
743
744 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
745 {
746 unsigned int first_irq;
747 int i;
748
749 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
750 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
751 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
752 handle_edge_irq);
753 set_irq_flags(i, IRQF_VALID);
754 irq_set_chip_data(i, nmk_chip);
755 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
756 }
757
758 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
759 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
760
761 if (nmk_chip->secondary_parent_irq >= 0) {
762 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
763 nmk_gpio_secondary_irq_handler);
764 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
765 }
766
767 return 0;
768 }
769
770 /* I/O Functions */
771 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
772 {
773 struct nmk_gpio_chip *nmk_chip =
774 container_of(chip, struct nmk_gpio_chip, chip);
775
776 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
777 return 0;
778 }
779
780 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
781 {
782 struct nmk_gpio_chip *nmk_chip =
783 container_of(chip, struct nmk_gpio_chip, chip);
784 u32 bit = 1 << offset;
785
786 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
787 }
788
789 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
790 int val)
791 {
792 struct nmk_gpio_chip *nmk_chip =
793 container_of(chip, struct nmk_gpio_chip, chip);
794
795 __nmk_gpio_set_output(nmk_chip, offset, val);
796 }
797
798 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
799 int val)
800 {
801 struct nmk_gpio_chip *nmk_chip =
802 container_of(chip, struct nmk_gpio_chip, chip);
803
804 __nmk_gpio_make_output(nmk_chip, offset, val);
805
806 return 0;
807 }
808
809 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
810 {
811 struct nmk_gpio_chip *nmk_chip =
812 container_of(chip, struct nmk_gpio_chip, chip);
813
814 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
815 }
816
817 #ifdef CONFIG_DEBUG_FS
818
819 #include <linux/seq_file.h>
820
821 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
822 {
823 int mode;
824 unsigned i;
825 unsigned gpio = chip->base;
826 int is_out;
827 struct nmk_gpio_chip *nmk_chip =
828 container_of(chip, struct nmk_gpio_chip, chip);
829 const char *modes[] = {
830 [NMK_GPIO_ALT_GPIO] = "gpio",
831 [NMK_GPIO_ALT_A] = "altA",
832 [NMK_GPIO_ALT_B] = "altB",
833 [NMK_GPIO_ALT_C] = "altC",
834 };
835
836 for (i = 0; i < chip->ngpio; i++, gpio++) {
837 const char *label = gpiochip_is_requested(chip, i);
838 bool pull;
839 u32 bit = 1 << i;
840
841 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
842 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
843 mode = nmk_gpio_get_mode(gpio);
844 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
845 gpio, label ?: "(none)",
846 is_out ? "out" : "in ",
847 chip->get
848 ? (chip->get(chip, i) ? "hi" : "lo")
849 : "? ",
850 (mode < 0) ? "unknown" : modes[mode],
851 pull ? "pull" : "none");
852
853 if (label && !is_out) {
854 int irq = gpio_to_irq(gpio);
855 struct irq_desc *desc = irq_to_desc(irq);
856
857 /* This races with request_irq(), set_irq_type(),
858 * and set_irq_wake() ... but those are "rare".
859 */
860 if (irq >= 0 && desc->action) {
861 char *trigger;
862 u32 bitmask = nmk_gpio_get_bitmask(gpio);
863
864 if (nmk_chip->edge_rising & bitmask)
865 trigger = "edge-rising";
866 else if (nmk_chip->edge_falling & bitmask)
867 trigger = "edge-falling";
868 else
869 trigger = "edge-undefined";
870
871 seq_printf(s, " irq-%d %s%s",
872 irq, trigger,
873 irqd_is_wakeup_set(&desc->irq_data)
874 ? " wakeup" : "");
875 }
876 }
877
878 seq_printf(s, "\n");
879 }
880 }
881
882 #else
883 #define nmk_gpio_dbg_show NULL
884 #endif
885
886 /* This structure is replicated for each GPIO block allocated at probe time */
887 static struct gpio_chip nmk_gpio_template = {
888 .direction_input = nmk_gpio_make_input,
889 .get = nmk_gpio_get_input,
890 .direction_output = nmk_gpio_make_output,
891 .set = nmk_gpio_set_output,
892 .to_irq = nmk_gpio_to_irq,
893 .dbg_show = nmk_gpio_dbg_show,
894 .can_sleep = 0,
895 };
896
897 /*
898 * Called from the suspend/resume path to only keep the real wakeup interrupts
899 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
900 * and not the rest of the interrupts which we needed to have as wakeups for
901 * cpuidle.
902 *
903 * PM ops are not used since this needs to be done at the end, after all the
904 * other drivers are done with their suspend callbacks.
905 */
906 void nmk_gpio_wakeups_suspend(void)
907 {
908 int i;
909
910 for (i = 0; i < NUM_BANKS; i++) {
911 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
912
913 if (!chip)
914 break;
915
916 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
917 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
918
919 writel(chip->rwimsc & chip->real_wake,
920 chip->addr + NMK_GPIO_RWIMSC);
921 writel(chip->fwimsc & chip->real_wake,
922 chip->addr + NMK_GPIO_FWIMSC);
923
924 if (chip->sleepmode) {
925 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
926
927 /* 0 -> wakeup enable */
928 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
929 }
930 }
931 }
932
933 void nmk_gpio_wakeups_resume(void)
934 {
935 int i;
936
937 for (i = 0; i < NUM_BANKS; i++) {
938 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
939
940 if (!chip)
941 break;
942
943 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
944 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
945
946 if (chip->sleepmode)
947 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
948 }
949 }
950
951 /*
952 * Read the pull up/pull down status.
953 * A bit set in 'pull_up' means that pull up
954 * is selected if pull is enabled in PDIS register.
955 * Note: only pull up/down set via this driver can
956 * be detected due to HW limitations.
957 */
958 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
959 {
960 if (gpio_bank < NUM_BANKS) {
961 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
962
963 if (!chip)
964 return;
965
966 *pull_up = chip->pull_up;
967 }
968 }
969
970 static int __devinit nmk_gpio_probe(struct platform_device *dev)
971 {
972 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
973 struct nmk_gpio_chip *nmk_chip;
974 struct gpio_chip *chip;
975 struct resource *res;
976 struct clk *clk;
977 int secondary_irq;
978 int irq;
979 int ret;
980
981 if (!pdata)
982 return -ENODEV;
983
984 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
985 if (!res) {
986 ret = -ENOENT;
987 goto out;
988 }
989
990 irq = platform_get_irq(dev, 0);
991 if (irq < 0) {
992 ret = irq;
993 goto out;
994 }
995
996 secondary_irq = platform_get_irq(dev, 1);
997 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
998 ret = -EINVAL;
999 goto out;
1000 }
1001
1002 if (request_mem_region(res->start, resource_size(res),
1003 dev_name(&dev->dev)) == NULL) {
1004 ret = -EBUSY;
1005 goto out;
1006 }
1007
1008 clk = clk_get(&dev->dev, NULL);
1009 if (IS_ERR(clk)) {
1010 ret = PTR_ERR(clk);
1011 goto out_release;
1012 }
1013
1014 clk_enable(clk);
1015
1016 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1017 if (!nmk_chip) {
1018 ret = -ENOMEM;
1019 goto out_clk;
1020 }
1021 /*
1022 * The virt address in nmk_chip->addr is in the nomadik register space,
1023 * so we can simply convert the resource address, without remapping
1024 */
1025 nmk_chip->bank = dev->id;
1026 nmk_chip->clk = clk;
1027 nmk_chip->addr = io_p2v(res->start);
1028 nmk_chip->chip = nmk_gpio_template;
1029 nmk_chip->parent_irq = irq;
1030 nmk_chip->secondary_parent_irq = secondary_irq;
1031 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1032 nmk_chip->set_ioforce = pdata->set_ioforce;
1033 nmk_chip->sleepmode = pdata->supports_sleepmode;
1034 spin_lock_init(&nmk_chip->lock);
1035
1036 chip = &nmk_chip->chip;
1037 chip->base = pdata->first_gpio;
1038 chip->ngpio = pdata->num_gpio;
1039 chip->label = pdata->name ?: dev_name(&dev->dev);
1040 chip->dev = &dev->dev;
1041 chip->owner = THIS_MODULE;
1042
1043 ret = gpiochip_add(&nmk_chip->chip);
1044 if (ret)
1045 goto out_free;
1046
1047 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1048
1049 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1050 platform_set_drvdata(dev, nmk_chip);
1051
1052 nmk_gpio_init_irq(nmk_chip);
1053
1054 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
1055 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
1056 return 0;
1057
1058 out_free:
1059 kfree(nmk_chip);
1060 out_clk:
1061 clk_disable(clk);
1062 clk_put(clk);
1063 out_release:
1064 release_mem_region(res->start, resource_size(res));
1065 out:
1066 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1067 pdata->first_gpio, pdata->first_gpio+31);
1068 return ret;
1069 }
1070
1071 static struct platform_driver nmk_gpio_driver = {
1072 .driver = {
1073 .owner = THIS_MODULE,
1074 .name = "gpio",
1075 },
1076 .probe = nmk_gpio_probe,
1077 };
1078
1079 static int __init nmk_gpio_init(void)
1080 {
1081 return platform_driver_register(&nmk_gpio_driver);
1082 }
1083
1084 core_initcall(nmk_gpio_init);
1085
1086 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1087 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1088 MODULE_LICENSE("GPL");
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