The discovered bit in PGCCSR register indicates if the device has been
[linux-2.6/next.git] / drivers / gpio / gpio-pch.c
blobc9c42971133c4193d1b21323de2ed20a8f46826f
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/gpio.h>
20 #include <linux/module.h>
22 #define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
23 #define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */
25 struct pch_regs {
26 u32 ien;
27 u32 istatus;
28 u32 idisp;
29 u32 iclr;
30 u32 imask;
31 u32 imaskclr;
32 u32 po;
33 u32 pi;
34 u32 pm;
35 u32 im0;
36 u32 im1;
37 u32 reserved[4];
38 u32 reset;
41 /**
42 * struct pch_gpio_reg_data - The register store data.
43 * @po_reg: To store contents of PO register.
44 * @pm_reg: To store contents of PM register.
46 struct pch_gpio_reg_data {
47 u32 po_reg;
48 u32 pm_reg;
51 /**
52 * struct pch_gpio - GPIO private data structure.
53 * @base: PCI base address of Memory mapped I/O register.
54 * @reg: Memory mapped PCH GPIO register list.
55 * @dev: Pointer to device structure.
56 * @gpio: Data for GPIO infrastructure.
57 * @pch_gpio_reg: Memory mapped Register data is saved here
58 * when suspend.
60 struct pch_gpio {
61 void __iomem *base;
62 struct pch_regs __iomem *reg;
63 struct device *dev;
64 struct gpio_chip gpio;
65 struct pch_gpio_reg_data pch_gpio_reg;
66 struct mutex lock;
69 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
71 u32 reg_val;
72 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
74 mutex_lock(&chip->lock);
75 reg_val = ioread32(&chip->reg->po);
76 if (val)
77 reg_val |= (1 << nr);
78 else
79 reg_val &= ~(1 << nr);
81 iowrite32(reg_val, &chip->reg->po);
82 mutex_unlock(&chip->lock);
85 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
87 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
89 return ioread32(&chip->reg->pi) & (1 << nr);
92 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
93 int val)
95 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
96 u32 pm;
97 u32 reg_val;
99 mutex_lock(&chip->lock);
100 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
101 pm |= (1 << nr);
102 iowrite32(pm, &chip->reg->pm);
104 reg_val = ioread32(&chip->reg->po);
105 if (val)
106 reg_val |= (1 << nr);
107 else
108 reg_val &= ~(1 << nr);
109 iowrite32(reg_val, &chip->reg->po);
111 mutex_unlock(&chip->lock);
113 return 0;
116 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
118 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
119 u32 pm;
121 mutex_lock(&chip->lock);
122 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
123 pm &= ~(1 << nr);
124 iowrite32(pm, &chip->reg->pm);
125 mutex_unlock(&chip->lock);
127 return 0;
131 * Save register configuration and disable interrupts.
133 static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
135 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
136 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
140 * This function restores the register configuration of the GPIO device.
142 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
144 /* to store contents of PO register */
145 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
146 /* to store contents of PM register */
147 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
150 static void pch_gpio_setup(struct pch_gpio *chip)
152 struct gpio_chip *gpio = &chip->gpio;
154 gpio->label = dev_name(chip->dev);
155 gpio->owner = THIS_MODULE;
156 gpio->direction_input = pch_gpio_direction_input;
157 gpio->get = pch_gpio_get;
158 gpio->direction_output = pch_gpio_direction_output;
159 gpio->set = pch_gpio_set;
160 gpio->dbg_show = NULL;
161 gpio->base = -1;
162 gpio->ngpio = GPIO_NUM_PINS;
163 gpio->can_sleep = 0;
166 static int __devinit pch_gpio_probe(struct pci_dev *pdev,
167 const struct pci_device_id *id)
169 s32 ret;
170 struct pch_gpio *chip;
172 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
173 if (chip == NULL)
174 return -ENOMEM;
176 chip->dev = &pdev->dev;
177 ret = pci_enable_device(pdev);
178 if (ret) {
179 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
180 goto err_pci_enable;
183 ret = pci_request_regions(pdev, KBUILD_MODNAME);
184 if (ret) {
185 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
186 goto err_request_regions;
189 chip->base = pci_iomap(pdev, 1, 0);
190 if (chip->base == 0) {
191 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
192 ret = -ENOMEM;
193 goto err_iomap;
196 chip->reg = chip->base;
197 pci_set_drvdata(pdev, chip);
198 mutex_init(&chip->lock);
199 pch_gpio_setup(chip);
200 ret = gpiochip_add(&chip->gpio);
201 if (ret) {
202 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
203 goto err_gpiochip_add;
206 return 0;
208 err_gpiochip_add:
209 pci_iounmap(pdev, chip->base);
211 err_iomap:
212 pci_release_regions(pdev);
214 err_request_regions:
215 pci_disable_device(pdev);
217 err_pci_enable:
218 kfree(chip);
219 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
220 return ret;
223 static void __devexit pch_gpio_remove(struct pci_dev *pdev)
225 int err;
226 struct pch_gpio *chip = pci_get_drvdata(pdev);
228 err = gpiochip_remove(&chip->gpio);
229 if (err)
230 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
232 pci_iounmap(pdev, chip->base);
233 pci_release_regions(pdev);
234 pci_disable_device(pdev);
235 kfree(chip);
238 #ifdef CONFIG_PM
239 static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
241 s32 ret;
242 struct pch_gpio *chip = pci_get_drvdata(pdev);
244 pch_gpio_save_reg_conf(chip);
245 pch_gpio_restore_reg_conf(chip);
247 ret = pci_save_state(pdev);
248 if (ret) {
249 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
250 return ret;
252 pci_disable_device(pdev);
253 pci_set_power_state(pdev, PCI_D0);
254 ret = pci_enable_wake(pdev, PCI_D0, 1);
255 if (ret)
256 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
258 return 0;
261 static int pch_gpio_resume(struct pci_dev *pdev)
263 s32 ret;
264 struct pch_gpio *chip = pci_get_drvdata(pdev);
266 ret = pci_enable_wake(pdev, PCI_D0, 0);
268 pci_set_power_state(pdev, PCI_D0);
269 ret = pci_enable_device(pdev);
270 if (ret) {
271 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
272 return ret;
274 pci_restore_state(pdev);
276 iowrite32(0x01, &chip->reg->reset);
277 iowrite32(0x00, &chip->reg->reset);
278 pch_gpio_restore_reg_conf(chip);
280 return 0;
282 #else
283 #define pch_gpio_suspend NULL
284 #define pch_gpio_resume NULL
285 #endif
287 #define PCI_VENDOR_ID_ROHM 0x10DB
288 static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
289 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
290 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
291 { 0, }
293 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
295 static struct pci_driver pch_gpio_driver = {
296 .name = "pch_gpio",
297 .id_table = pch_gpio_pcidev_id,
298 .probe = pch_gpio_probe,
299 .remove = __devexit_p(pch_gpio_remove),
300 .suspend = pch_gpio_suspend,
301 .resume = pch_gpio_resume
304 static int __init pch_gpio_pci_init(void)
306 return pci_register_driver(&pch_gpio_driver);
308 module_init(pch_gpio_pci_init);
310 static void __exit pch_gpio_pci_exit(void)
312 pci_unregister_driver(&pch_gpio_driver);
314 module_exit(pch_gpio_pci_exit);
316 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
317 MODULE_LICENSE("GPL");