The discovered bit in PGCCSR register indicates if the device has been
[linux-2.6/next.git] / include / linux / serial_sci.h
blob8bffe9ae2ca076cc1ec9b5cdf706f18d900e1c97
1 #ifndef __LINUX_SERIAL_SCI_H
2 #define __LINUX_SERIAL_SCI_H
4 #include <linux/serial_core.h>
5 #include <linux/sh_dma.h>
7 /*
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
9 */
11 #define SCIx_NOT_SUPPORTED (-1)
13 enum {
14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
21 #define SCSCR_TIE (1 << 7)
22 #define SCSCR_RIE (1 << 6)
23 #define SCSCR_TE (1 << 5)
24 #define SCSCR_RE (1 << 4)
25 #define SCSCR_REIE (1 << 3) /* not supported by all parts */
26 #define SCSCR_TOIE (1 << 2) /* not supported by all parts */
27 #define SCSCR_CKE1 (1 << 1)
28 #define SCSCR_CKE0 (1 << 0)
30 /* SCxSR SCI */
31 #define SCI_TDRE 0x80
32 #define SCI_RDRF 0x40
33 #define SCI_ORER 0x20
34 #define SCI_FER 0x10
35 #define SCI_PER 0x08
36 #define SCI_TEND 0x04
38 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
40 /* SCxSR SCIF */
41 #define SCIF_ER 0x0080
42 #define SCIF_TEND 0x0040
43 #define SCIF_TDFE 0x0020
44 #define SCIF_BRK 0x0010
45 #define SCIF_FER 0x0008
46 #define SCIF_PER 0x0004
47 #define SCIF_RDF 0x0002
48 #define SCIF_DR 0x0001
50 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
52 /* Offsets into the sci_port->irqs array */
53 enum {
54 SCIx_ERI_IRQ,
55 SCIx_RXI_IRQ,
56 SCIx_TXI_IRQ,
57 SCIx_BRI_IRQ,
58 SCIx_NR_IRQS,
60 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
63 enum {
64 SCIx_PROBE_REGTYPE,
66 SCIx_SCI_REGTYPE,
67 SCIx_IRDA_REGTYPE,
68 SCIx_SCIFA_REGTYPE,
69 SCIx_SCIFB_REGTYPE,
70 SCIx_SH3_SCIF_REGTYPE,
71 SCIx_SH4_SCIF_REGTYPE,
72 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
73 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
74 SCIx_SH7705_SCIF_REGTYPE,
76 SCIx_NR_REGTYPES,
79 #define SCIx_IRQ_MUXED(irq) \
80 { \
81 [SCIx_ERI_IRQ] = (irq), \
82 [SCIx_RXI_IRQ] = (irq), \
83 [SCIx_TXI_IRQ] = (irq), \
84 [SCIx_BRI_IRQ] = (irq), \
87 #define SCIx_IRQ_IS_MUXED(port) \
88 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \
89 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \
90 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \
91 !(port)->cfg->irqs[SCIx_RXI_IRQ])
93 * SCI register subset common for all port types.
94 * Not all registers will exist on all parts.
96 enum {
97 SCSMR, SCBRR, SCSCR, SCxSR,
98 SCFCR, SCFDR, SCxTDR, SCxRDR,
99 SCLSR, SCTFDR, SCRFDR, SCSPTR,
101 SCIx_NR_REGS,
104 struct device;
106 struct plat_sci_port_ops {
107 void (*init_pins)(struct uart_port *, unsigned int cflag);
111 * Platform device specific platform_data struct
113 struct plat_sci_port {
114 unsigned long mapbase; /* resource base */
115 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
116 unsigned int type; /* SCI / SCIF / IRDA */
117 upf_t flags; /* UPF_* flags */
119 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
120 unsigned int scscr; /* SCSCR initialization */
123 * Platform overrides if necessary, defaults otherwise.
125 int overrun_bit;
126 unsigned int error_mask;
128 int port_reg;
129 unsigned char regshift;
130 unsigned char regtype;
132 struct plat_sci_port_ops *ops;
134 struct device *dma_dev;
136 unsigned int dma_slave_tx;
137 unsigned int dma_slave_rx;
140 #endif /* __LINUX_SERIAL_SCI_H */