arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h

   1 /*
   2  * Jaguar-ATX Board Register Definitions
   3  *
   4  * (C) 2002 Momentum Computer Inc.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  12  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  14  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  15  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  16  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  17  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  18  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  19  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  20  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  *
  22  *  You should have received a copy of the  GNU General Public License along
  23  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  24  *  675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26 #ifndef __JAGUAR_ATX_FPGA_H__
  27 #define __JAGUAR_ATX_FPGA_H__
  28
  29 #define JAGUAR_ATX_REG_BOARDREV         0x0
  30 #define JAGUAR_ATX_REG_FPGA_REV         0x1
  31 #define JAGUAR_ATX_REG_FPGA_TYPE        0x2
  32 #define JAGUAR_ATX_REG_RESET_STATUS     0x3
  33 #define JAGUAR_ATX_REG_BOARD_STATUS     0x4
  34 #define JAGUAR_ATX_REG_RESERVED1        0x5
  35 #define JAGUAR_ATX_REG_SET              0x6
  36 #define JAGUAR_ATX_REG_CLR              0x7
  37 #define JAGUAR_ATX_REG_EEPROM_MODE      0x9
  38 #define JAGUAR_ATX_REG_RESERVED2        0xa
  39 #define JAGUAR_ATX_REG_RESERVED3        0xb
  40 #define JAGUAR_ATX_REG_RESERVED4        0xc
  41 #define JAGUAR_ATX_REG_PHY_INTSTAT      0xd
  42 #define JAGUAR_ATX_REG_RESERVED5        0xe
  43 #define JAGUAR_ATX_REG_RESERVED6        0xf
  44
  45 #define JAGUAR_ATX_CS0_ADDR             0xfc000000L
  46
  47 extern unsigned long ja_fpga_base;
  48
  49 #define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y)
  50 #define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x)
  51
  52 #endif