Linux-2.6.12-rc2
[linux-2.6/next.git] / arch / ppc / 8xx_io / enet.c
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1 /*
2 * Ethernet driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * I copied the basic skeleton from the lance driver, because I did not
6 * know how to write the Linux driver, but I did know how the LANCE worked.
8 * This version of the driver is somewhat selectable for the different
9 * processor/board combinations. It works for the boards I know about
10 * now, and should be easily modified to include others. Some of the
11 * configuration information is contained in <asm/commproc.h> and the
12 * remainder is here.
14 * Buffer descriptors are kept in the CPM dual port RAM, and the frame
15 * buffers are in the host memory.
17 * Right now, I am very watseful with the buffers. I allocate memory
18 * pages and then divide them into 2K frame buffers. This way I know I
19 * have buffers large enough to hold one frame within one buffer descriptor.
20 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
21 * will be much more memory efficient and will easily handle lots of
22 * small packets.
25 #include <linux/config.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/string.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/spinlock.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/bitops.h>
44 #include <asm/8xx_immap.h>
45 #include <asm/pgtable.h>
46 #include <asm/mpc8xx.h>
47 #include <asm/uaccess.h>
48 #include <asm/commproc.h>
51 * Theory of Operation
53 * The MPC8xx CPM performs the Ethernet processing on SCC1. It can use
54 * an aribtrary number of buffers on byte boundaries, but must have at
55 * least two receive buffers to prevent constant overrun conditions.
57 * The buffer descriptors are allocated from the CPM dual port memory
58 * with the data buffers allocated from host memory, just like all other
59 * serial communication protocols. The host memory buffers are allocated
60 * from the free page pool, and then divided into smaller receive and
61 * transmit buffers. The size of the buffers should be a power of two,
62 * since that nicely divides the page. This creates a ring buffer
63 * structure similar to the LANCE and other controllers.
65 * Like the LANCE driver:
66 * The driver runs as two independent, single-threaded flows of control. One
67 * is the send-packet routine, which enforces single-threaded use by the
68 * cep->tx_busy flag. The other thread is the interrupt handler, which is
69 * single threaded by the hardware and other software.
71 * The send packet thread has partial control over the Tx ring and the
72 * 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx
73 * packet. If the next queue slot is empty, it clears the tx_busy flag when
74 * finished otherwise it sets the 'lp->tx_full' flag.
76 * The MBX has a control register external to the MPC8xx that has some
77 * control of the Ethernet interface. Information is in the manual for
78 * your board.
80 * The RPX boards have an external control/status register. Consult the
81 * programming documents for details unique to your board.
83 * For the TQM8xx(L) modules, there is no control register interface.
84 * All functions are directly controlled using I/O pins. See <asm/commproc.h>.
87 /* The transmitter timeout
89 #define TX_TIMEOUT (2*HZ)
91 /* The number of Tx and Rx buffers. These are allocated from the page
92 * pool. The code may assume these are power of two, so it is best
93 * to keep them that size.
94 * We don't need to allocate pages for the transmitter. We just use
95 * the skbuffer directly.
97 #ifdef CONFIG_ENET_BIG_BUFFERS
98 #define CPM_ENET_RX_PAGES 32
99 #define CPM_ENET_RX_FRSIZE 2048
100 #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
101 #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
102 #define TX_RING_SIZE 64 /* Must be power of two */
103 #define TX_RING_MOD_MASK 63 /* for this to work */
104 #else
105 #define CPM_ENET_RX_PAGES 4
106 #define CPM_ENET_RX_FRSIZE 2048
107 #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
108 #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
109 #define TX_RING_SIZE 8 /* Must be power of two */
110 #define TX_RING_MOD_MASK 7 /* for this to work */
111 #endif
113 /* The CPM stores dest/src/type, data, and checksum for receive packets.
115 #define PKT_MAXBUF_SIZE 1518
116 #define PKT_MINBUF_SIZE 64
117 #define PKT_MAXBLR_SIZE 1520
119 /* The CPM buffer descriptors track the ring buffers. The rx_bd_base and
120 * tx_bd_base always point to the base of the buffer descriptors. The
121 * cur_rx and cur_tx point to the currently available buffer.
122 * The dirty_tx tracks the current buffer that is being sent by the
123 * controller. The cur_tx and dirty_tx are equal under both completely
124 * empty and completely full conditions. The empty/ready indicator in
125 * the buffer descriptor determines the actual condition.
127 struct scc_enet_private {
128 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
129 struct sk_buff* tx_skbuff[TX_RING_SIZE];
130 ushort skb_cur;
131 ushort skb_dirty;
133 /* CPM dual port RAM relative addresses.
135 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
136 cbd_t *tx_bd_base;
137 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
138 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
139 scc_t *sccp;
141 /* Virtual addresses for the receive buffers because we can't
142 * do a __va() on them anymore.
144 unsigned char *rx_vaddr[RX_RING_SIZE];
145 struct net_device_stats stats;
146 uint tx_full;
147 spinlock_t lock;
150 static int scc_enet_open(struct net_device *dev);
151 static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
152 static int scc_enet_rx(struct net_device *dev);
153 static void scc_enet_interrupt(void *dev_id, struct pt_regs *regs);
154 static int scc_enet_close(struct net_device *dev);
155 static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
156 static void set_multicast_list(struct net_device *dev);
158 /* Get this from various configuration locations (depends on board).
160 /*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/
162 /* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards
163 * use SCC2. Some even may use SCC3.
164 * This is easily extended if necessary.
166 #if defined(CONFIG_SCC3_ENET)
167 #define CPM_CR_ENET CPM_CR_CH_SCC3
168 #define PROFF_ENET PROFF_SCC3
169 #define SCC_ENET 2 /* Index, not number! */
170 #define CPMVEC_ENET CPMVEC_SCC3
171 #elif defined(CONFIG_SCC2_ENET)
172 #define CPM_CR_ENET CPM_CR_CH_SCC2
173 #define PROFF_ENET PROFF_SCC2
174 #define SCC_ENET 1 /* Index, not number! */
175 #define CPMVEC_ENET CPMVEC_SCC2
176 #elif defined(CONFIG_SCC1_ENET)
177 #define CPM_CR_ENET CPM_CR_CH_SCC1
178 #define PROFF_ENET PROFF_SCC1
179 #define SCC_ENET 0 /* Index, not number! */
180 #define CPMVEC_ENET CPMVEC_SCC1
181 #else
182 #error CONFIG_SCCx_ENET not defined
183 #endif
185 static int
186 scc_enet_open(struct net_device *dev)
189 /* I should reset the ring buffers here, but I don't yet know
190 * a simple way to do that.
193 netif_start_queue(dev);
194 return 0; /* Always succeed */
197 static int
198 scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
200 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
201 volatile cbd_t *bdp;
203 /* Fill in a Tx ring entry */
204 bdp = cep->cur_tx;
206 #ifndef final_version
207 if (bdp->cbd_sc & BD_ENET_TX_READY) {
208 /* Ooops. All transmit buffers are full. Bail out.
209 * This should not happen, since cep->tx_busy should be set.
211 printk("%s: tx queue full!.\n", dev->name);
212 return 1;
214 #endif
216 /* Clear all of the status flags.
218 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
220 /* If the frame is short, tell CPM to pad it.
222 if (skb->len <= ETH_ZLEN)
223 bdp->cbd_sc |= BD_ENET_TX_PAD;
224 else
225 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
227 /* Set buffer length and buffer pointer.
229 bdp->cbd_datlen = skb->len;
230 bdp->cbd_bufaddr = __pa(skb->data);
232 /* Save skb pointer.
234 cep->tx_skbuff[cep->skb_cur] = skb;
236 cep->stats.tx_bytes += skb->len;
237 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
239 /* Push the data cache so the CPM does not get stale memory
240 * data.
242 flush_dcache_range((unsigned long)(skb->data),
243 (unsigned long)(skb->data + skb->len));
245 spin_lock_irq(&cep->lock);
247 /* Send it on its way. Tell CPM its ready, interrupt when done,
248 * its the last BD of the frame, and to put the CRC on the end.
250 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
252 dev->trans_start = jiffies;
254 /* If this was the last BD in the ring, start at the beginning again.
256 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
257 bdp = cep->tx_bd_base;
258 else
259 bdp++;
261 if (bdp->cbd_sc & BD_ENET_TX_READY) {
262 netif_stop_queue(dev);
263 cep->tx_full = 1;
266 cep->cur_tx = (cbd_t *)bdp;
268 spin_unlock_irq(&cep->lock);
270 return 0;
273 static void
274 scc_enet_timeout(struct net_device *dev)
276 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
278 printk("%s: transmit timed out.\n", dev->name);
279 cep->stats.tx_errors++;
280 #ifndef final_version
282 int i;
283 cbd_t *bdp;
284 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
285 cep->cur_tx, cep->tx_full ? " (full)" : "",
286 cep->cur_rx);
287 bdp = cep->tx_bd_base;
288 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
289 printk("%04x %04x %08x\n",
290 bdp->cbd_sc,
291 bdp->cbd_datlen,
292 bdp->cbd_bufaddr);
293 bdp = cep->rx_bd_base;
294 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
295 printk("%04x %04x %08x\n",
296 bdp->cbd_sc,
297 bdp->cbd_datlen,
298 bdp->cbd_bufaddr);
300 #endif
301 if (!cep->tx_full)
302 netif_wake_queue(dev);
305 /* The interrupt handler.
306 * This is called from the CPM handler, not the MPC core interrupt.
308 static void
309 scc_enet_interrupt(void *dev_id, struct pt_regs *regs)
311 struct net_device *dev = dev_id;
312 volatile struct scc_enet_private *cep;
313 volatile cbd_t *bdp;
314 ushort int_events;
315 int must_restart;
317 cep = (struct scc_enet_private *)dev->priv;
319 /* Get the interrupt events that caused us to be here.
321 int_events = cep->sccp->scc_scce;
322 cep->sccp->scc_scce = int_events;
323 must_restart = 0;
325 /* Handle receive event in its own function.
327 if (int_events & SCCE_ENET_RXF)
328 scc_enet_rx(dev_id);
330 /* Check for a transmit error. The manual is a little unclear
331 * about this, so the debug code until I get it figured out. It
332 * appears that if TXE is set, then TXB is not set. However,
333 * if carrier sense is lost during frame transmission, the TXE
334 * bit is set, "and continues the buffer transmission normally."
335 * I don't know if "normally" implies TXB is set when the buffer
336 * descriptor is closed.....trial and error :-).
339 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
341 if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) {
342 spin_lock(&cep->lock);
343 bdp = cep->dirty_tx;
344 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
345 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
346 break;
348 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
349 cep->stats.tx_heartbeat_errors++;
350 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
351 cep->stats.tx_window_errors++;
352 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
353 cep->stats.tx_aborted_errors++;
354 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
355 cep->stats.tx_fifo_errors++;
356 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
357 cep->stats.tx_carrier_errors++;
360 /* No heartbeat or Lost carrier are not really bad errors.
361 * The others require a restart transmit command.
363 if (bdp->cbd_sc &
364 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
365 must_restart = 1;
366 cep->stats.tx_errors++;
369 cep->stats.tx_packets++;
371 /* Deferred means some collisions occurred during transmit,
372 * but we eventually sent the packet OK.
374 if (bdp->cbd_sc & BD_ENET_TX_DEF)
375 cep->stats.collisions++;
377 /* Free the sk buffer associated with this last transmit.
379 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
380 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
382 /* Update pointer to next buffer descriptor to be transmitted.
384 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
385 bdp = cep->tx_bd_base;
386 else
387 bdp++;
389 /* I don't know if we can be held off from processing these
390 * interrupts for more than one frame time. I really hope
391 * not. In such a case, we would now want to check the
392 * currently available BD (cur_tx) and determine if any
393 * buffers between the dirty_tx and cur_tx have also been
394 * sent. We would want to process anything in between that
395 * does not have BD_ENET_TX_READY set.
398 /* Since we have freed up a buffer, the ring is no longer
399 * full.
401 if (cep->tx_full) {
402 cep->tx_full = 0;
403 if (netif_queue_stopped(dev))
404 netif_wake_queue(dev);
407 cep->dirty_tx = (cbd_t *)bdp;
410 if (must_restart) {
411 volatile cpm8xx_t *cp;
413 /* Some transmit errors cause the transmitter to shut
414 * down. We now issue a restart transmit. Since the
415 * errors close the BD and update the pointers, the restart
416 * _should_ pick up without having to reset any of our
417 * pointers either.
419 cp = cpmp;
420 cp->cp_cpcr =
421 mk_cr_cmd(CPM_CR_ENET, CPM_CR_RESTART_TX) | CPM_CR_FLG;
422 while (cp->cp_cpcr & CPM_CR_FLG);
424 spin_unlock(&cep->lock);
427 /* Check for receive busy, i.e. packets coming but no place to
428 * put them. This "can't happen" because the receive interrupt
429 * is tossing previous frames.
431 if (int_events & SCCE_ENET_BSY) {
432 cep->stats.rx_dropped++;
433 printk("CPM ENET: BSY can't happen.\n");
436 return;
439 /* During a receive, the cur_rx points to the current incoming buffer.
440 * When we update through the ring, if the next incoming buffer has
441 * not been given to the system, we just set the empty indicator,
442 * effectively tossing the packet.
444 static int
445 scc_enet_rx(struct net_device *dev)
447 struct scc_enet_private *cep;
448 volatile cbd_t *bdp;
449 struct sk_buff *skb;
450 ushort pkt_len;
452 cep = (struct scc_enet_private *)dev->priv;
454 /* First, grab all of the stats for the incoming packet.
455 * These get messed up if we get called due to a busy condition.
457 bdp = cep->cur_rx;
459 for (;;) {
460 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
461 break;
463 #ifndef final_version
464 /* Since we have allocated space to hold a complete frame, both
465 * the first and last indicators should be set.
467 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
468 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
469 printk("CPM ENET: rcv is not first+last\n");
470 #endif
472 /* Frame too long or too short.
474 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
475 cep->stats.rx_length_errors++;
476 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
477 cep->stats.rx_frame_errors++;
478 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
479 cep->stats.rx_crc_errors++;
480 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
481 cep->stats.rx_crc_errors++;
483 /* Report late collisions as a frame error.
484 * On this error, the BD is closed, but we don't know what we
485 * have in the buffer. So, just drop this frame on the floor.
487 if (bdp->cbd_sc & BD_ENET_RX_CL) {
488 cep->stats.rx_frame_errors++;
490 else {
492 /* Process the incoming frame.
494 cep->stats.rx_packets++;
495 pkt_len = bdp->cbd_datlen;
496 cep->stats.rx_bytes += pkt_len;
498 /* This does 16 byte alignment, much more than we need.
499 * The packet length includes FCS, but we don't want to
500 * include that when passing upstream as it messes up
501 * bridging applications.
503 skb = dev_alloc_skb(pkt_len-4);
505 if (skb == NULL) {
506 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
507 cep->stats.rx_dropped++;
509 else {
510 skb->dev = dev;
511 skb_put(skb,pkt_len-4); /* Make room */
512 eth_copy_and_sum(skb,
513 cep->rx_vaddr[bdp - cep->rx_bd_base],
514 pkt_len-4, 0);
515 skb->protocol=eth_type_trans(skb,dev);
516 netif_rx(skb);
520 /* Clear the status flags for this buffer.
522 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
524 /* Mark the buffer empty.
526 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
528 /* Update BD pointer to next entry.
530 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
531 bdp = cep->rx_bd_base;
532 else
533 bdp++;
536 cep->cur_rx = (cbd_t *)bdp;
538 return 0;
541 static int
542 scc_enet_close(struct net_device *dev)
544 /* Don't know what to do yet.
546 netif_stop_queue(dev);
548 return 0;
551 static struct net_device_stats *scc_enet_get_stats(struct net_device *dev)
553 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
555 return &cep->stats;
558 /* Set or clear the multicast filter for this adaptor.
559 * Skeleton taken from sunlance driver.
560 * The CPM Ethernet implementation allows Multicast as well as individual
561 * MAC address filtering. Some of the drivers check to make sure it is
562 * a group multicast address, and discard those that are not. I guess I
563 * will do the same for now, but just remove the test if you want
564 * individual filtering as well (do the upper net layers want or support
565 * this kind of feature?).
568 static void set_multicast_list(struct net_device *dev)
570 struct scc_enet_private *cep;
571 struct dev_mc_list *dmi;
572 u_char *mcptr, *tdptr;
573 volatile scc_enet_t *ep;
574 int i, j;
575 cep = (struct scc_enet_private *)dev->priv;
577 /* Get pointer to SCC area in parameter RAM.
579 ep = (scc_enet_t *)dev->base_addr;
581 if (dev->flags&IFF_PROMISC) {
583 /* Log any net taps. */
584 printk("%s: Promiscuous mode enabled.\n", dev->name);
585 cep->sccp->scc_psmr |= SCC_PSMR_PRO;
586 } else {
588 cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
590 if (dev->flags & IFF_ALLMULTI) {
591 /* Catch all multicast addresses, so set the
592 * filter to all 1's.
594 ep->sen_gaddr1 = 0xffff;
595 ep->sen_gaddr2 = 0xffff;
596 ep->sen_gaddr3 = 0xffff;
597 ep->sen_gaddr4 = 0xffff;
599 else {
600 /* Clear filter and add the addresses in the list.
602 ep->sen_gaddr1 = 0;
603 ep->sen_gaddr2 = 0;
604 ep->sen_gaddr3 = 0;
605 ep->sen_gaddr4 = 0;
607 dmi = dev->mc_list;
609 for (i=0; i<dev->mc_count; i++) {
611 /* Only support group multicast for now.
613 if (!(dmi->dmi_addr[0] & 1))
614 continue;
616 /* The address in dmi_addr is LSB first,
617 * and taddr is MSB first. We have to
618 * copy bytes MSB first from dmi_addr.
620 mcptr = (u_char *)dmi->dmi_addr + 5;
621 tdptr = (u_char *)&ep->sen_taddrh;
622 for (j=0; j<6; j++)
623 *tdptr++ = *mcptr--;
625 /* Ask CPM to run CRC and set bit in
626 * filter mask.
628 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_SET_GADDR) | CPM_CR_FLG;
629 /* this delay is necessary here -- Cort */
630 udelay(10);
631 while (cpmp->cp_cpcr & CPM_CR_FLG);
637 /* Initialize the CPM Ethernet on SCC. If EPPC-Bug loaded us, or performed
638 * some other network I/O, a whole bunch of this has already been set up.
639 * It is no big deal if we do it again, we just have to disable the
640 * transmit and receive to make sure we don't catch the CPM with some
641 * inconsistent control information.
643 static int __init scc_enet_init(void)
645 struct net_device *dev;
646 struct scc_enet_private *cep;
647 int i, j, k, err;
648 uint dp_offset;
649 unsigned char *eap, *ba;
650 dma_addr_t mem_addr;
651 bd_t *bd;
652 volatile cbd_t *bdp;
653 volatile cpm8xx_t *cp;
654 volatile scc_t *sccp;
655 volatile scc_enet_t *ep;
656 volatile immap_t *immap;
658 cp = cpmp; /* Get pointer to Communication Processor */
660 immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000); /* and to internal registers */
662 bd = (bd_t *)__res;
664 dev = alloc_etherdev(sizeof(*cep));
665 if (!dev)
666 return -ENOMEM;
668 cep = dev->priv;
669 spin_lock_init(&cep->lock);
671 /* Get pointer to SCC area in parameter RAM.
673 ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]);
675 /* And another to the SCC register area.
677 sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]);
678 cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */
680 /* Disable receive and transmit in case EPPC-Bug started it.
682 sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
684 /* Cookbook style from the MPC860 manual.....
685 * Not all of this is necessary if EPPC-Bug has initialized
686 * the network.
687 * So far we are lucky, all board configurations use the same
688 * pins, or at least the same I/O Port for these functions.....
689 * It can't last though......
692 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
693 /* Configure port A pins for Txd and Rxd.
695 immap->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
696 immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
697 immap->im_ioport.iop_paodr &= ~PA_ENET_TXD;
698 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
699 /* Configure port B pins for Txd and Rxd.
701 immap->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
702 immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
703 immap->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
704 #else
705 #error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
706 #endif
708 #if defined(PC_ENET_LBK)
709 /* Configure port C pins to disable External Loopback
711 immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
712 immap->im_ioport.iop_pcdir |= PC_ENET_LBK;
713 immap->im_ioport.iop_pcso &= ~PC_ENET_LBK;
714 immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
715 #endif /* PC_ENET_LBK */
717 /* Configure port C pins to enable CLSN and RENA.
719 immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
720 immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
721 immap->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
723 /* Configure port A for TCLK and RCLK.
725 immap->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
726 immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
728 /* Configure Serial Interface clock routing.
729 * First, clear all SCC bits to zero, then set the ones we want.
731 cp->cp_sicr &= ~SICR_ENET_MASK;
732 cp->cp_sicr |= SICR_ENET_CLKRT;
734 /* Manual says set SDDR, but I can't find anything with that
735 * name. I think it is a misprint, and should be SDCR. This
736 * has already been set by the communication processor initialization.
739 /* Allocate space for the buffer descriptors in the DP ram.
740 * These are relative offsets in the DP ram address space.
741 * Initialize base addresses for the buffer descriptors.
743 dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
744 ep->sen_genscc.scc_rbase = dp_offset;
745 cep->rx_bd_base = cpm_dpram_addr(dp_offset);
747 dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
748 ep->sen_genscc.scc_tbase = dp_offset;
749 cep->tx_bd_base = cpm_dpram_addr(dp_offset);
751 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
752 cep->cur_rx = cep->rx_bd_base;
754 /* Issue init Rx BD command for SCC.
755 * Manual says to perform an Init Rx parameters here. We have
756 * to perform both Rx and Tx because the SCC may have been
757 * already running.
758 * In addition, we have to do it later because we don't yet have
759 * all of the BD control/status set properly.
760 cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG;
761 while (cp->cp_cpcr & CPM_CR_FLG);
764 /* Initialize function code registers for big-endian.
766 ep->sen_genscc.scc_rfcr = SCC_EB;
767 ep->sen_genscc.scc_tfcr = SCC_EB;
769 /* Set maximum bytes per receive buffer.
770 * This appears to be an Ethernet frame size, not the buffer
771 * fragment size. It must be a multiple of four.
773 ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE;
775 /* Set CRC preset and mask.
777 ep->sen_cpres = 0xffffffff;
778 ep->sen_cmask = 0xdebb20e3;
780 ep->sen_crcec = 0; /* CRC Error counter */
781 ep->sen_alec = 0; /* alignment error counter */
782 ep->sen_disfc = 0; /* discard frame counter */
784 ep->sen_pads = 0x8888; /* Tx short frame pad character */
785 ep->sen_retlim = 15; /* Retry limit threshold */
787 ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
788 ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
790 ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */
791 ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */
793 /* Clear hash tables.
795 ep->sen_gaddr1 = 0;
796 ep->sen_gaddr2 = 0;
797 ep->sen_gaddr3 = 0;
798 ep->sen_gaddr4 = 0;
799 ep->sen_iaddr1 = 0;
800 ep->sen_iaddr2 = 0;
801 ep->sen_iaddr3 = 0;
802 ep->sen_iaddr4 = 0;
804 /* Set Ethernet station address.
806 eap = (unsigned char *)&(ep->sen_paddrh);
807 for (i=5; i>=0; i--)
808 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
810 ep->sen_pper = 0; /* 'cause the book says so */
811 ep->sen_taddrl = 0; /* temp address (LSB) */
812 ep->sen_taddrm = 0;
813 ep->sen_taddrh = 0; /* temp address (MSB) */
815 /* Now allocate the host memory pages and initialize the
816 * buffer descriptors.
818 bdp = cep->tx_bd_base;
819 for (i=0; i<TX_RING_SIZE; i++) {
821 /* Initialize the BD for every fragment in the page.
823 bdp->cbd_sc = 0;
824 bdp->cbd_bufaddr = 0;
825 bdp++;
828 /* Set the last buffer to wrap.
830 bdp--;
831 bdp->cbd_sc |= BD_SC_WRAP;
833 bdp = cep->rx_bd_base;
834 k = 0;
835 for (i=0; i<CPM_ENET_RX_PAGES; i++) {
837 /* Allocate a page.
839 ba = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE,
840 &mem_addr, GFP_KERNEL);
841 /* BUG: no check for failure */
843 /* Initialize the BD for every fragment in the page.
845 for (j=0; j<CPM_ENET_RX_FRPPG; j++) {
846 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
847 bdp->cbd_bufaddr = mem_addr;
848 cep->rx_vaddr[k++] = ba;
849 mem_addr += CPM_ENET_RX_FRSIZE;
850 ba += CPM_ENET_RX_FRSIZE;
851 bdp++;
855 /* Set the last buffer to wrap.
857 bdp--;
858 bdp->cbd_sc |= BD_SC_WRAP;
860 /* Let's re-initialize the channel now. We have to do it later
861 * than the manual describes because we have just now finished
862 * the BD initialization.
864 cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG;
865 while (cp->cp_cpcr & CPM_CR_FLG);
867 cep->skb_cur = cep->skb_dirty = 0;
869 sccp->scc_scce = 0xffff; /* Clear any pending events */
871 /* Enable interrupts for transmit error, complete frame
872 * received, and any transmit buffer we have also set the
873 * interrupt flag.
875 sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
877 /* Install our interrupt handler.
879 cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev);
881 /* Set GSMR_H to enable all normal operating modes.
882 * Set GSMR_L to enable Ethernet to MC68160.
884 sccp->scc_gsmrh = 0;
885 sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);
887 /* Set sync/delimiters.
889 sccp->scc_dsr = 0xd555;
891 /* Set processing mode. Use Ethernet CRC, catch broadcast, and
892 * start frame search 22 bit times after RENA.
894 sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
896 /* It is now OK to enable the Ethernet transmitter.
897 * Unfortunately, there are board implementation differences here.
899 #if (!defined (PB_ENET_TENA) && defined (PC_ENET_TENA))
900 immap->im_ioport.iop_pcpar |= PC_ENET_TENA;
901 immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
902 #elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA))
903 cp->cp_pbpar |= PB_ENET_TENA;
904 cp->cp_pbdir |= PB_ENET_TENA;
905 #else
906 #error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA
907 #endif
909 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
910 /* And while we are here, set the configuration to enable ethernet.
912 *((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK;
913 *((volatile uint *)RPX_CSR_ADDR) |=
914 (BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS);
915 #endif
917 #ifdef CONFIG_BSEIP
918 /* BSE uses port B and C for PHY control.
920 cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS);
921 cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
922 cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
924 immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK;
925 immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK;
926 immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK;
927 immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK;
928 #endif
930 #ifdef CONFIG_FADS
931 cp->cp_pbpar |= PB_ENET_TENA;
932 cp->cp_pbdir |= PB_ENET_TENA;
934 /* Enable the EEST PHY.
936 *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
937 #endif
939 dev->base_addr = (unsigned long)ep;
940 #if 0
941 dev->name = "CPM_ENET";
942 #endif
944 /* The CPM Ethernet specific entries in the device structure. */
945 dev->open = scc_enet_open;
946 dev->hard_start_xmit = scc_enet_start_xmit;
947 dev->tx_timeout = scc_enet_timeout;
948 dev->watchdog_timeo = TX_TIMEOUT;
949 dev->stop = scc_enet_close;
950 dev->get_stats = scc_enet_get_stats;
951 dev->set_multicast_list = set_multicast_list;
953 err = register_netdev(dev);
954 if (err) {
955 free_netdev(dev);
956 return err;
959 /* And last, enable the transmit and receive processing.
961 sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
963 printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1);
964 for (i=0; i<5; i++)
965 printk("%02x:", dev->dev_addr[i]);
966 printk("%02x\n", dev->dev_addr[5]);
968 return 0;
971 module_init(scc_enet_init);