drivers/scsi/pas16.h

   1 /*
   2  * This driver adapted from Drew Eckhardt's Trantor T128 driver
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  *  ( Based on T128 - DISTRIBUTION RELEASE 3. )
  11  *
  12  * Modified to work with the Pro Audio Spectrum/Studio 16
  13  * by John Weidman.
  14  *
  15  *
  16  * For more information, please consult
  17  *
  18  * Media Vision
  19  * (510) 770-8600
  20  * (800) 348-7116
  21  *
  22  * and
  23  *
  24  * NCR 5380 Family
  25  * SCSI Protocol Controller
  26  * Databook
  27  *
  28  * NCR Microelectronics
  29  * 1635 Aeroplaza Drive
  30  * Colorado Springs, CO 80916
  31  * 1+ (719) 578-3400
  32  * 1+ (800) 334-5454
  33  */
  34
  35
  36 #ifndef PAS16_H
  37 #define PAS16_H
  38
  39 #define PAS16_PUBLIC_RELEASE 3
  40
  41 #define PDEBUG_INIT     0x1
  42 #define PDEBUG_TRANSFER 0x2
  43
  44 #define PAS16_DEFAULT_BASE_1  0x388
  45 #define PAS16_DEFAULT_BASE_2  0x384
  46 #define PAS16_DEFAULT_BASE_3  0x38c
  47 #define PAS16_DEFAULT_BASE_4  0x288
  48
  49 #define PAS16_DEFAULT_BOARD_1_IRQ 10
  50 #define PAS16_DEFAULT_BOARD_2_IRQ 12
  51 #define PAS16_DEFAULT_BOARD_3_IRQ 14
  52 #define PAS16_DEFAULT_BOARD_4_IRQ 15
  53
  54
  55 /*
  56  * The Pro Audio Spectrum boards are I/O mapped. They use a Zilog 5380
  57  * SCSI controller, which is the equivalent of NCR's 5380.  "Pseudo-DMA"
  58  * architecture is used, where a PAL drives the DMA signals on the 5380
  59  * allowing fast, blind transfers with proper handshaking.
  60  */
  61
  62
  63 /* The Time-out Counter register is used to safe-guard against a stuck
  64  * bus (in the case of RDY driven handshake) or a stuck byte (if 16-Bit
  65  * DMA conversion is used).  The counter uses a 28.224MHz clock
  66  * divided by 14 as its clock source.  In the case of a stuck byte in
  67  * the holding register, an interrupt is generated (and mixed with the
  68  * one with the drive) using the CD-ROM interrupt pointer.
  69  */
  70
  71 #define P_TIMEOUT_COUNTER_REG   0x4000
  72 #define P_TC_DISABLE    0x80    /* Set to 0 to enable timeout int. */
  73                                 /* Bits D6-D0 contain timeout count */
  74
  75
  76 #define P_TIMEOUT_STATUS_REG_OFFSET     0x4001
  77 #define P_TS_TIM                0x80    /* check timeout status */
  78                                         /* Bits D6-D4 N/U */
  79 #define P_TS_ARM_DRQ_INT        0x08    /* Arm DRQ Int.  When set high,
  80                                          * the next rising edge will
  81                                          * cause a CD-ROM interrupt.
  82                                          * When set low, the interrupt
  83                                          * will be cleared.  There is
  84                                          * no status available for
  85                                          * this interrupt.
  86                                          */
  87 #define P_TS_ENABLE_TO_ERR_INTERRUPT    /* Enable timeout error int. */
  88 #define P_TS_ENABLE_WAIT                /* Enable Wait */
  89
  90 #define P_TS_CT                 0x01    /* clear timeout. Note: writing
  91                                          * to this register clears the
  92                                          * timeout error int. or status
  93                                          */
  94
  95
  96 /*
  97  * The data register reads/writes to/from the 5380 in pseudo-DMA mode
  98  */
  99
 100 #define P_DATA_REG_OFFSET       0x5c00  /* rw */
 101
 102 #define P_STATUS_REG_OFFSET     0x5c01  /* ro */
 103 #define P_ST_RDY                0x80    /* 5380 DDRQ Status */
 104
 105 #define P_IRQ_STATUS            0x5c03
 106 #define P_IS_IRQ                0x80    /* DIRQ status */
 107
 108 #define PCB_CONFIG 0x803
 109 #define MASTER_ADDRESS_PTR 0x9a01  /* Fixed position - no relo */
 110 #define SYS_CONFIG_4 0x8003
 111 #define WAIT_STATE 0xbc00
 112 #define OPERATION_MODE_1 0xec03
 113 #define IO_CONFIG_3 0xf002
 114
 115
 116 #ifndef ASM
 117 static int pas16_abort(Scsi_Cmnd *);
 118 static int pas16_biosparam(struct scsi_device *, struct block_device *,
 119                            sector_t, int*);
 120 static int pas16_detect(Scsi_Host_Template *);
 121 static int pas16_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
 122 static int pas16_bus_reset(Scsi_Cmnd *);
 123 static int pas16_host_reset(Scsi_Cmnd *);
 124 static int pas16_device_reset(Scsi_Cmnd *);
 125
 126 #ifndef CMD_PER_LUN
 127 #define CMD_PER_LUN 2
 128 #endif
 129
 130 #ifndef CAN_QUEUE
 131 #define CAN_QUEUE 32
 132 #endif
 133
 134 #ifndef HOSTS_C
 135
 136 #define NCR5380_implementation_fields \
 137     volatile unsigned short io_port
 138
 139 #define NCR5380_local_declare() \
 140     volatile unsigned short io_port
 141
 142 #define NCR5380_setup(instance) \
 143     io_port = (instance)->io_port
 144
 145 #define PAS16_io_port(reg) ( io_port + pas16_offset[(reg)] )
 146
 147 #if !(PDEBUG & PDEBUG_TRANSFER)
 148 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
 149 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
 150 #else
 151 #define NCR5380_read(reg)                                               \
 152     (((unsigned char) printk("scsi%d : read register %d at io_port %04x\n"\
 153     , instance->hostno, (reg), PAS16_io_port(reg))), inb( PAS16_io_port(reg)) )
 154
 155 #define NCR5380_write(reg, value)                                       \
 156     (printk("scsi%d : write %02x to register %d at io_port %04x\n",     \
 157             instance->hostno, (value), (reg), PAS16_io_port(reg)),      \
 158     outb( (value),PAS16_io_port(reg) ) )
 159
 160 #endif
 161
 162
 163 #define NCR5380_intr pas16_intr
 164 #define do_NCR5380_intr do_pas16_intr
 165 #define NCR5380_queue_command pas16_queue_command
 166 #define NCR5380_abort pas16_abort
 167 #define NCR5380_device_reset pas16_device_reset
 168 #define NCR5380_bus_reset pas16_bus_reset
 169 #define NCR5380_host_reset pas16_host_reset
 170 #define NCR5380_proc_info pas16_proc_info
 171
 172 /* 15 14 12 10 7 5 3
 173    1101 0100 1010 1000 */
 174
 175 #define PAS16_IRQS 0xd4a8
 176
 177 #endif /* else def HOSTS_C */
 178 #endif /* ndef ASM */
 179 #endif /* PAS16_H */