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Linux-2.6.12-rc2
[linux-2.6/next.git] / drivers / video / aty / radeon_pm.c
blob23c677e5093fddc5408cf10a6564673533628023
1 /*
2 * drivers/video/aty/radeon_pm.c
3 *
4 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright 2004 Paul Mackerras <paulus@samba.org>
6 *
7 * This is the power management code for ATI radeon chipsets. It contains
8 * some dynamic clock PM enable/disable code similar to what X.org does,
9 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10 * and the necessary bits to re-initialize from scratch a few chips found
11 * on PowerMacs as well. The later could be extended to more platforms
12 * provided the memory controller configuration code be made more generic,
13 * and you can get the proper mode register commands for your RAMs.
14 * Those things may be found in the BIOS image...
15 */
16
17 #include "radeonfb.h"
18
19 #include <linux/console.h>
20 #include <linux/agp_backend.h>
21
22 #ifdef CONFIG_PPC_PMAC
23 #include <asm/processor.h>
24 #include <asm/prom.h>
25 #include <asm/pmac_feature.h>
26 #endif
27
28 #include "ati_ids.h"
29
30 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
31 {
32 u32 tmp;
33
34 /* RV100 */
35 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
36 if (rinfo->has_CRTC2) {
37 tmp = INPLL(pllSCLK_CNTL);
38 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
39 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
40 OUTPLL(pllSCLK_CNTL, tmp);
41 }
42 tmp = INPLL(pllMCLK_CNTL);
43 tmp |= (MCLK_CNTL__FORCE_MCLKA |
44 MCLK_CNTL__FORCE_MCLKB |
45 MCLK_CNTL__FORCE_YCLKA |
46 MCLK_CNTL__FORCE_YCLKB |
47 MCLK_CNTL__FORCE_AIC |
48 MCLK_CNTL__FORCE_MC);
49 OUTPLL(pllMCLK_CNTL, tmp);
50 return;
51 }
52 /* R100 */
53 if (!rinfo->has_CRTC2) {
54 tmp = INPLL(pllSCLK_CNTL);
55 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
56 SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
57 SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
58 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
59 SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
60 SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
61 SCLK_CNTL__FORCE_RB);
62 OUTPLL(pllSCLK_CNTL, tmp);
63 return;
64 }
65 /* RV350 (M10) */
66 if (rinfo->family == CHIP_FAMILY_RV350) {
67 /* for RV350/M10, no delays are required. */
68 tmp = INPLL(pllSCLK_CNTL2);
69 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
70 SCLK_CNTL2__R300_FORCE_GA |
71 SCLK_CNTL2__R300_FORCE_CBA);
72 OUTPLL(pllSCLK_CNTL2, tmp);
73
74 tmp = INPLL(pllSCLK_CNTL);
75 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
76 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
77 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
78 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
79 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
80 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
81 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
82 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
83 OUTPLL(pllSCLK_CNTL, tmp);
84
85 tmp = INPLL(pllSCLK_MORE_CNTL);
86 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
87 SCLK_MORE_CNTL__FORCE_MC_HOST);
88 OUTPLL(pllSCLK_MORE_CNTL, tmp);
89
90 tmp = INPLL(pllMCLK_CNTL);
91 tmp |= (MCLK_CNTL__FORCE_MCLKA |
92 MCLK_CNTL__FORCE_MCLKB |
93 MCLK_CNTL__FORCE_YCLKA |
94 MCLK_CNTL__FORCE_YCLKB |
95 MCLK_CNTL__FORCE_MC);
96 OUTPLL(pllMCLK_CNTL, tmp);
97
98 tmp = INPLL(pllVCLK_ECP_CNTL);
99 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
100 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
101 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
102 OUTPLL(pllVCLK_ECP_CNTL, tmp);
103
104 tmp = INPLL(pllPIXCLKS_CNTL);
105 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
106 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
107 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
108 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
109 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
110 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
111 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
112 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
113 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
114 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
115 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
116 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
117 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
118 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
119 OUTPLL(pllPIXCLKS_CNTL, tmp);
120
121 return;
122 }
123
124 /* Default */
125
126 /* Force Core Clocks */
127 tmp = INPLL(pllSCLK_CNTL);
128 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
129
130 /* XFree doesn't do that case, but we had this code from Apple and it
131 * seem necessary for proper suspend/resume operations
132 */
133 if (rinfo->is_mobility) {
134 tmp |= SCLK_CNTL__FORCE_HDP|
135 SCLK_CNTL__FORCE_DISP1|
136 SCLK_CNTL__FORCE_DISP2|
137 SCLK_CNTL__FORCE_TOP|
138 SCLK_CNTL__FORCE_SE|
139 SCLK_CNTL__FORCE_IDCT|
140 SCLK_CNTL__FORCE_VIP|
141 SCLK_CNTL__FORCE_PB|
142 SCLK_CNTL__FORCE_RE|
143 SCLK_CNTL__FORCE_TAM|
144 SCLK_CNTL__FORCE_TDM|
145 SCLK_CNTL__FORCE_RB|
146 SCLK_CNTL__FORCE_TV_SCLK|
147 SCLK_CNTL__FORCE_SUBPIC|
148 SCLK_CNTL__FORCE_OV0;
149 }
150 else if (rinfo->family == CHIP_FAMILY_R300 ||
151 rinfo->family == CHIP_FAMILY_R350) {
152 tmp |= SCLK_CNTL__FORCE_HDP |
153 SCLK_CNTL__FORCE_DISP1 |
154 SCLK_CNTL__FORCE_DISP2 |
155 SCLK_CNTL__FORCE_TOP |
156 SCLK_CNTL__FORCE_IDCT |
157 SCLK_CNTL__FORCE_VIP;
158 }
159 OUTPLL(pllSCLK_CNTL, tmp);
160 radeon_msleep(16);
161
162 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
163 tmp = INPLL(pllSCLK_CNTL2);
164 tmp |= SCLK_CNTL2__R300_FORCE_TCL |
165 SCLK_CNTL2__R300_FORCE_GA |
166 SCLK_CNTL2__R300_FORCE_CBA;
167 OUTPLL(pllSCLK_CNTL2, tmp);
168 radeon_msleep(16);
169 }
170
171 tmp = INPLL(pllCLK_PIN_CNTL);
172 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
173 OUTPLL(pllCLK_PIN_CNTL, tmp);
174 radeon_msleep(15);
175
176 if (rinfo->is_IGP) {
177 /* Weird ... X is _un_ forcing clocks here, I think it's
178 * doing backward. Imitate it for now...
179 */
180 tmp = INPLL(pllMCLK_CNTL);
181 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
182 MCLK_CNTL__FORCE_YCLKA);
183 OUTPLL(pllMCLK_CNTL, tmp);
184 radeon_msleep(16);
185 }
186 /* Hrm... same shit, X doesn't do that but I have to */
187 else if (rinfo->is_mobility) {
188 tmp = INPLL(pllMCLK_CNTL);
189 tmp |= (MCLK_CNTL__FORCE_MCLKA |
190 MCLK_CNTL__FORCE_MCLKB |
191 MCLK_CNTL__FORCE_YCLKA |
192 MCLK_CNTL__FORCE_YCLKB);
193 OUTPLL(pllMCLK_CNTL, tmp);
194 radeon_msleep(16);
195
196 tmp = INPLL(pllMCLK_MISC);
197 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
198 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
199 MCLK_MISC__MC_MCLK_DYN_ENABLE|
200 MCLK_MISC__IO_MCLK_DYN_ENABLE);
201 OUTPLL(pllMCLK_MISC, tmp);
202 radeon_msleep(15);
203 }
204
205 if (rinfo->is_mobility) {
206 tmp = INPLL(pllSCLK_MORE_CNTL);
207 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
208 SCLK_MORE_CNTL__FORCE_MC_GUI|
209 SCLK_MORE_CNTL__FORCE_MC_HOST;
210 OUTPLL(pllSCLK_MORE_CNTL, tmp);
211 radeon_msleep(16);
212 }
213
214 tmp = INPLL(pllPIXCLKS_CNTL);
215 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
216 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
217 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
218 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
219 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
220 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
221 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
222 OUTPLL(pllPIXCLKS_CNTL, tmp);
223 radeon_msleep(16);
224
225 tmp = INPLL( pllVCLK_ECP_CNTL);
226 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
227 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
228 OUTPLL( pllVCLK_ECP_CNTL, tmp);
229 radeon_msleep(16);
230 }
231
232 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
233 {
234 u32 tmp;
235
236 /* R100 */
237 if (!rinfo->has_CRTC2) {
238 tmp = INPLL(pllSCLK_CNTL);
239
240 if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
241 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
242 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
243 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
244 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
245 SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
246 SCLK_CNTL__FORCE_TDM);
247 OUTPLL(pllSCLK_CNTL, tmp);
248 return;
249 }
250
251 /* M10 */
252 if (rinfo->family == CHIP_FAMILY_RV350) {
253 tmp = INPLL(pllSCLK_CNTL2);
254 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
255 SCLK_CNTL2__R300_FORCE_GA |
256 SCLK_CNTL2__R300_FORCE_CBA);
257 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
258 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
259 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
260 OUTPLL(pllSCLK_CNTL2, tmp);
261
262 tmp = INPLL(pllSCLK_CNTL);
263 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
264 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
265 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
266 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
267 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
268 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
269 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
270 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
271 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
272 OUTPLL(pllSCLK_CNTL, tmp);
273
274 tmp = INPLL(pllSCLK_MORE_CNTL);
275 tmp &= ~SCLK_MORE_CNTL__FORCEON;
276 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
277 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
278 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
279 OUTPLL(pllSCLK_MORE_CNTL, tmp);
280
281 tmp = INPLL(pllVCLK_ECP_CNTL);
282 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
283 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
284 OUTPLL(pllVCLK_ECP_CNTL, tmp);
285
286 tmp = INPLL(pllPIXCLKS_CNTL);
287 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
288 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
289 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
290 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
291 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
292 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
293 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
294 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
295 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
296 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
297 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
298 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
299 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
300 OUTPLL(pllPIXCLKS_CNTL, tmp);
301
302 tmp = INPLL(pllMCLK_MISC);
303 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
304 MCLK_MISC__IO_MCLK_DYN_ENABLE);
305 OUTPLL(pllMCLK_MISC, tmp);
306
307 tmp = INPLL(pllMCLK_CNTL);
308 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
309 tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
310 MCLK_CNTL__FORCE_YCLKB |
311 MCLK_CNTL__FORCE_MC);
312
313 /* Some releases of vbios have set DISABLE_MC_MCLKA
314 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
315 * bits will cause H/W hang when reading video memory with dynamic
316 * clocking enabled.
317 */
318 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
319 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
320 /* If both bits are set, then check the active channels */
321 tmp = INPLL(pllMCLK_CNTL);
322 if (rinfo->vram_width == 64) {
323 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
324 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
325 else
326 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
327 } else {
328 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
329 MCLK_CNTL__R300_DISABLE_MC_MCLKB);
330 }
331 }
332 OUTPLL(pllMCLK_CNTL, tmp);
333 return;
334 }
335
336 /* R300 */
337 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
338 tmp = INPLL(pllSCLK_CNTL);
339 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
340 tmp |= SCLK_CNTL__FORCE_CP;
341 OUTPLL(pllSCLK_CNTL, tmp);
342 radeon_msleep(15);
343
344 tmp = INPLL(pllSCLK_CNTL2);
345 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
346 SCLK_CNTL2__R300_FORCE_GA |
347 SCLK_CNTL2__R300_FORCE_CBA);
348 OUTPLL(pllSCLK_CNTL2, tmp);
349 }
350
351 /* Others */
352
353 tmp = INPLL( pllCLK_PWRMGT_CNTL);
354 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
355 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
356 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
357 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
358 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
359 OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
360 radeon_msleep(15);
361
362 tmp = INPLL(pllCLK_PIN_CNTL);
363 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
364 OUTPLL(pllCLK_PIN_CNTL, tmp);
365 radeon_msleep(15);
366
367 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
368 * to lockup randomly, leave them as set by BIOS.
369 */
370 tmp = INPLL(pllSCLK_CNTL);
371 tmp &= ~SCLK_CNTL__FORCEON_MASK;
372
373 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
374 if ((rinfo->family == CHIP_FAMILY_RV250 &&
375 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
376 ((rinfo->family == CHIP_FAMILY_RV100) &&
377 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
378 tmp |= SCLK_CNTL__FORCE_CP;
379 tmp |= SCLK_CNTL__FORCE_VIP;
380 }
381 OUTPLL(pllSCLK_CNTL, tmp);
382 radeon_msleep(15);
383
384 if ((rinfo->family == CHIP_FAMILY_RV200) ||
385 (rinfo->family == CHIP_FAMILY_RV250) ||
386 (rinfo->family == CHIP_FAMILY_RV280)) {
387 tmp = INPLL(pllSCLK_MORE_CNTL);
388 tmp &= ~SCLK_MORE_CNTL__FORCEON;
389
390 /* RV200::A11 A12 RV250::A11 A12 */
391 if (((rinfo->family == CHIP_FAMILY_RV200) ||
392 (rinfo->family == CHIP_FAMILY_RV250)) &&
393 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
394 tmp |= SCLK_MORE_CNTL__FORCEON;
395
396 OUTPLL(pllSCLK_MORE_CNTL, tmp);
397 radeon_msleep(15);
398 }
399
400
401 /* RV200::A11 A12, RV250::A11 A12 */
402 if (((rinfo->family == CHIP_FAMILY_RV200) ||
403 (rinfo->family == CHIP_FAMILY_RV250)) &&
404 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
405 tmp = INPLL(pllPLL_PWRMGT_CNTL);
406 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
407 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
408 radeon_msleep(15);
409 }
410
411 tmp = INPLL(pllPIXCLKS_CNTL);
412 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
413 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
414 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
415 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
416 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
417 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
418 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
419 OUTPLL(pllPIXCLKS_CNTL, tmp);
420 radeon_msleep(15);
421
422 tmp = INPLL(pllVCLK_ECP_CNTL);
423 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
424 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
425 OUTPLL(pllVCLK_ECP_CNTL, tmp);
426
427 /* X doesn't do that ... hrm, we do on mobility && Macs */
428 #ifdef CONFIG_PPC_OF
429 if (rinfo->is_mobility) {
430 tmp = INPLL(pllMCLK_CNTL);
431 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
432 MCLK_CNTL__FORCE_MCLKB |
433 MCLK_CNTL__FORCE_YCLKA |
434 MCLK_CNTL__FORCE_YCLKB);
435 OUTPLL(pllMCLK_CNTL, tmp);
436 radeon_msleep(15);
437
438 tmp = INPLL(pllMCLK_MISC);
439 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
440 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
441 MCLK_MISC__MC_MCLK_DYN_ENABLE|
442 MCLK_MISC__IO_MCLK_DYN_ENABLE;
443 OUTPLL(pllMCLK_MISC, tmp);
444 radeon_msleep(15);
445 }
446 #endif /* CONFIG_PPC_OF */
447 }
448
449 #ifdef CONFIG_PM
450
451 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
452 {
453 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
454 OUTREG( MC_IND_DATA, value);
455 }
456
457 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
458 {
459 OUTREG( MC_IND_INDEX, indx);
460 return INREG( MC_IND_DATA);
461 }
462
463 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
464 {
465 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
466 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
467 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
468 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
469 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
470 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
471 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
472 rinfo->save_regs[7] = INPLL(MCLK_MISC);
473 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
474
475 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
476 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
477 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
478 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
479 rinfo->save_regs[14] = INREG(BUS_CNTL1);
480 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
481 rinfo->save_regs[16] = INREG(AGP_CNTL);
482 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
483 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
484 rinfo->save_regs[19] = INREG(GPIOPAD_A);
485 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
486 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
487 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
488 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
489 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
490 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
491 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
492 rinfo->save_regs[27] = INREG(GPIO_MONID);
493 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
494
495 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
496 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
497 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
498 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
499 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
500
501 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
502 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
503 rinfo->save_regs[36] = INREG(BUS_CNTL);
504 rinfo->save_regs[39] = INREG(RBBM_CNTL);
505 rinfo->save_regs[40] = INREG(DAC_CNTL);
506 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
507 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
508 rinfo->save_regs[38] = INREG(FCP_CNTL);
509
510 if (rinfo->is_mobility) {
511 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
512 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
513 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
514 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
515 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
516 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
517 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
518 }
519
520 if (rinfo->family >= CHIP_FAMILY_RV200) {
521 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
522 rinfo->save_regs[46] = INREG(MC_CNTL);
523 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
524 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
525 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
526 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
527 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
528 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
529 rinfo->save_regs[53] = INREG(MC_DEBUG);
530 }
531 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
532 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
533 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
534 rinfo->save_regs[57] = INREG(FW_CNTL);
535
536 if (rinfo->family >= CHIP_FAMILY_R300) {
537 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
538 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
539 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
540 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
541 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
542 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
543 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
544 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
545 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
546 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
547 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
548 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
549 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
550 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
551 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
552 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
553 } else {
554 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
555 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
556 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
557 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
558 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
559 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
560 }
561
562 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
563 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
564 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
565 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
566 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
567 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
568 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
569
570 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
571 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
572 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
573 rinfo->save_regs[84] = INREG(TMDS_CNTL);
574 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
575 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
576 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
577 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
578 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
579 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
580 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
581 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
582 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
583 rinfo->save_regs[96] = INREG(HDP_DEBUG);
584 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
585 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
586 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
587 }
588
589 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
590 {
591 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
592
593 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
594 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
595 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
596 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
597 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
598 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
599 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
600 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
601 if (rinfo->family == CHIP_FAMILY_RV350)
602 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
603
604 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
605 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
606 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
607 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
608 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
609 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
610
611 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
612 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
613 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
614 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
615 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
616 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
617 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
618 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
619 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
620 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
621 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
622
623 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
624 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
625 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
626 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
627 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
628 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
629 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
630 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
631 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
632 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
633 }
634
635 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
636 {
637 OUTREG(GPIOPAD_MASK, 0x0001ffff);
638 OUTREG(GPIOPAD_EN, 0x00000400);
639 OUTREG(GPIOPAD_A, 0x00000000);
640 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
641 OUTREG(ZV_LCDPAD_EN, 0x00000000);
642 OUTREG(ZV_LCDPAD_A, 0x00000000);
643 OUTREG(GPIO_VGA_DDC, 0x00030000);
644 OUTREG(GPIO_DVI_DDC, 0x00000000);
645 OUTREG(GPIO_MONID, 0x00030000);
646 OUTREG(GPIO_CRT2_DDC, 0x00000000);
647 }
648
649 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
650 {
651 /* Set v2clk to 65MHz */
652 if (rinfo->family <= CHIP_FAMILY_RV280) {
653 OUTPLL(pllPIXCLKS_CNTL,
654 __INPLL(rinfo, pllPIXCLKS_CNTL)
655 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
656
657 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
658 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
659 } else {
660 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
661 INPLL(pllP2PLL_REF_DIV);
662 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
663 }
664
665 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
666
667 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
668 mdelay(1);
669
670 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
671 mdelay( 1);
672
673 OUTPLL(pllPIXCLKS_CNTL,
674 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
675 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
676 mdelay( 1);
677 }
678
679 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
680 {
681 u32 reg;
682
683 reg = INREG(BUS_CNTL1);
684 if (rinfo->family <= CHIP_FAMILY_RV280) {
685 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
686 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
687 } else {
688 reg |= 0x4080;
689 }
690 OUTREG(BUS_CNTL1, reg);
691
692 reg = INPLL(PLL_PWRMGT_CNTL);
693 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
694 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
695 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
696 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
697 OUTPLL(PLL_PWRMGT_CNTL, reg);
698
699 reg = INREG(TV_DAC_CNTL);
700 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
701 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
702 TV_DAC_CNTL_BDACPD |
703 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
704 OUTREG(TV_DAC_CNTL, reg);
705
706 reg = INREG(TMDS_TRANSMITTER_CNTL);
707 reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
708 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
709
710 reg = INREG(DAC_CNTL);
711 reg &= ~DAC_CMP_EN;
712 OUTREG(DAC_CNTL, reg);
713
714 reg = INREG(DAC_CNTL2);
715 reg &= ~DAC2_CMP_EN;
716 OUTREG(DAC_CNTL2, reg);
717
718 reg = INREG(TV_DAC_CNTL);
719 reg &= ~TV_DAC_CNTL_DETECT;
720 OUTREG(TV_DAC_CNTL, reg);
721 }
722
723 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
724 {
725
726 u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
727
728 u32 pll_pwrmgt_cntl;
729 u32 clk_pwrmgt_cntl;
730 u32 clk_pin_cntl;
731 u32 vclk_ecp_cntl;
732 u32 pixclks_cntl;
733 u32 disp_mis_cntl;
734 u32 disp_pwr_man;
735 u32 tmp;
736
737 /* Force Core Clocks */
738 sclk_cntl = INPLL( pllSCLK_CNTL);
739 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
740 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
741 SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
742 SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
743 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
744 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
745 SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
746
747 SCLK_CNTL__FORCE_DISP2|
748 SCLK_CNTL__FORCE_CP|
749 SCLK_CNTL__FORCE_HDP|
750 SCLK_CNTL__FORCE_DISP1|
751 SCLK_CNTL__FORCE_TOP|
752 SCLK_CNTL__FORCE_E2|
753 SCLK_CNTL__FORCE_SE|
754 SCLK_CNTL__FORCE_IDCT|
755 SCLK_CNTL__FORCE_VIP|
756
757 SCLK_CNTL__FORCE_PB|
758 SCLK_CNTL__FORCE_TAM|
759 SCLK_CNTL__FORCE_TDM|
760 SCLK_CNTL__FORCE_RB|
761 SCLK_CNTL__FORCE_TV_SCLK|
762 SCLK_CNTL__FORCE_SUBPIC|
763 SCLK_CNTL__FORCE_OV0;
764 if (rinfo->family <= CHIP_FAMILY_RV280)
765 sclk_cntl |= SCLK_CNTL__FORCE_RE;
766 else
767 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
768 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
769 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
770 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
771 SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
772
773 OUTPLL( pllSCLK_CNTL, sclk_cntl);
774
775 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
776 sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
777 SCLK_MORE_CNTL__FORCE_MC_GUI |
778 SCLK_MORE_CNTL__FORCE_MC_HOST;
779
780 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
781
782
783 mclk_cntl = INPLL( pllMCLK_CNTL);
784 mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
785 MCLK_CNTL__FORCE_MCLKB |
786 MCLK_CNTL__FORCE_YCLKA |
787 MCLK_CNTL__FORCE_YCLKB |
788 MCLK_CNTL__FORCE_MC
789 );
790 OUTPLL( pllMCLK_CNTL, mclk_cntl);
791
792 /* Force Display clocks */
793 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
794 vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
795 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
796 vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
797 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
798
799
800 pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
801 pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
802 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
803 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
804 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
805 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
806 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
807 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
808
809 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
810
811 /* Switch off LVDS interface */
812 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
813 ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
814
815 /* Enable System power management */
816 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
817
818 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
819 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
820 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
821 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
822 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
823
824 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
825
826 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
827
828 clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
829 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
830 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
831 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
832 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
833 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
834 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
835 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
836 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
837 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
838 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
839 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
840 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
841 );
842
843 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
844 | CLK_PWRMGT_CNTL__DISP_PM;
845
846 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
847
848 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
849
850 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
851
852 /* because both INPLL and OUTPLL take the same lock, that's why. */
853 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
854 OUTPLL( pllMCLK_MISC, tmp);
855
856 /* AGP PLL control */
857 if (rinfo->family <= CHIP_FAMILY_RV280) {
858 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
859
860 OUTREG(BUS_CNTL1,
861 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
862 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
863 } else {
864 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
865 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
866 }
867
868 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
869 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
870
871 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
872 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
873 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
874
875 /* Solano2M */
876 OUTREG(AGP_CNTL,
877 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
878 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
879
880 /* ACPI mode */
881 /* because both INPLL and OUTPLL take the same lock, that's why. */
882 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
883 OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
884
885
886 disp_mis_cntl = INREG(DISP_MISC_CNTL);
887
888 disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
889 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
890 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
891 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
892 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
893 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
894 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
895 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
896 DISP_MISC_CNTL__SOFT_RESET_LVDS|
897 DISP_MISC_CNTL__SOFT_RESET_TMDS|
898 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
899 DISP_MISC_CNTL__SOFT_RESET_TV);
900
901 OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
902
903 disp_pwr_man = INREG(DISP_PWR_MAN);
904
905 disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
906 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
907 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
908 DISP_PWR_MAN__DISP_D3_RST|
909 DISP_PWR_MAN__DISP_D3_REG_RST
910 );
911
912 disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
913 DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
914 DISP_PWR_MAN__DISP_D3_OV0_RST|
915 DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
916 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
917 DISP_PWR_MAN__DISP_D1D2_OV0_RST|
918 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
919 DISP_PWR_MAN__TV_ENABLE_RST|
920 // DISP_PWR_MAN__AUTO_PWRUP_EN|
921 0;
922
923 OUTREG(DISP_PWR_MAN, disp_pwr_man);
924
925 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
926 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
927 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
928 disp_pwr_man = INREG(DISP_PWR_MAN);
929
930
931 /* D2 */
932 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
933 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
934 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
935 disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
936 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
937
938 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
939 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
940 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
941 OUTREG(DISP_PWR_MAN, disp_pwr_man);
942
943 /* disable display request & disable display */
944 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
945 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
946 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
947 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
948
949 mdelay(17);
950
951 }
952
953 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
954 {
955 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
956
957 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
958 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
959 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
960 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
961
962 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
963 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
964 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
965 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
966
967 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
968 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
969
970 mdelay( 1);
971 }
972
973 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
974 {
975 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
976
977 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
978 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
979 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
980 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
981
982 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
983 mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
984 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
985 mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
986
987 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
988 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
989
990 mdelay( 1);
991 }
992
993 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
994 u8 delay_required)
995 {
996 u32 mem_sdram_mode;
997
998 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
999
1000 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1001 mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1002 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1003 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1004 if (delay_required >= 2)
1005 mdelay(1);
1006
1007 mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1008 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1009 if (delay_required >= 2)
1010 mdelay(1);
1011
1012 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1013 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1014 if (delay_required >= 2)
1015 mdelay(1);
1016
1017 if (delay_required) {
1018 do {
1019 if (delay_required >= 2)
1020 mdelay(1);
1021 } while ((INREG(MC_STATUS)
1022 & (MC_STATUS__MEM_PWRUP_COMPL_A |
1023 MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1024 }
1025 }
1026
1027 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1028 {
1029 int cnt;
1030
1031 for (cnt = 0; cnt < 100; ++cnt) {
1032 mdelay(1);
1033 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1034 | MC_STATUS__MEM_PWRUP_COMPL_B))
1035 break;
1036 }
1037 }
1038
1039
1040 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1041 {
1042 #define DLL_RESET_DELAY 5
1043 #define DLL_SLEEP_DELAY 1
1044
1045 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
1046 | MDLL_CKO__MCKOA_RESET;
1047 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1048 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1049 | MDLL_RDCKA__MRDCKA1_RESET;
1050 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1051 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1052 | MDLL_RDCKB__MRDCKB1_RESET;
1053
1054 /* Setting up the DLL range for write */
1055 OUTPLL(pllMDLL_CKO, cko);
1056 OUTPLL(pllMDLL_RDCKA, cka);
1057 OUTPLL(pllMDLL_RDCKB, ckb);
1058
1059 mdelay(DLL_RESET_DELAY*2);
1060
1061 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1062 OUTPLL(pllMDLL_CKO, cko);
1063 mdelay(DLL_SLEEP_DELAY);
1064 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1065 OUTPLL(pllMDLL_CKO, cko);
1066 mdelay(DLL_RESET_DELAY);
1067
1068 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1069 OUTPLL(pllMDLL_RDCKA, cka);
1070 mdelay(DLL_SLEEP_DELAY);
1071 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1072 OUTPLL(pllMDLL_RDCKA, cka);
1073 mdelay(DLL_RESET_DELAY);
1074
1075 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1076 OUTPLL(pllMDLL_RDCKB, ckb);
1077 mdelay(DLL_SLEEP_DELAY);
1078 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1079 OUTPLL(pllMDLL_RDCKB, ckb);
1080 mdelay(DLL_RESET_DELAY);
1081
1082
1083 #undef DLL_RESET_DELAY
1084 #undef DLL_SLEEP_DELAY
1085 }
1086
1087 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1088 {
1089 u32 dll_value;
1090 u32 dll_sleep_mask = 0;
1091 u32 dll_reset_mask = 0;
1092 u32 mc;
1093
1094 #define DLL_RESET_DELAY 5
1095 #define DLL_SLEEP_DELAY 1
1096
1097 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1098 mc = INREG(MC_CNTL);
1099 /* Check which channels are enabled */
1100 switch (mc & 0x3) {
1101 case 1:
1102 if (mc & 0x4)
1103 break;
1104 case 2:
1105 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1106 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1107 case 0:
1108 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1109 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1110 }
1111 switch (mc & 0x3) {
1112 case 1:
1113 if (!(mc & 0x4))
1114 break;
1115 case 2:
1116 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1117 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1118 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1119 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1120 }
1121
1122 dll_value = INPLL(pllMDLL_RDCKA);
1123
1124 /* Power Up */
1125 dll_value &= ~(dll_sleep_mask);
1126 OUTPLL(pllMDLL_RDCKA, dll_value);
1127 mdelay( DLL_SLEEP_DELAY);
1128
1129 dll_value &= ~(dll_reset_mask);
1130 OUTPLL(pllMDLL_RDCKA, dll_value);
1131 mdelay( DLL_RESET_DELAY);
1132
1133 #undef DLL_RESET_DELAY
1134 #undef DLL_SLEEP_DELAY
1135 }
1136
1137
1138 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1139 {
1140 u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1141 fp_gen_cntl, fp2_gen_cntl;
1142
1143 crtcGenCntl = INREG( CRTC_GEN_CNTL);
1144 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1145
1146 crtc_more_cntl = INREG( CRTC_MORE_CNTL);
1147 fp_gen_cntl = INREG( FP_GEN_CNTL);
1148 fp2_gen_cntl = INREG( FP2_GEN_CNTL);
1149
1150
1151 OUTREG( CRTC_MORE_CNTL, 0);
1152 OUTREG( FP_GEN_CNTL, 0);
1153 OUTREG( FP2_GEN_CNTL,0);
1154
1155 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1156 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1157
1158 /* This is the code for the Aluminium PowerBooks M10 */
1159 if (rinfo->family == CHIP_FAMILY_RV350) {
1160 u32 sdram_mode_reg = rinfo->save_regs[35];
1161 static u32 default_mrtable[] =
1162 { 0x21320032,
1163 0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1164 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1165 0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1166 0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1167 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1168 0x31320032 };
1169
1170 u32 *mrtable = default_mrtable;
1171 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1172
1173 mdelay(30);
1174
1175 /* Disable refresh */
1176 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1177 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1178 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1179 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1180
1181 /* Configure and enable M & SPLLs */
1182 radeon_pm_enable_dll_m10(rinfo);
1183 radeon_pm_yclk_mclk_sync_m10(rinfo);
1184
1185 #ifdef CONFIG_PPC_OF
1186 if (rinfo->of_node != NULL) {
1187 int size;
1188
1189 mrtable = (u32 *)get_property(rinfo->of_node, "ATY,MRT", &size);
1190 if (mrtable)
1191 mrtable_size = size >> 2;
1192 else
1193 mrtable = default_mrtable;
1194 }
1195 #endif /* CONFIG_PPC_OF */
1196
1197 /* Program the SDRAM */
1198 sdram_mode_reg = mrtable[0];
1199 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1200 for (i = 0; i < mrtable_size; i++) {
1201 if (mrtable[i] == 0xffffffffu)
1202 radeon_pm_m10_program_mode_wait(rinfo);
1203 else {
1204 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1205 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1206 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1207 sdram_mode_reg |= mrtable[i];
1208
1209 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1210 mdelay(1);
1211 }
1212 }
1213
1214 /* Restore memory refresh */
1215 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1216 mdelay(30);
1217
1218 }
1219 /* Here come the desktop RV200 "QW" card */
1220 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1221 /* Disable refresh */
1222 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1223 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1224 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1225 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1226 mdelay(30);
1227
1228 /* Reset memory */
1229 OUTREG(MEM_SDRAM_MODE_REG,
1230 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1231
1232 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1233 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1234 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1235
1236 OUTREG(MEM_SDRAM_MODE_REG,
1237 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1238
1239 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1240
1241 }
1242 /* The M6 */
1243 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1244 /* Disable refresh */
1245 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1246 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1247
1248 /* Reset memory */
1249 OUTREG( MEM_SDRAM_MODE_REG,
1250 INREG( MEM_SDRAM_MODE_REG)
1251 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1252
1253 /* DLL */
1254 radeon_pm_enable_dll(rinfo);
1255
1256 /* MLCK / YCLK sync */
1257 radeon_pm_yclk_mclk_sync(rinfo);
1258
1259 /* Program Mode Register */
1260 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1261 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1262 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1263 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1264 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1265
1266 /* Complete & re-enable refresh */
1267 OUTREG( MEM_SDRAM_MODE_REG,
1268 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1269
1270 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1271 }
1272 /* And finally, the M7..M9 models, including M9+ (RV280) */
1273 else if (rinfo->is_mobility) {
1274
1275 /* Disable refresh */
1276 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1277 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1278 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1279 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1280
1281 /* Reset memory */
1282 OUTREG( MEM_SDRAM_MODE_REG,
1283 INREG( MEM_SDRAM_MODE_REG)
1284 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1285
1286 /* DLL */
1287 radeon_pm_enable_dll(rinfo);
1288
1289 /* MLCK / YCLK sync */
1290 radeon_pm_yclk_mclk_sync(rinfo);
1291
1292 /* M6, M7 and M9 so far ... */
1293 if (rinfo->family <= CHIP_FAMILY_RV250) {
1294 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1295 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1296 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1297 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1298 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1299 }
1300 /* M9+ (iBook G4) */
1301 else if (rinfo->family == CHIP_FAMILY_RV280) {
1302 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1303 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1304 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1305 }
1306
1307 /* Complete & re-enable refresh */
1308 OUTREG( MEM_SDRAM_MODE_REG,
1309 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1310
1311 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1312 }
1313
1314 OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
1315 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
1316 OUTREG( FP_GEN_CNTL, fp_gen_cntl);
1317 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
1318
1319 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
1320
1321 mdelay( 15);
1322 }
1323
1324 #ifdef CONFIG_PPC_OF
1325
1326 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1327 {
1328 u32 tmp, tmp2;
1329 int i,j;
1330
1331 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1332 INREG(PAD_CTLR_STRENGTH);
1333 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1334 tmp = INREG(PAD_CTLR_STRENGTH);
1335 for (i = j = 0; i < 65; ++i) {
1336 mdelay(1);
1337 tmp2 = INREG(PAD_CTLR_STRENGTH);
1338 if (tmp != tmp2) {
1339 tmp = tmp2;
1340 i = 0;
1341 j++;
1342 if (j > 10) {
1343 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1344 "stabilize !\n");
1345 break;
1346 }
1347 }
1348 }
1349 }
1350
1351 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1352 {
1353 u32 tmp;
1354
1355 tmp = INPLL(pllPPLL_CNTL);
1356 OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1357 tmp = INPLL(pllP2PLL_CNTL);
1358 OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1359 tmp = INPLL(pllSPLL_CNTL);
1360 OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1361 tmp = INPLL(pllMPLL_CNTL);
1362 OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1363 }
1364
1365 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1366 {
1367 u32 tmp;
1368
1369 /* Switch SPLL to PCI source */
1370 tmp = INPLL(pllSCLK_CNTL);
1371 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1372
1373 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1374 tmp = INPLL(pllSPLL_CNTL);
1375 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1376 radeon_pll_errata_after_index(rinfo);
1377 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1378 radeon_pll_errata_after_data(rinfo);
1379
1380 /* Set SPLL feedback divider */
1381 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1382 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1383 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1384
1385 /* Power up SPLL */
1386 tmp = INPLL(pllSPLL_CNTL);
1387 OUTPLL(pllSPLL_CNTL, tmp & ~1);
1388 (void)INPLL(pllSPLL_CNTL);
1389
1390 mdelay(10);
1391
1392 /* Release SPLL reset */
1393 tmp = INPLL(pllSPLL_CNTL);
1394 OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1395 (void)INPLL(pllSPLL_CNTL);
1396
1397 mdelay(10);
1398
1399 /* Select SCLK source */
1400 tmp = INPLL(pllSCLK_CNTL);
1401 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1402 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1403 OUTPLL(pllSCLK_CNTL, tmp);
1404 (void)INPLL(pllSCLK_CNTL);
1405
1406 mdelay(10);
1407
1408 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1409 tmp = INPLL(pllMPLL_CNTL);
1410 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1411 radeon_pll_errata_after_index(rinfo);
1412 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1413 radeon_pll_errata_after_data(rinfo);
1414
1415 /* Set MPLL feedback divider */
1416 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1417 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1418
1419 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1420 /* Power up MPLL */
1421 tmp = INPLL(pllMPLL_CNTL);
1422 OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1423 (void)INPLL(pllMPLL_CNTL);
1424
1425 mdelay(10);
1426
1427 /* Un-reset MPLL */
1428 tmp = INPLL(pllMPLL_CNTL);
1429 OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1430 (void)INPLL(pllMPLL_CNTL);
1431
1432 mdelay(10);
1433
1434 /* Select source for MCLK */
1435 tmp = INPLL(pllMCLK_CNTL);
1436 tmp |= rinfo->save_regs[2] & 0xffff;
1437 OUTPLL(pllMCLK_CNTL, tmp);
1438 (void)INPLL(pllMCLK_CNTL);
1439
1440 mdelay(10);
1441 }
1442
1443 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1444 {
1445 u32 r2ec;
1446
1447 /* GACK ! I though we didn't have a DDA on Radeon's anymore
1448 * here we rewrite with the same value, ... I suppose we clear
1449 * some bits that are already clear ? Or maybe this 0x2ec
1450 * register is something new ?
1451 */
1452 mdelay(20);
1453 r2ec = INREG(VGA_DDA_ON_OFF);
1454 OUTREG(VGA_DDA_ON_OFF, r2ec);
1455 mdelay(1);
1456
1457 /* Spread spectrum PLLL off */
1458 OUTPLL(pllSSPLL_CNTL, 0xbf03);
1459
1460 /* Spread spectrum disabled */
1461 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1462
1463 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1464 * value, not sure what for...
1465 */
1466
1467 r2ec |= 0x3f0;
1468 OUTREG(VGA_DDA_ON_OFF, r2ec);
1469 mdelay(1);
1470 }
1471
1472 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1473 {
1474 u32 r2ec, tmp;
1475
1476 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1477 * here we rewrite with the same value, ... I suppose we clear/set
1478 * some bits that are already clear/set ?
1479 */
1480 r2ec = INREG(VGA_DDA_ON_OFF);
1481 OUTREG(VGA_DDA_ON_OFF, r2ec);
1482 mdelay(1);
1483
1484 /* Enable spread spectrum */
1485 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1486 mdelay(3);
1487
1488 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1489 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1490 tmp = INPLL(pllSSPLL_CNTL);
1491 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1492 mdelay(6);
1493 tmp = INPLL(pllSSPLL_CNTL);
1494 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1495 mdelay(5);
1496
1497 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1498
1499 r2ec |= 8;
1500 OUTREG(VGA_DDA_ON_OFF, r2ec);
1501 mdelay(20);
1502
1503 /* Enable LVDS interface */
1504 tmp = INREG(LVDS_GEN_CNTL);
1505 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1506
1507 /* Enable LVDS_PLL */
1508 tmp = INREG(LVDS_PLL_CNTL);
1509 tmp &= ~0x30000;
1510 tmp |= 0x10000;
1511 OUTREG(LVDS_PLL_CNTL, tmp);
1512
1513 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1514 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1515
1516 /* The trace reads that one here, waiting for something to settle down ? */
1517 INREG(RBBM_STATUS);
1518
1519 /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1520 * R300 register spec at least...
1521 */
1522 tmp = INPLL(pllSS_TST_CNTL);
1523 tmp |= 0x00400000;
1524 OUTPLL(pllSS_TST_CNTL, tmp);
1525 }
1526
1527 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1528 {
1529 u32 tmp;
1530
1531 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1532 radeon_pll_errata_after_index(rinfo);
1533 OUTREG8(CLOCK_CNTL_DATA, 0);
1534 radeon_pll_errata_after_data(rinfo);
1535
1536 tmp = INPLL(pllVCLK_ECP_CNTL);
1537 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1538 mdelay(5);
1539
1540 tmp = INPLL(pllPPLL_REF_DIV);
1541 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1542 OUTPLL(pllPPLL_REF_DIV, tmp);
1543 INPLL(pllPPLL_REF_DIV);
1544
1545 /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1546 * probably useless since we already did it ...
1547 */
1548 tmp = INPLL(pllPPLL_CNTL);
1549 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1550 radeon_pll_errata_after_index(rinfo);
1551 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1552 radeon_pll_errata_after_data(rinfo);
1553
1554 /* Restore our "reference" PPLL divider set by firmware
1555 * according to proper spread spectrum calculations
1556 */
1557 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1558
1559 tmp = INPLL(pllPPLL_CNTL);
1560 OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1561 mdelay(5);
1562
1563 tmp = INPLL(pllPPLL_CNTL);
1564 OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1565 mdelay(5);
1566
1567 tmp = INPLL(pllVCLK_ECP_CNTL);
1568 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1569 mdelay(5);
1570
1571 tmp = INPLL(pllVCLK_ECP_CNTL);
1572 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1573 mdelay(5);
1574
1575 /* Switch pixel clock to firmware default div 0 */
1576 OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1577 radeon_pll_errata_after_index(rinfo);
1578 radeon_pll_errata_after_data(rinfo);
1579 }
1580
1581 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1582 {
1583 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1584 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1585 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1586 OUTREG(MEM_SDRAM_MODE_REG,
1587 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1588 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1589 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1590 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1591 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1592 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1593 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1594
1595 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1596 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1597 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1598 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1599 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1600 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1601 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1602 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1603 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1604 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1605 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1606 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1607 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1608 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1609 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1610 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1611 OUTREG(MC_IND_INDEX, 0);
1612 }
1613
1614 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1615 {
1616 u32 tmp, i;
1617
1618 /* Restore a bunch of registers first */
1619 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1620 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1621 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1622 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1623 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1624 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1625 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1626 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1627 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1628 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1629 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1630 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1631 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1632 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1633
1634 /* Hrm... */
1635 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1636
1637 /* Reset the PAD CTLR */
1638 radeon_pm_reset_pad_ctlr_strength(rinfo);
1639
1640 /* Some PLLs are Read & written identically in the trace here...
1641 * I suppose it's actually to switch them all off & reset,
1642 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1643 */
1644 radeon_pm_all_ppls_off(rinfo);
1645
1646 /* Clear tiling, reset swappers */
1647 INREG(SURFACE_CNTL);
1648 OUTREG(SURFACE_CNTL, 0);
1649
1650 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1651 * rather than hard coding...
1652 */
1653 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1654 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1655 OUTREG(TV_DAC_CNTL, tmp);
1656
1657 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1658 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1659 OUTREG(TV_DAC_CNTL, tmp);
1660
1661 /* More registers restored */
1662 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1663 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1664 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1665
1666 /* Hrmmm ... What is that ? */
1667 tmp = rinfo->save_regs[1]
1668 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1669 CLK_PWRMGT_CNTL__MC_BUSY);
1670 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1671
1672 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1673 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1674 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1675 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1676 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1677 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1678
1679 /* Restore Memory Controller configuration */
1680 radeon_pm_m10_reconfigure_mc(rinfo);
1681
1682 /* Make sure CRTC's dont touch memory */
1683 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1684 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1685 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1686 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1687 mdelay(30);
1688
1689 /* Disable SDRAM refresh */
1690 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1691 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1692
1693 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1694 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1695
1696 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1697 tmp = rinfo->save_regs[2] & 0xff000000;
1698 tmp |= MCLK_CNTL__FORCE_MCLKA |
1699 MCLK_CNTL__FORCE_MCLKB |
1700 MCLK_CNTL__FORCE_YCLKA |
1701 MCLK_CNTL__FORCE_YCLKB |
1702 MCLK_CNTL__FORCE_MC;
1703 OUTPLL(pllMCLK_CNTL, tmp);
1704
1705 /* Force all clocks on in SCLK */
1706 tmp = INPLL(pllSCLK_CNTL);
1707 tmp |= SCLK_CNTL__FORCE_DISP2|
1708 SCLK_CNTL__FORCE_CP|
1709 SCLK_CNTL__FORCE_HDP|
1710 SCLK_CNTL__FORCE_DISP1|
1711 SCLK_CNTL__FORCE_TOP|
1712 SCLK_CNTL__FORCE_E2|
1713 SCLK_CNTL__FORCE_SE|
1714 SCLK_CNTL__FORCE_IDCT|
1715 SCLK_CNTL__FORCE_VIP|
1716 SCLK_CNTL__FORCE_PB|
1717 SCLK_CNTL__FORCE_TAM|
1718 SCLK_CNTL__FORCE_TDM|
1719 SCLK_CNTL__FORCE_RB|
1720 SCLK_CNTL__FORCE_TV_SCLK|
1721 SCLK_CNTL__FORCE_SUBPIC|
1722 SCLK_CNTL__FORCE_OV0;
1723 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
1724 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1725 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1726 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1727 SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1728 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1729 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1730 SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
1731 SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
1732 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1733 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1734 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1735 OUTPLL(pllSCLK_CNTL, tmp);
1736
1737 OUTPLL(pllVCLK_ECP_CNTL, 0);
1738 OUTPLL(pllPIXCLKS_CNTL, 0);
1739 OUTPLL(pllMCLK_MISC,
1740 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1741 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1742
1743 mdelay(5);
1744
1745 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1746 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1747 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1748 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1749
1750 /* Now restore the major PLLs settings, keeping them off & reset though */
1751 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1752 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1753 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1754 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1755
1756 /* Restore MC DLL state and switch it off/reset too */
1757 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1758
1759 /* Switch MDLL off & reset */
1760 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1761 mdelay(5);
1762
1763 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1764 * 0xa1100007... and MacOS writes 0xa1000007 ..
1765 */
1766 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1767
1768 /* Restore more stuffs */
1769 OUTPLL(pllHTOTAL_CNTL, 0);
1770 OUTPLL(pllHTOTAL2_CNTL, 0);
1771
1772 /* More PLL initial configuration */
1773 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1774 OUTPLL(pllSCLK_CNTL2, tmp);
1775
1776 tmp = INPLL(pllSCLK_MORE_CNTL);
1777 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
1778 SCLK_MORE_CNTL__FORCE_MC_GUI |
1779 SCLK_MORE_CNTL__FORCE_MC_HOST;
1780 OUTPLL(pllSCLK_MORE_CNTL, tmp);
1781
1782 /* Now we actually start MCLK and SCLK */
1783 radeon_pm_start_mclk_sclk(rinfo);
1784
1785 /* Full reset sdrams, this also re-inits the MDLL */
1786 radeon_pm_full_reset_sdram(rinfo);
1787
1788 /* Fill palettes */
1789 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1790 for (i=0; i<256; i++)
1791 OUTREG(PALETTE_30_DATA, 0x15555555);
1792 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1793 udelay(20);
1794 for (i=0; i<256; i++)
1795 OUTREG(PALETTE_30_DATA, 0x15555555);
1796
1797 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1798 mdelay(3);
1799
1800 /* Restore TMDS */
1801 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1802 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1803
1804 /* Set LVDS registers but keep interface & pll down */
1805 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1806 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1807 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1808
1809 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1810
1811 /* Restore GPIOPAD state */
1812 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1813 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1814 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1815
1816 /* write some stuff to the framebuffer... */
1817 for (i = 0; i < 0x8000; ++i)
1818 writeb(0, rinfo->fb_base + i);
1819
1820 mdelay(40);
1821 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1822 mdelay(40);
1823
1824 /* Restore a few more things */
1825 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1826 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1827
1828 /* Take care of spread spectrum & PPLLs now */
1829 radeon_pm_m10_disable_spread_spectrum(rinfo);
1830 radeon_pm_restore_pixel_pll(rinfo);
1831
1832 /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1833 * code I have for blank/unblank doesn't quite work on some laptop models
1834 * it seems ... Hrm. What I have here works most of the time ...
1835 */
1836 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1837 }
1838
1839 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1840 {
1841 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1842 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1843 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1844 OUTREG(MEM_SDRAM_MODE_REG,
1845 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1846 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1847 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1848 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1849 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1850 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1851 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1852
1853 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1854 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1855 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1856 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1857 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1858 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1859 OUTREG(MC_IND_INDEX, 0);
1860 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1861
1862 mdelay(20);
1863 }
1864
1865 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1866 {
1867 u32 tmp, i;
1868
1869 /* Restore a bunch of registers first */
1870 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1871 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1872 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1873 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1874 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1875 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1876 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1877 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1878 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1879 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1880 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1881
1882 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1883 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1884
1885 /* Reset the PAD CTLR */
1886 radeon_pm_reset_pad_ctlr_strength(rinfo);
1887
1888 /* Some PLLs are Read & written identically in the trace here...
1889 * I suppose it's actually to switch them all off & reset,
1890 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1891 */
1892 radeon_pm_all_ppls_off(rinfo);
1893
1894 /* Clear tiling, reset swappers */
1895 INREG(SURFACE_CNTL);
1896 OUTREG(SURFACE_CNTL, 0);
1897
1898 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1899 * rather than hard coding...
1900 */
1901 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1902 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
1903 OUTREG(TV_DAC_CNTL, tmp);
1904
1905 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1906 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
1907 OUTREG(TV_DAC_CNTL, tmp);
1908
1909 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
1910
1911 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1912 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1913 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1914
1915 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1916 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
1917 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1918
1919 tmp = rinfo->save_regs[1]
1920 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1921 CLK_PWRMGT_CNTL__MC_BUSY);
1922 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1923
1924 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1925
1926 /* Disable SDRAM refresh */
1927 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1928 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1929
1930 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1931 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1932
1933 /* Force MCLK to be PCI sourced and forced ON */
1934 tmp = rinfo->save_regs[2] & 0xff000000;
1935 tmp |= MCLK_CNTL__FORCE_MCLKA |
1936 MCLK_CNTL__FORCE_MCLKB |
1937 MCLK_CNTL__FORCE_YCLKA |
1938 MCLK_CNTL__FORCE_YCLKB |
1939 MCLK_CNTL__FORCE_MC |
1940 MCLK_CNTL__FORCE_AIC;
1941 OUTPLL(pllMCLK_CNTL, tmp);
1942
1943 /* Force SCLK to be PCI sourced with a bunch forced */
1944 tmp = 0 |
1945 SCLK_CNTL__FORCE_DISP2|
1946 SCLK_CNTL__FORCE_CP|
1947 SCLK_CNTL__FORCE_HDP|
1948 SCLK_CNTL__FORCE_DISP1|
1949 SCLK_CNTL__FORCE_TOP|
1950 SCLK_CNTL__FORCE_E2|
1951 SCLK_CNTL__FORCE_SE|
1952 SCLK_CNTL__FORCE_IDCT|
1953 SCLK_CNTL__FORCE_VIP|
1954 SCLK_CNTL__FORCE_RE|
1955 SCLK_CNTL__FORCE_PB|
1956 SCLK_CNTL__FORCE_TAM|
1957 SCLK_CNTL__FORCE_TDM|
1958 SCLK_CNTL__FORCE_RB;
1959 OUTPLL(pllSCLK_CNTL, tmp);
1960
1961 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
1962 OUTPLL(pllVCLK_ECP_CNTL, 0);
1963 OUTPLL(pllPIXCLKS_CNTL, 0);
1964
1965 /* Setup MCLK_MISC, non dynamic mode */
1966 OUTPLL(pllMCLK_MISC,
1967 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1968 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1969
1970 mdelay(5);
1971
1972 /* Set back the default clock dividers */
1973 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1974 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1975 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1976
1977 /* PPLL and P2PLL default values & off */
1978 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1979 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1980
1981 /* S and M PLLs are reset & off, configure them */
1982 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1983 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1984
1985 /* Default values for MDLL ... fixme */
1986 OUTPLL(pllMDLL_CKO, 0x9c009c);
1987 OUTPLL(pllMDLL_RDCKA, 0x08830883);
1988 OUTPLL(pllMDLL_RDCKB, 0x08830883);
1989 mdelay(5);
1990
1991 /* Restore PLL_PWRMGT_CNTL */ // XXXX
1992 tmp = rinfo->save_regs[0];
1993 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
1994 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
1995 OUTPLL(PLL_PWRMGT_CNTL, tmp);
1996
1997 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
1998 OUTPLL(pllHTOTAL_CNTL, 0);
1999 OUTPLL(pllHTOTAL2_CNTL, 0);
2000
2001 /* All outputs off */
2002 OUTREG(CRTC_GEN_CNTL, 0x04000000);
2003 OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2004 OUTREG(FP_GEN_CNTL, 0x00004008);
2005 OUTREG(FP2_GEN_CNTL, 0x00000008);
2006 OUTREG(LVDS_GEN_CNTL, 0x08000008);
2007
2008 /* Restore Memory Controller configuration */
2009 radeon_pm_m9p_reconfigure_mc(rinfo);
2010
2011 /* Now we actually start MCLK and SCLK */
2012 radeon_pm_start_mclk_sclk(rinfo);
2013
2014 /* Full reset sdrams, this also re-inits the MDLL */
2015 radeon_pm_full_reset_sdram(rinfo);
2016
2017 /* Fill palettes */
2018 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2019 for (i=0; i<256; i++)
2020 OUTREG(PALETTE_30_DATA, 0x15555555);
2021 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2022 udelay(20);
2023 for (i=0; i<256; i++)
2024 OUTREG(PALETTE_30_DATA, 0x15555555);
2025
2026 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2027 mdelay(3);
2028
2029 /* Restore TV stuff, make sure TV DAC is down */
2030 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2031 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2032
2033 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2034 * possibly related to the weird PLL related workarounds and to the
2035 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2036 * but we keep things the simple way here
2037 */
2038 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2039 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2040 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2041
2042 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2043 * high bits from backup
2044 */
2045 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2046 tmp |= rinfo->save_regs[34] & 0xffff0000;
2047 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2048 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2049
2050 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2051 tmp |= rinfo->save_regs[34] & 0xffff0000;
2052 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2053 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2054
2055 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2056 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2057 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2058 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2059 mdelay(20);
2060
2061 /* write some stuff to the framebuffer... */
2062 for (i = 0; i < 0x8000; ++i)
2063 writeb(0, rinfo->fb_base + i);
2064
2065 OUTREG(0x2ec, 0x6332a020);
2066 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2067 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2068 tmp = INPLL(pllSSPLL_CNTL);
2069 tmp &= ~2;
2070 OUTPLL(pllSSPLL_CNTL, tmp);
2071 mdelay(6);
2072 tmp &= ~1;
2073 OUTPLL(pllSSPLL_CNTL, tmp);
2074 mdelay(5);
2075 tmp |= 3;
2076 OUTPLL(pllSSPLL_CNTL, tmp);
2077 mdelay(5);
2078
2079 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2080 OUTREG(0x2ec, 0x6332a3f0);
2081 mdelay(17);
2082
2083 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);;
2084 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2085
2086 mdelay(40);
2087 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2088 mdelay(40);
2089
2090 /* Restore a few more things */
2091 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2092 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2093
2094 /* Restore PPLL, spread spectrum & LVDS */
2095 radeon_pm_m10_disable_spread_spectrum(rinfo);
2096 radeon_pm_restore_pixel_pll(rinfo);
2097 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2098 }
2099
2100 #if 0 /* Not ready yet */
2101 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2102 {
2103 int i;
2104 u32 tmp, tmp2;
2105 u32 cko, cka, ckb;
2106 u32 cgc, cec, c2gc;
2107
2108 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2109 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2110 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2111 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2112 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2113 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2114
2115 INREG(PAD_CTLR_STRENGTH);
2116 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2117 for (i = 0; i < 65; ++i) {
2118 mdelay(1);
2119 INREG(PAD_CTLR_STRENGTH);
2120 }
2121
2122 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2123 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2124 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2125 OUTREG(DAC_CNTL, 0xff00410a);
2126 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2127 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2128
2129 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2130 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2131 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2132 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2133
2134 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2135 OUTREG(MC_IND_INDEX, 0);
2136 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2137 OUTREG(MC_IND_INDEX, 0);
2138
2139 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2140
2141 tmp = INPLL(pllVCLK_ECP_CNTL);
2142 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2143 tmp = INPLL(pllPIXCLKS_CNTL);
2144 OUTPLL(pllPIXCLKS_CNTL, tmp);
2145
2146 OUTPLL(MCLK_CNTL, 0xaa3f0000);
2147 OUTPLL(SCLK_CNTL, 0xffff0000);
2148 OUTPLL(pllMPLL_AUX_CNTL, 6);
2149 OUTPLL(pllSPLL_AUX_CNTL, 1);
2150 OUTPLL(MDLL_CKO, 0x9f009f);
2151 OUTPLL(MDLL_RDCKA, 0x830083);
2152 OUTPLL(pllMDLL_RDCKB, 0x830083);
2153 OUTPLL(PPLL_CNTL, 0xa433);
2154 OUTPLL(P2PLL_CNTL, 0xa433);
2155 OUTPLL(MPLL_CNTL, 0x0400a403);
2156 OUTPLL(SPLL_CNTL, 0x0400a433);
2157
2158 tmp = INPLL(M_SPLL_REF_FB_DIV);
2159 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2160 tmp = INPLL(M_SPLL_REF_FB_DIV);
2161 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2162 INPLL(M_SPLL_REF_FB_DIV);
2163
2164 tmp = INPLL(MPLL_CNTL);
2165 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2166 radeon_pll_errata_after_index(rinfo);
2167 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2168 radeon_pll_errata_after_data(rinfo);
2169
2170 tmp = INPLL(M_SPLL_REF_FB_DIV);
2171 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2172
2173 tmp = INPLL(MPLL_CNTL);
2174 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2175 mdelay(1);
2176 tmp = INPLL(MPLL_CNTL);
2177 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2178 mdelay(10);
2179
2180 OUTPLL(MCLK_CNTL, 0xaa3f1212);
2181 mdelay(1);
2182
2183 INPLL(M_SPLL_REF_FB_DIV);
2184 INPLL(MCLK_CNTL);
2185 INPLL(M_SPLL_REF_FB_DIV);
2186
2187 tmp = INPLL(SPLL_CNTL);
2188 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2189 radeon_pll_errata_after_index(rinfo);
2190 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2191 radeon_pll_errata_after_data(rinfo);
2192
2193 tmp = INPLL(M_SPLL_REF_FB_DIV);
2194 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2195
2196 tmp = INPLL(SPLL_CNTL);
2197 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2198 mdelay(1);
2199 tmp = INPLL(SPLL_CNTL);
2200 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2201 mdelay(10);
2202
2203 tmp = INPLL(SCLK_CNTL);
2204 OUTPLL(SCLK_CNTL, tmp | 2);
2205 mdelay(1);
2206
2207 cko = INPLL(pllMDLL_CKO);
2208 cka = INPLL(pllMDLL_RDCKA);
2209 ckb = INPLL(pllMDLL_RDCKB);
2210
2211 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2212 OUTPLL(pllMDLL_CKO, cko);
2213 mdelay(1);
2214 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2215 OUTPLL(pllMDLL_CKO, cko);
2216 mdelay(5);
2217
2218 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2219 OUTPLL(pllMDLL_RDCKA, cka);
2220 mdelay(1);
2221 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2222 OUTPLL(pllMDLL_RDCKA, cka);
2223 mdelay(5);
2224
2225 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2226 OUTPLL(pllMDLL_RDCKB, ckb);
2227 mdelay(1);
2228 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2229 OUTPLL(pllMDLL_RDCKB, ckb);
2230 mdelay(5);
2231
2232 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2233 OUTREG(MC_IND_INDEX, 0);
2234 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2235 OUTREG(MC_IND_INDEX, 0);
2236 mdelay(1);
2237 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2238 OUTREG(MC_IND_INDEX, 0);
2239 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2240 OUTREG(MC_IND_INDEX, 0);
2241 mdelay(1);
2242
2243 OUTPLL(pllHTOTAL_CNTL, 0);
2244 OUTPLL(pllHTOTAL2_CNTL, 0);
2245
2246 OUTREG(MEM_CNTL, 0x29002901);
2247 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2248 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2249 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2250 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2251 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2252 OUTREG(MC_DEBUG, 0);
2253 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2254
2255 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2256 OUTREG(MC_IND_INDEX, 0);
2257 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2258 OUTREG(MC_IND_INDEX, 0);
2259
2260 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2261
2262 radeon_pm_full_reset_sdram(rinfo);
2263
2264 INREG(FP_GEN_CNTL);
2265 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2266 tmp = INREG(FP_GEN_CNTL);
2267 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2268 OUTREG(FP_GEN_CNTL, tmp);
2269
2270 tmp = INREG(DISP_OUTPUT_CNTL);
2271 tmp &= ~0x400;
2272 OUTREG(DISP_OUTPUT_CNTL, tmp);
2273
2274 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2275 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2276 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2277
2278 tmp = INPLL(MCLK_MISC);
2279 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2280 OUTPLL(MCLK_MISC, tmp);
2281
2282 tmp = INPLL(SCLK_CNTL);
2283 OUTPLL(SCLK_CNTL, tmp);
2284
2285 OUTREG(CRTC_MORE_CNTL, 0);
2286 OUTREG8(CRTC_GEN_CNTL+1, 6);
2287 OUTREG8(CRTC_GEN_CNTL+3, 1);
2288 OUTREG(CRTC_PITCH, 32);
2289
2290 tmp = INPLL(VCLK_ECP_CNTL);
2291 OUTPLL(VCLK_ECP_CNTL, tmp);
2292
2293 tmp = INPLL(PPLL_CNTL);
2294 OUTPLL(PPLL_CNTL, tmp);
2295
2296 /* palette stuff and BIOS_1_SCRATCH... */
2297
2298 tmp = INREG(FP_GEN_CNTL);
2299 tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2300 tmp |= 2;
2301 OUTREG(FP_GEN_CNTL, tmp);
2302 mdelay(5);
2303 OUTREG(FP_GEN_CNTL, tmp);
2304 mdelay(5);
2305 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2306 OUTREG(CRTC_MORE_CNTL, 0);
2307 mdelay(20);
2308
2309 tmp = INREG(CRTC_MORE_CNTL);
2310 OUTREG(CRTC_MORE_CNTL, tmp);
2311
2312 cgc = INREG(CRTC_GEN_CNTL);
2313 cec = INREG(CRTC_EXT_CNTL);
2314 c2gc = INREG(CRTC2_GEN_CNTL);
2315
2316 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2317 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2318 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2319 radeon_pll_errata_after_index(rinfo);
2320 OUTREG8(CLOCK_CNTL_DATA, 0);
2321 radeon_pll_errata_after_data(rinfo);
2322 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2323 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2324 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2325 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2326 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2327 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2328 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2329 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2330 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2331 OUTREG(FP_HORZ_STRETCH, 0);
2332 OUTREG(FP_VERT_STRETCH, 0);
2333 OUTREG(OVR_CLR, 0);
2334 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2335 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2336
2337 tmp = INPLL(PPLL_REF_DIV);
2338 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2339 OUTPLL(PPLL_REF_DIV, tmp);
2340 INPLL(PPLL_REF_DIV);
2341
2342 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2343 radeon_pll_errata_after_index(rinfo);
2344 OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2345 radeon_pll_errata_after_data(rinfo);
2346
2347 tmp = INREG(CLOCK_CNTL_INDEX);
2348 radeon_pll_errata_after_index(rinfo);
2349 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2350 radeon_pll_errata_after_index(rinfo);
2351 radeon_pll_errata_after_data(rinfo);
2352
2353 OUTPLL(PPLL_DIV_0, 0x48090);
2354
2355 tmp = INPLL(PPLL_CNTL);
2356 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2357 mdelay(1);
2358 tmp = INPLL(PPLL_CNTL);
2359 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2360 mdelay(10);
2361
2362 tmp = INPLL(VCLK_ECP_CNTL);
2363 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2364 mdelay(1);
2365
2366 tmp = INPLL(VCLK_ECP_CNTL);
2367 OUTPLL(VCLK_ECP_CNTL, tmp);
2368
2369 c2gc |= CRTC2_DISP_REQ_EN_B;
2370 OUTREG(CRTC2_GEN_CNTL, c2gc);
2371 cgc |= CRTC_EN;
2372 OUTREG(CRTC_GEN_CNTL, cgc);
2373 OUTREG(CRTC_EXT_CNTL, cec);
2374 OUTREG(CRTC_PITCH, 0xa0);
2375 OUTREG(CRTC_OFFSET, 0);
2376 OUTREG(CRTC_OFFSET_CNTL, 0);
2377
2378 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2379 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2380
2381 tmp2 = INREG(FP_GEN_CNTL);
2382 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2383 OUTREG(0x2a8, 0x0000061b);
2384 tmp |= TMDS_PLL_EN;
2385 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2386 mdelay(1);
2387 tmp &= ~TMDS_PLLRST;
2388 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2389 tmp2 &= ~2;
2390 tmp2 |= FP_TMDS_EN;
2391 OUTREG(FP_GEN_CNTL, tmp2);
2392 mdelay(5);
2393 tmp2 |= FP_FPON;
2394 OUTREG(FP_GEN_CNTL, tmp2);
2395
2396 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2397 cgc = INREG(CRTC_GEN_CNTL);
2398 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2399 cgc |= 0x10000;
2400 OUTREG(CUR_OFFSET, 0);
2401 }
2402 #endif /* 0 */
2403
2404 #endif /* CONFIG_PPC_OF */
2405
2406 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2407 {
2408 u16 pwr_cmd;
2409 u32 tmp;
2410 int i;
2411
2412 if (!rinfo->pm_reg)
2413 return;
2414
2415 /* Set the chip into appropriate suspend mode (we use D2,
2416 * D3 would require a compete re-initialization of the chip,
2417 * including PCI config registers, clocks, AGP conf, ...)
2418 */
2419 if (suspend) {
2420 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2421 pci_name(rinfo->pdev));
2422
2423 /* Disable dynamic power management of clocks for the
2424 * duration of the suspend/resume process
2425 */
2426 radeon_pm_disable_dynamic_mode(rinfo);
2427
2428 /* Save some registers */
2429 radeon_pm_save_regs(rinfo, 0);
2430
2431 /* Prepare mobility chips for suspend.
2432 */
2433 if (rinfo->is_mobility) {
2434 /* Program V2CLK */
2435 radeon_pm_program_v2clk(rinfo);
2436
2437 /* Disable IO PADs */
2438 radeon_pm_disable_iopad(rinfo);
2439
2440 /* Set low current */
2441 radeon_pm_low_current(rinfo);
2442
2443 /* Prepare chip for power management */
2444 radeon_pm_setup_for_suspend(rinfo);
2445
2446 if (rinfo->family <= CHIP_FAMILY_RV280) {
2447 /* Reset the MDLL */
2448 /* because both INPLL and OUTPLL take the same
2449 * lock, that's why. */
2450 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2451 | MDLL_CKO__MCKOB_RESET;
2452 OUTPLL( pllMDLL_CKO, tmp );
2453 }
2454 }
2455
2456 for (i = 0; i < 64; ++i)
2457 pci_read_config_dword(rinfo->pdev, i * 4,
2458 &rinfo->cfg_save[i]);
2459
2460 /* Switch PCI power managment to D2. */
2461 pci_disable_device(rinfo->pdev);
2462 for (;;) {
2463 pci_read_config_word(
2464 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2465 &pwr_cmd);
2466 if (pwr_cmd & 2)
2467 break;
2468 pci_write_config_word(
2469 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2470 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2471 mdelay(500);
2472 }
2473 } else {
2474 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2475 pci_name(rinfo->pdev));
2476
2477 /* Switch back PCI powermanagment to D0 */
2478 mdelay(200);
2479 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2480 mdelay(500);
2481
2482 if (rinfo->family <= CHIP_FAMILY_RV250) {
2483 /* Reset the SDRAM controller */
2484 radeon_pm_full_reset_sdram(rinfo);
2485
2486 /* Restore some registers */
2487 radeon_pm_restore_regs(rinfo);
2488 } else {
2489 /* Restore registers first */
2490 radeon_pm_restore_regs(rinfo);
2491 /* init sdram controller */
2492 radeon_pm_full_reset_sdram(rinfo);
2493 }
2494 }
2495 }
2496
2497 static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo)
2498 {
2499 int i;
2500 static u32 radeon_cfg_after_resume[64];
2501
2502 for (i = 0; i < 64; ++i)
2503 pci_read_config_dword(rinfo->pdev, i * 4,
2504 &radeon_cfg_after_resume[i]);
2505
2506 if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4]
2507 == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4])
2508 return 0; /* assume everything is ok */
2509
2510 for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) {
2511 if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i])
2512 pci_write_config_dword(rinfo->pdev, i * 4,
2513 rinfo->cfg_save[i]);
2514 }
2515 pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE,
2516 rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]);
2517 pci_write_config_word(rinfo->pdev, PCI_COMMAND,
2518 rinfo->cfg_save[PCI_COMMAND/4]);
2519 return 1;
2520 }
2521
2522
2523 static/*extern*/ int susdisking = 0;
2524
2525 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2526 {
2527 struct fb_info *info = pci_get_drvdata(pdev);
2528 struct radeonfb_info *rinfo = info->par;
2529 u8 agp;
2530 int i;
2531
2532 if (state == pdev->dev.power.power_state)
2533 return 0;
2534
2535 printk(KERN_DEBUG "radeonfb (%s): suspending to state: %d...\n",
2536 pci_name(pdev), state);
2537
2538 /* For suspend-to-disk, we cheat here. We don't suspend anything and
2539 * let fbcon continue drawing until we are all set. That shouldn't
2540 * really cause any problem at this point, provided that the wakeup
2541 * code knows that any state in memory may not match the HW
2542 */
2543 if (state != PM_SUSPEND_MEM)
2544 goto done;
2545 if (susdisking) {
2546 printk("radeonfb (%s): suspending to disk but state = %d\n",
2547 pci_name(pdev), state);
2548 goto done;
2549 }
2550
2551 acquire_console_sem();
2552
2553 fb_set_suspend(info, 1);
2554
2555 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2556 /* Make sure engine is reset */
2557 radeon_engine_idle();
2558 radeonfb_engine_reset(rinfo);
2559 radeon_engine_idle();
2560 }
2561
2562 /* Blank display and LCD */
2563 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2564
2565 /* Sleep */
2566 rinfo->asleep = 1;
2567 rinfo->lock_blank = 1;
2568 del_timer_sync(&rinfo->lvds_timer);
2569
2570 /* Disable AGP. The AGP host should have done it, but since ordering
2571 * isn't always properly guaranteed in this specific case, let's make
2572 * sure it's disabled on card side now. Ultimately, when merging fbdev
2573 * and dri into some common infrastructure, this will be handled
2574 * more nicely. The host bridge side will (or will not) be dealt with
2575 * by the bridge AGP driver, we don't attempt to touch it here.
2576 */
2577 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2578 if (agp) {
2579 u32 cmd;
2580
2581 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
2582 if (cmd & PCI_AGP_COMMAND_AGP) {
2583 printk(KERN_INFO "radeonfb (%s): AGP was enabled, "
2584 "disabling ...\n",
2585 pci_name(pdev));
2586 cmd &= ~PCI_AGP_COMMAND_AGP;
2587 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND,
2588 cmd);
2589 }
2590 }
2591
2592 /* If we support wakeup from poweroff, we save all regs we can including cfg
2593 * space
2594 */
2595 if (rinfo->pm_mode & radeon_pm_off) {
2596 /* Always disable dynamic clocks or weird things are happening when
2597 * the chip goes off (basically the panel doesn't shut down properly
2598 * and we crash on wakeup),
2599 * also, we want the saved regs context to have no dynamic clocks in
2600 * it, we'll restore the dynamic clocks state on wakeup
2601 */
2602 radeon_pm_disable_dynamic_mode(rinfo);
2603 mdelay(50);
2604 radeon_pm_save_regs(rinfo, 1);
2605
2606 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2607 /* Switch off LVDS interface */
2608 mdelay(1);
2609 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2610 mdelay(1);
2611 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2612 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2613 mdelay(20);
2614 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2615 }
2616 // FIXME: Use PCI layer
2617 for (i = 0; i < 64; ++i)
2618 pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]);
2619 pci_disable_device(pdev);
2620 }
2621 /* If we support D2, we go to it (should be fixed later with a flag forcing
2622 * D3 only for some laptops)
2623 */
2624 if (rinfo->pm_mode & radeon_pm_d2)
2625 radeon_set_suspend(rinfo, 1);
2626
2627 release_console_sem();
2628
2629 done:
2630 pdev->dev.power.power_state = state;
2631
2632 return 0;
2633 }
2634
2635 int radeonfb_pci_resume(struct pci_dev *pdev)
2636 {
2637 struct fb_info *info = pci_get_drvdata(pdev);
2638 struct radeonfb_info *rinfo = info->par;
2639 int rc = 0;
2640
2641 if (pdev->dev.power.power_state == 0)
2642 return 0;
2643
2644 if (rinfo->no_schedule) {
2645 if (try_acquire_console_sem())
2646 return 0;
2647 } else
2648 acquire_console_sem();
2649
2650 printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2651 pci_name(pdev), pdev->dev.power.power_state);
2652
2653
2654 if (pci_enable_device(pdev)) {
2655 rc = -ENODEV;
2656 printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n",
2657 pci_name(pdev));
2658 goto bail;
2659 }
2660 pci_set_master(pdev);
2661
2662 if (pdev->dev.power.power_state == PM_SUSPEND_MEM) {
2663 /* Wakeup chip. Check from config space if we were powered off
2664 * (todo: additionally, check CLK_PIN_CNTL too)
2665 */
2666 if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) {
2667 if (rinfo->reinit_func != NULL)
2668 rinfo->reinit_func(rinfo);
2669 else {
2670 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2671 " D3 cold, need softboot !", pci_name(pdev));
2672 rc = -EIO;
2673 goto bail;
2674 }
2675 }
2676 /* If we support D2, try to resume... we should check what was our
2677 * state though... (were we really in D2 state ?). Right now, this code
2678 * is only enable on Macs so it's fine.
2679 */
2680 else if (rinfo->pm_mode & radeon_pm_d2)
2681 radeon_set_suspend(rinfo, 0);
2682
2683 rinfo->asleep = 0;
2684 } else
2685 radeon_engine_idle();
2686
2687 /* Restore display & engine */
2688 radeon_write_mode (rinfo, &rinfo->state, 1);
2689 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2690 radeonfb_engine_init (rinfo);
2691
2692 fb_pan_display(info, &info->var);
2693 fb_set_cmap(&info->cmap, info);
2694
2695 /* Refresh */
2696 fb_set_suspend(info, 0);
2697
2698 /* Unblank */
2699 rinfo->lock_blank = 0;
2700 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2701
2702 /* Check status of dynclk */
2703 if (rinfo->dynclk == 1)
2704 radeon_pm_enable_dynamic_mode(rinfo);
2705 else if (rinfo->dynclk == 0)
2706 radeon_pm_disable_dynamic_mode(rinfo);
2707
2708 pdev->dev.power.power_state = PMSG_ON;
2709
2710 bail:
2711 release_console_sem();
2712
2713 return rc;
2714 }
2715
2716 #ifdef CONFIG_PPC_OF
2717 static void radeonfb_early_resume(void *data)
2718 {
2719 struct radeonfb_info *rinfo = data;
2720
2721 rinfo->no_schedule = 1;
2722 radeonfb_pci_resume(rinfo->pdev);
2723 rinfo->no_schedule = 0;
2724 }
2725 #endif /* CONFIG_PPC_OF */
2726
2727 #endif /* CONFIG_PM */
2728
2729 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk)
2730 {
2731 /* Find PM registers in config space if any*/
2732 rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2733
2734 /* Enable/Disable dynamic clocks: TODO add sysfs access */
2735 rinfo->dynclk = dynclk;
2736 if (dynclk == 1) {
2737 radeon_pm_enable_dynamic_mode(rinfo);
2738 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2739 } else if (dynclk == 0) {
2740 radeon_pm_disable_dynamic_mode(rinfo);
2741 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2742 }
2743
2744 /* Check if we can power manage on suspend/resume. We can do
2745 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2746 * "Mac" cards, but that's all. We need more infos about what the
2747 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2748 * reason. --BenH
2749 */
2750 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2751 if (_machine == _MACH_Pmac && rinfo->of_node) {
2752 if (rinfo->is_mobility && rinfo->pm_reg &&
2753 rinfo->family <= CHIP_FAMILY_RV250)
2754 rinfo->pm_mode |= radeon_pm_d2;
2755
2756 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2757 * in some desktop G4s), and Via (M9+ chip on iBook G4)
2758 */
2759 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent")) {
2760 rinfo->reinit_func = radeon_reinitialize_M10;
2761 rinfo->pm_mode |= radeon_pm_off;
2762 }
2763 #if 0 /* Not ready yet */
2764 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2765 rinfo->reinit_func = radeon_reinitialize_QW;
2766 rinfo->pm_mode |= radeon_pm_off;
2767 }
2768 #endif
2769 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2770 rinfo->reinit_func = radeon_reinitialize_M9P;
2771 rinfo->pm_mode |= radeon_pm_off;
2772 }
2773
2774 /* If any of the above is set, we assume the machine can sleep/resume.
2775 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2776 * from the platform about what happens to the chip...
2777 * Now we tell the platform about our capability
2778 */
2779 if (rinfo->pm_mode != radeon_pm_none) {
2780 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2781 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2782 }
2783
2784 #if 0
2785 /* Power down TV DAC, taht saves a significant amount of power,
2786 * we'll have something better once we actually have some TVOut
2787 * support
2788 */
2789 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2790 #endif
2791 }
2792 #endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */
2793 }
2794
2795 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2796 {
2797 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2798 if (rinfo->pm_mode != radeon_pm_none)
2799 pmac_set_early_video_resume(NULL, NULL);
2800 #endif
2801 }
linux-next