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PCIE: check and return bus_register errors
[linux-2.6/next.git] / drivers / net / irda / smsc-ircc2.c
blob2eff45bedc7cbc28a0f819fe44e43feece707bfe
1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 * Copyright (c) 2006 Linus Walleij
15 *
16 *
17 * Based on smc-ircc.c:
18 *
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
21 * Copyright (c) 1998-1999 Thomas Davis,
22 *
23 * and irport.c:
24 *
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 *
27 *
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
31 * the License, or (at your option) any later version.
32 *
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 * MA 02111-1307 USA
42 *
43 ********************************************************************/
44
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/skbuff.h>
49 #include <linux/netdevice.h>
50 #include <linux/ioport.h>
51 #include <linux/delay.h>
52 #include <linux/slab.h>
53 #include <linux/init.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/serial_reg.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/pnp.h>
58 #include <linux/platform_device.h>
59
60 #include <asm/io.h>
61 #include <asm/dma.h>
62 #include <asm/byteorder.h>
63
64 #include <linux/spinlock.h>
65 #include <linux/pm.h>
66 #ifdef CONFIG_PCI
67 #include <linux/pci.h>
68 #endif
69
70 #include <net/irda/wrapper.h>
71 #include <net/irda/irda.h>
72 #include <net/irda/irda_device.h>
73
74 #include "smsc-ircc2.h"
75 #include "smsc-sio.h"
76
77
78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80 MODULE_LICENSE("GPL");
81
82 static int ircc_dma = 255;
83 module_param(ircc_dma, int, 0);
84 MODULE_PARM_DESC(ircc_dma, "DMA channel");
85
86 static int ircc_irq = 255;
87 module_param(ircc_irq, int, 0);
88 MODULE_PARM_DESC(ircc_irq, "IRQ line");
89
90 static int ircc_fir;
91 module_param(ircc_fir, int, 0);
92 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
93
94 static int ircc_sir;
95 module_param(ircc_sir, int, 0);
96 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
97
98 static int ircc_cfg;
99 module_param(ircc_cfg, int, 0);
100 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
101
102 static int ircc_transceiver;
103 module_param(ircc_transceiver, int, 0);
104 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
105
106 /* Types */
107
108 #ifdef CONFIG_PCI
109 struct smsc_ircc_subsystem_configuration {
110 unsigned short vendor; /* PCI vendor ID */
111 unsigned short device; /* PCI vendor ID */
112 unsigned short subvendor; /* PCI subsystem vendor ID */
113 unsigned short subdevice; /* PCI sybsystem device ID */
114 unsigned short sir_io; /* I/O port for SIR */
115 unsigned short fir_io; /* I/O port for FIR */
116 unsigned char fir_irq; /* FIR IRQ */
117 unsigned char fir_dma; /* FIR DMA */
118 unsigned short cfg_base; /* I/O port for chip configuration */
119 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
120 const char *name; /* name shown as info */
121 };
122 #endif
123
124 struct smsc_transceiver {
125 char *name;
126 void (*set_for_speed)(int fir_base, u32 speed);
127 int (*probe)(int fir_base);
128 };
129
130 struct smsc_chip {
131 char *name;
132 #if 0
133 u8 type;
134 #endif
135 u16 flags;
136 u8 devid;
137 u8 rev;
138 };
139
140 struct smsc_chip_address {
141 unsigned int cfg_base;
142 unsigned int type;
143 };
144
145 /* Private data for each instance */
146 struct smsc_ircc_cb {
147 struct net_device *netdev; /* Yes! we are some kind of netdevice */
148 struct net_device_stats stats;
149 struct irlap_cb *irlap; /* The link layer we are binded to */
150
151 chipio_t io; /* IrDA controller information */
152 iobuff_t tx_buff; /* Transmit buffer */
153 iobuff_t rx_buff; /* Receive buffer */
154 dma_addr_t tx_buff_dma;
155 dma_addr_t rx_buff_dma;
156
157 struct qos_info qos; /* QoS capabilities for this device */
158
159 spinlock_t lock; /* For serializing operations */
160
161 __u32 new_speed;
162 __u32 flags; /* Interface flags */
163
164 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
165 int tx_len; /* Number of frames in tx_buff */
166
167 int transceiver;
168 struct platform_device *pldev;
169 };
170
171 /* Constants */
172
173 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
174
175 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
176 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
177 #define SMSC_IRCC2_C_NET_TIMEOUT 0
178 #define SMSC_IRCC2_C_SIR_STOP 0
179
180 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
181
182 /* Prototypes */
183
184 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
185 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
186 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
187 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
188 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
189 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
190 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
191 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
192 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
193 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
194 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
195 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
196 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
197 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
198 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
199 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
200 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
201 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
202 #if SMSC_IRCC2_C_SIR_STOP
203 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
204 #endif
205 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
206 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
207 static int smsc_ircc_net_open(struct net_device *dev);
208 static int smsc_ircc_net_close(struct net_device *dev);
209 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
210 #if SMSC_IRCC2_C_NET_TIMEOUT
211 static void smsc_ircc_timeout(struct net_device *dev);
212 #endif
213 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
214 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
215 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
216 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
217 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
218
219 /* Probing */
220 static int __init smsc_ircc_look_for_chips(void);
221 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
222 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
223 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
224 static int __init smsc_superio_fdc(unsigned short cfg_base);
225 static int __init smsc_superio_lpc(unsigned short cfg_base);
226 #ifdef CONFIG_PCI
227 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
228 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
229 static void __init preconfigure_ali_port(struct pci_dev *dev,
230 unsigned short port);
231 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
232 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
233 unsigned short ircc_fir,
234 unsigned short ircc_sir,
235 unsigned char ircc_dma,
236 unsigned char ircc_irq);
237 #endif
238
239 /* Transceivers specific functions */
240
241 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
242 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
243 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
244 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
245 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
246 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
247
248 /* Power Management */
249
250 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
251 static int smsc_ircc_resume(struct platform_device *dev);
252
253 static struct platform_driver smsc_ircc_driver = {
254 .suspend = smsc_ircc_suspend,
255 .resume = smsc_ircc_resume,
256 .driver = {
257 .name = SMSC_IRCC2_DRIVER_NAME,
258 },
259 };
260
261 /* Transceivers for SMSC-ircc */
262
263 static struct smsc_transceiver smsc_transceivers[] =
264 {
265 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
266 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
267 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
268 { NULL, NULL }
269 };
270 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
271
272 /* SMC SuperIO chipsets definitions */
273
274 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
275 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
276 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
277 #define SIR 0 /* SuperIO Chip has only slow IRDA */
278 #define FIR 4 /* SuperIO Chip has fast IRDA */
279 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
280
281 static struct smsc_chip __initdata fdc_chips_flat[] =
282 {
283 /* Base address 0x3f0 or 0x370 */
284 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
285 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
286 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
287 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
288 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
289 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
290 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
291 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
292 { NULL }
293 };
294
295 static struct smsc_chip __initdata fdc_chips_paged[] =
296 {
297 /* Base address 0x3f0 or 0x370 */
298 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
299 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
300 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
301 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
302 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
303 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
304 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
305 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
306 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
308 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
309 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
310 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
311 { NULL }
312 };
313
314 static struct smsc_chip __initdata lpc_chips_flat[] =
315 {
316 /* Base address 0x2E or 0x4E */
317 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
318 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
319 { NULL }
320 };
321
322 static struct smsc_chip __initdata lpc_chips_paged[] =
323 {
324 /* Base address 0x2E or 0x4E */
325 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
326 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
327 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
328 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
329 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
330 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
331 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
332 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
333 { NULL }
334 };
335
336 #define SMSCSIO_TYPE_FDC 1
337 #define SMSCSIO_TYPE_LPC 2
338 #define SMSCSIO_TYPE_FLAT 4
339 #define SMSCSIO_TYPE_PAGED 8
340
341 static struct smsc_chip_address __initdata possible_addresses[] =
342 {
343 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
344 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
345 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
346 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
347 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
348 { 0, 0 }
349 };
350
351 /* Globals */
352
353 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
354 static unsigned short dev_count;
355
356 static inline void register_bank(int iobase, int bank)
357 {
358 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
359 iobase + IRCC_MASTER);
360 }
361
362 #ifdef CONFIG_PNP
363 /* PNP hotplug support */
364 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
365 { .id = "SMCf010", .driver_data = 0 },
366 /* and presumably others */
367 { }
368 };
369 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
370 #endif
371
372
373 /*******************************************************************************
374 *
375 *
376 * SMSC-ircc stuff
377 *
378 *
379 *******************************************************************************/
380
381 /*
382 * Function smsc_ircc_init ()
383 *
384 * Initialize chip. Just try to find out how many chips we are dealing with
385 * and where they are
386 */
387 static int __init smsc_ircc_init(void)
388 {
389 int ret;
390
391 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
392
393 ret = platform_driver_register(&smsc_ircc_driver);
394 if (ret) {
395 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
396 return ret;
397 }
398
399 #ifdef CONFIG_PCI
400 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
401 /* Ignore errors from preconfiguration */
402 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
403 }
404 #endif
405
406 dev_count = 0;
407
408 if (ircc_fir > 0 && ircc_sir > 0) {
409 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
410 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
411
412 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
413 ret = -ENODEV;
414 } else {
415 ret = -ENODEV;
416
417 /* try user provided configuration register base address */
418 if (ircc_cfg > 0) {
419 IRDA_MESSAGE(" Overriding configuration address "
420 "0x%04x\n", ircc_cfg);
421 if (!smsc_superio_fdc(ircc_cfg))
422 ret = 0;
423 if (!smsc_superio_lpc(ircc_cfg))
424 ret = 0;
425 }
426
427 if (smsc_ircc_look_for_chips() > 0)
428 ret = 0;
429 }
430
431 if (ret)
432 platform_driver_unregister(&smsc_ircc_driver);
433
434 return ret;
435 }
436
437 /*
438 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
439 *
440 * Try to open driver instance
441 *
442 */
443 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
444 {
445 struct smsc_ircc_cb *self;
446 struct net_device *dev;
447 int err;
448
449 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
450
451 err = smsc_ircc_present(fir_base, sir_base);
452 if (err)
453 goto err_out;
454
455 err = -ENOMEM;
456 if (dev_count >= ARRAY_SIZE(dev_self)) {
457 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
458 goto err_out1;
459 }
460
461 /*
462 * Allocate new instance of the driver
463 */
464 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
465 if (!dev) {
466 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
467 goto err_out1;
468 }
469
470 SET_MODULE_OWNER(dev);
471
472 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
473 #if SMSC_IRCC2_C_NET_TIMEOUT
474 dev->tx_timeout = smsc_ircc_timeout;
475 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
476 #endif
477 dev->open = smsc_ircc_net_open;
478 dev->stop = smsc_ircc_net_close;
479 dev->do_ioctl = smsc_ircc_net_ioctl;
480 dev->get_stats = smsc_ircc_net_get_stats;
481
482 self = netdev_priv(dev);
483 self->netdev = dev;
484
485 /* Make ifconfig display some details */
486 dev->base_addr = self->io.fir_base = fir_base;
487 dev->irq = self->io.irq = irq;
488
489 /* Need to store self somewhere */
490 dev_self[dev_count] = self;
491 spin_lock_init(&self->lock);
492
493 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
494 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
495
496 self->rx_buff.head =
497 dma_alloc_coherent(NULL, self->rx_buff.truesize,
498 &self->rx_buff_dma, GFP_KERNEL);
499 if (self->rx_buff.head == NULL) {
500 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
501 driver_name);
502 goto err_out2;
503 }
504
505 self->tx_buff.head =
506 dma_alloc_coherent(NULL, self->tx_buff.truesize,
507 &self->tx_buff_dma, GFP_KERNEL);
508 if (self->tx_buff.head == NULL) {
509 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
510 driver_name);
511 goto err_out3;
512 }
513
514 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
515 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
516
517 self->rx_buff.in_frame = FALSE;
518 self->rx_buff.state = OUTSIDE_FRAME;
519 self->tx_buff.data = self->tx_buff.head;
520 self->rx_buff.data = self->rx_buff.head;
521
522 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
523 smsc_ircc_setup_qos(self);
524 smsc_ircc_init_chip(self);
525
526 if (ircc_transceiver > 0 &&
527 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
528 self->transceiver = ircc_transceiver;
529 else
530 smsc_ircc_probe_transceiver(self);
531
532 err = register_netdev(self->netdev);
533 if (err) {
534 IRDA_ERROR("%s, Network device registration failed!\n",
535 driver_name);
536 goto err_out4;
537 }
538
539 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
540 dev_count, NULL, 0);
541 if (IS_ERR(self->pldev)) {
542 err = PTR_ERR(self->pldev);
543 goto err_out5;
544 }
545 platform_set_drvdata(self->pldev, self);
546
547 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
548 dev_count++;
549
550 return 0;
551
552 err_out5:
553 unregister_netdev(self->netdev);
554
555 err_out4:
556 dma_free_coherent(NULL, self->tx_buff.truesize,
557 self->tx_buff.head, self->tx_buff_dma);
558 err_out3:
559 dma_free_coherent(NULL, self->rx_buff.truesize,
560 self->rx_buff.head, self->rx_buff_dma);
561 err_out2:
562 free_netdev(self->netdev);
563 dev_self[dev_count] = NULL;
564 err_out1:
565 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
566 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
567 err_out:
568 return err;
569 }
570
571 /*
572 * Function smsc_ircc_present(fir_base, sir_base)
573 *
574 * Check the smsc-ircc chip presence
575 *
576 */
577 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
578 {
579 unsigned char low, high, chip, config, dma, irq, version;
580
581 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
582 driver_name)) {
583 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
584 __FUNCTION__, fir_base);
585 goto out1;
586 }
587
588 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
589 driver_name)) {
590 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
591 __FUNCTION__, sir_base);
592 goto out2;
593 }
594
595 register_bank(fir_base, 3);
596
597 high = inb(fir_base + IRCC_ID_HIGH);
598 low = inb(fir_base + IRCC_ID_LOW);
599 chip = inb(fir_base + IRCC_CHIP_ID);
600 version = inb(fir_base + IRCC_VERSION);
601 config = inb(fir_base + IRCC_INTERFACE);
602 dma = config & IRCC_INTERFACE_DMA_MASK;
603 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
604
605 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
606 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
607 __FUNCTION__, fir_base);
608 goto out3;
609 }
610 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
611 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
612 chip & 0x0f, version, fir_base, sir_base, dma, irq);
613
614 return 0;
615
616 out3:
617 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
618 out2:
619 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
620 out1:
621 return -ENODEV;
622 }
623
624 /*
625 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
626 *
627 * Setup I/O
628 *
629 */
630 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
631 unsigned int fir_base, unsigned int sir_base,
632 u8 dma, u8 irq)
633 {
634 unsigned char config, chip_dma, chip_irq;
635
636 register_bank(fir_base, 3);
637 config = inb(fir_base + IRCC_INTERFACE);
638 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
639 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
640
641 self->io.fir_base = fir_base;
642 self->io.sir_base = sir_base;
643 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
644 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
645 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
646 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
647
648 if (irq < 255) {
649 if (irq != chip_irq)
650 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
651 driver_name, chip_irq, irq);
652 self->io.irq = irq;
653 } else
654 self->io.irq = chip_irq;
655
656 if (dma < 255) {
657 if (dma != chip_dma)
658 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
659 driver_name, chip_dma, dma);
660 self->io.dma = dma;
661 } else
662 self->io.dma = chip_dma;
663
664 }
665
666 /*
667 * Function smsc_ircc_setup_qos(self)
668 *
669 * Setup qos
670 *
671 */
672 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
673 {
674 /* Initialize QoS for this device */
675 irda_init_max_qos_capabilies(&self->qos);
676
677 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
678 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
679
680 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
681 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
682 irda_qos_bits_to_value(&self->qos);
683 }
684
685 /*
686 * Function smsc_ircc_init_chip(self)
687 *
688 * Init chip
689 *
690 */
691 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
692 {
693 int iobase = self->io.fir_base;
694
695 register_bank(iobase, 0);
696 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
697 outb(0x00, iobase + IRCC_MASTER);
698
699 register_bank(iobase, 1);
700 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
701 iobase + IRCC_SCE_CFGA);
702
703 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
704 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
705 iobase + IRCC_SCE_CFGB);
706 #else
707 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
708 iobase + IRCC_SCE_CFGB);
709 #endif
710 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
711 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
712
713 register_bank(iobase, 4);
714 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
715
716 register_bank(iobase, 0);
717 outb(0, iobase + IRCC_LCR_A);
718
719 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
720
721 /* Power on device */
722 outb(0x00, iobase + IRCC_MASTER);
723 }
724
725 /*
726 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
727 *
728 * Process IOCTL commands for this device
729 *
730 */
731 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
732 {
733 struct if_irda_req *irq = (struct if_irda_req *) rq;
734 struct smsc_ircc_cb *self;
735 unsigned long flags;
736 int ret = 0;
737
738 IRDA_ASSERT(dev != NULL, return -1;);
739
740 self = netdev_priv(dev);
741
742 IRDA_ASSERT(self != NULL, return -1;);
743
744 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
745
746 switch (cmd) {
747 case SIOCSBANDWIDTH: /* Set bandwidth */
748 if (!capable(CAP_NET_ADMIN))
749 ret = -EPERM;
750 else {
751 /* Make sure we are the only one touching
752 * self->io.speed and the hardware - Jean II */
753 spin_lock_irqsave(&self->lock, flags);
754 smsc_ircc_change_speed(self, irq->ifr_baudrate);
755 spin_unlock_irqrestore(&self->lock, flags);
756 }
757 break;
758 case SIOCSMEDIABUSY: /* Set media busy */
759 if (!capable(CAP_NET_ADMIN)) {
760 ret = -EPERM;
761 break;
762 }
763
764 irda_device_set_media_busy(self->netdev, TRUE);
765 break;
766 case SIOCGRECEIVING: /* Check if we are receiving right now */
767 irq->ifr_receiving = smsc_ircc_is_receiving(self);
768 break;
769 #if 0
770 case SIOCSDTRRTS:
771 if (!capable(CAP_NET_ADMIN)) {
772 ret = -EPERM;
773 break;
774 }
775 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
776 break;
777 #endif
778 default:
779 ret = -EOPNOTSUPP;
780 }
781
782 return ret;
783 }
784
785 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
786 {
787 struct smsc_ircc_cb *self = netdev_priv(dev);
788
789 return &self->stats;
790 }
791
792 #if SMSC_IRCC2_C_NET_TIMEOUT
793 /*
794 * Function smsc_ircc_timeout (struct net_device *dev)
795 *
796 * The networking timeout management.
797 *
798 */
799
800 static void smsc_ircc_timeout(struct net_device *dev)
801 {
802 struct smsc_ircc_cb *self = netdev_priv(dev);
803 unsigned long flags;
804
805 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
806 dev->name, self->io.speed);
807 spin_lock_irqsave(&self->lock, flags);
808 smsc_ircc_sir_start(self);
809 smsc_ircc_change_speed(self, self->io.speed);
810 dev->trans_start = jiffies;
811 netif_wake_queue(dev);
812 spin_unlock_irqrestore(&self->lock, flags);
813 }
814 #endif
815
816 /*
817 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
818 *
819 * Transmits the current frame until FIFO is full, then
820 * waits until the next transmit interrupt, and continues until the
821 * frame is transmitted.
822 */
823 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
824 {
825 struct smsc_ircc_cb *self;
826 unsigned long flags;
827 s32 speed;
828
829 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
830
831 IRDA_ASSERT(dev != NULL, return 0;);
832
833 self = netdev_priv(dev);
834 IRDA_ASSERT(self != NULL, return 0;);
835
836 netif_stop_queue(dev);
837
838 /* Make sure test of self->io.speed & speed change are atomic */
839 spin_lock_irqsave(&self->lock, flags);
840
841 /* Check if we need to change the speed */
842 speed = irda_get_next_speed(skb);
843 if (speed != self->io.speed && speed != -1) {
844 /* Check for empty frame */
845 if (!skb->len) {
846 /*
847 * We send frames one by one in SIR mode (no
848 * pipelining), so at this point, if we were sending
849 * a previous frame, we just received the interrupt
850 * telling us it is finished (UART_IIR_THRI).
851 * Therefore, waiting for the transmitter to really
852 * finish draining the fifo won't take too long.
853 * And the interrupt handler is not expected to run.
854 * - Jean II */
855 smsc_ircc_sir_wait_hw_transmitter_finish(self);
856 smsc_ircc_change_speed(self, speed);
857 spin_unlock_irqrestore(&self->lock, flags);
858 dev_kfree_skb(skb);
859 return 0;
860 }
861 self->new_speed = speed;
862 }
863
864 /* Init tx buffer */
865 self->tx_buff.data = self->tx_buff.head;
866
867 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
868 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
869 self->tx_buff.truesize);
870
871 self->stats.tx_bytes += self->tx_buff.len;
872
873 /* Turn on transmit finished interrupt. Will fire immediately! */
874 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
875
876 spin_unlock_irqrestore(&self->lock, flags);
877
878 dev_kfree_skb(skb);
879
880 return 0;
881 }
882
883 /*
884 * Function smsc_ircc_set_fir_speed (self, baud)
885 *
886 * Change the speed of the device
887 *
888 */
889 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
890 {
891 int fir_base, ir_mode, ctrl, fast;
892
893 IRDA_ASSERT(self != NULL, return;);
894 fir_base = self->io.fir_base;
895
896 self->io.speed = speed;
897
898 switch (speed) {
899 default:
900 case 576000:
901 ir_mode = IRCC_CFGA_IRDA_HDLC;
902 ctrl = IRCC_CRC;
903 fast = 0;
904 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
905 break;
906 case 1152000:
907 ir_mode = IRCC_CFGA_IRDA_HDLC;
908 ctrl = IRCC_1152 | IRCC_CRC;
909 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
910 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
911 __FUNCTION__);
912 break;
913 case 4000000:
914 ir_mode = IRCC_CFGA_IRDA_4PPM;
915 ctrl = IRCC_CRC;
916 fast = IRCC_LCR_A_FAST;
917 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
918 __FUNCTION__);
919 break;
920 }
921 #if 0
922 Now in tranceiver!
923 /* This causes an interrupt */
924 register_bank(fir_base, 0);
925 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
926 #endif
927
928 register_bank(fir_base, 1);
929 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
930
931 register_bank(fir_base, 4);
932 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
933 }
934
935 /*
936 * Function smsc_ircc_fir_start(self)
937 *
938 * Change the speed of the device
939 *
940 */
941 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
942 {
943 struct net_device *dev;
944 int fir_base;
945
946 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
947
948 IRDA_ASSERT(self != NULL, return;);
949 dev = self->netdev;
950 IRDA_ASSERT(dev != NULL, return;);
951
952 fir_base = self->io.fir_base;
953
954 /* Reset everything */
955
956 /* Install FIR transmit handler */
957 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
958
959 /* Clear FIFO */
960 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
961
962 /* Enable interrupt */
963 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
964
965 register_bank(fir_base, 1);
966
967 /* Select the TX/RX interface */
968 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
969 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
970 fir_base + IRCC_SCE_CFGB);
971 #else
972 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
973 fir_base + IRCC_SCE_CFGB);
974 #endif
975 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
976
977 /* Enable SCE interrupts */
978 outb(0, fir_base + IRCC_MASTER);
979 register_bank(fir_base, 0);
980 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
981 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
982 }
983
984 /*
985 * Function smsc_ircc_fir_stop(self, baud)
986 *
987 * Change the speed of the device
988 *
989 */
990 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
991 {
992 int fir_base;
993
994 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
995
996 IRDA_ASSERT(self != NULL, return;);
997
998 fir_base = self->io.fir_base;
999 register_bank(fir_base, 0);
1000 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1001 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1002 }
1003
1004
1005 /*
1006 * Function smsc_ircc_change_speed(self, baud)
1007 *
1008 * Change the speed of the device
1009 *
1010 * This function *must* be called with spinlock held, because it may
1011 * be called from the irq handler. - Jean II
1012 */
1013 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1014 {
1015 struct net_device *dev;
1016 int last_speed_was_sir;
1017
1018 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1019
1020 IRDA_ASSERT(self != NULL, return;);
1021 dev = self->netdev;
1022
1023 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1024
1025 #if 0
1026 /* Temp Hack */
1027 speed= 1152000;
1028 self->io.speed = speed;
1029 last_speed_was_sir = 0;
1030 smsc_ircc_fir_start(self);
1031 #endif
1032
1033 if (self->io.speed == 0)
1034 smsc_ircc_sir_start(self);
1035
1036 #if 0
1037 if (!last_speed_was_sir) speed = self->io.speed;
1038 #endif
1039
1040 if (self->io.speed != speed)
1041 smsc_ircc_set_transceiver_for_speed(self, speed);
1042
1043 self->io.speed = speed;
1044
1045 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1046 if (!last_speed_was_sir) {
1047 smsc_ircc_fir_stop(self);
1048 smsc_ircc_sir_start(self);
1049 }
1050 smsc_ircc_set_sir_speed(self, speed);
1051 } else {
1052 if (last_speed_was_sir) {
1053 #if SMSC_IRCC2_C_SIR_STOP
1054 smsc_ircc_sir_stop(self);
1055 #endif
1056 smsc_ircc_fir_start(self);
1057 }
1058 smsc_ircc_set_fir_speed(self, speed);
1059
1060 #if 0
1061 self->tx_buff.len = 10;
1062 self->tx_buff.data = self->tx_buff.head;
1063
1064 smsc_ircc_dma_xmit(self, 4000);
1065 #endif
1066 /* Be ready for incoming frames */
1067 smsc_ircc_dma_receive(self);
1068 }
1069
1070 netif_wake_queue(dev);
1071 }
1072
1073 /*
1074 * Function smsc_ircc_set_sir_speed (self, speed)
1075 *
1076 * Set speed of IrDA port to specified baudrate
1077 *
1078 */
1079 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1080 {
1081 int iobase;
1082 int fcr; /* FIFO control reg */
1083 int lcr; /* Line control reg */
1084 int divisor;
1085
1086 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1087
1088 IRDA_ASSERT(self != NULL, return;);
1089 iobase = self->io.sir_base;
1090
1091 /* Update accounting for new speed */
1092 self->io.speed = speed;
1093
1094 /* Turn off interrupts */
1095 outb(0, iobase + UART_IER);
1096
1097 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1098
1099 fcr = UART_FCR_ENABLE_FIFO;
1100
1101 /*
1102 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1103 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1104 * about this timeout since it will always be fast enough.
1105 */
1106 fcr |= self->io.speed < 38400 ?
1107 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1108
1109 /* IrDA ports use 8N1 */
1110 lcr = UART_LCR_WLEN8;
1111
1112 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1113 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1114 outb(divisor >> 8, iobase + UART_DLM);
1115 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1116 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1117
1118 /* Turn on interrups */
1119 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1120
1121 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1122 }
1123
1124
1125 /*
1126 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1127 *
1128 * Transmit the frame!
1129 *
1130 */
1131 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1132 {
1133 struct smsc_ircc_cb *self;
1134 unsigned long flags;
1135 s32 speed;
1136 int mtt;
1137
1138 IRDA_ASSERT(dev != NULL, return 0;);
1139 self = netdev_priv(dev);
1140 IRDA_ASSERT(self != NULL, return 0;);
1141
1142 netif_stop_queue(dev);
1143
1144 /* Make sure test of self->io.speed & speed change are atomic */
1145 spin_lock_irqsave(&self->lock, flags);
1146
1147 /* Check if we need to change the speed after this frame */
1148 speed = irda_get_next_speed(skb);
1149 if (speed != self->io.speed && speed != -1) {
1150 /* Check for empty frame */
1151 if (!skb->len) {
1152 /* Note : you should make sure that speed changes
1153 * are not going to corrupt any outgoing frame.
1154 * Look at nsc-ircc for the gory details - Jean II */
1155 smsc_ircc_change_speed(self, speed);
1156 spin_unlock_irqrestore(&self->lock, flags);
1157 dev_kfree_skb(skb);
1158 return 0;
1159 }
1160
1161 self->new_speed = speed;
1162 }
1163
1164 memcpy(self->tx_buff.head, skb->data, skb->len);
1165
1166 self->tx_buff.len = skb->len;
1167 self->tx_buff.data = self->tx_buff.head;
1168
1169 mtt = irda_get_mtt(skb);
1170 if (mtt) {
1171 int bofs;
1172
1173 /*
1174 * Compute how many BOFs (STA or PA's) we need to waste the
1175 * min turn time given the speed of the link.
1176 */
1177 bofs = mtt * (self->io.speed / 1000) / 8000;
1178 if (bofs > 4095)
1179 bofs = 4095;
1180
1181 smsc_ircc_dma_xmit(self, bofs);
1182 } else {
1183 /* Transmit frame */
1184 smsc_ircc_dma_xmit(self, 0);
1185 }
1186
1187 spin_unlock_irqrestore(&self->lock, flags);
1188 dev_kfree_skb(skb);
1189
1190 return 0;
1191 }
1192
1193 /*
1194 * Function smsc_ircc_dma_xmit (self, bofs)
1195 *
1196 * Transmit data using DMA
1197 *
1198 */
1199 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1200 {
1201 int iobase = self->io.fir_base;
1202 u8 ctrl;
1203
1204 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1205 #if 1
1206 /* Disable Rx */
1207 register_bank(iobase, 0);
1208 outb(0x00, iobase + IRCC_LCR_B);
1209 #endif
1210 register_bank(iobase, 1);
1211 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1212 iobase + IRCC_SCE_CFGB);
1213
1214 self->io.direction = IO_XMIT;
1215
1216 /* Set BOF additional count for generating the min turn time */
1217 register_bank(iobase, 4);
1218 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1219 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1220 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1221
1222 /* Set max Tx frame size */
1223 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1224 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1225
1226 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1227
1228 /* Enable burst mode chip Tx DMA */
1229 register_bank(iobase, 1);
1230 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1231 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1232
1233 /* Setup DMA controller (must be done after enabling chip DMA) */
1234 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1235 DMA_TX_MODE);
1236
1237 /* Enable interrupt */
1238
1239 register_bank(iobase, 0);
1240 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1241 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1242
1243 /* Enable transmit */
1244 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1245 }
1246
1247 /*
1248 * Function smsc_ircc_dma_xmit_complete (self)
1249 *
1250 * The transfer of a frame in finished. This function will only be called
1251 * by the interrupt handler
1252 *
1253 */
1254 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1255 {
1256 int iobase = self->io.fir_base;
1257
1258 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1259 #if 0
1260 /* Disable Tx */
1261 register_bank(iobase, 0);
1262 outb(0x00, iobase + IRCC_LCR_B);
1263 #endif
1264 register_bank(iobase, 1);
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1266 iobase + IRCC_SCE_CFGB);
1267
1268 /* Check for underrun! */
1269 register_bank(iobase, 0);
1270 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1271 self->stats.tx_errors++;
1272 self->stats.tx_fifo_errors++;
1273
1274 /* Reset error condition */
1275 register_bank(iobase, 0);
1276 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1277 outb(0x00, iobase + IRCC_MASTER);
1278 } else {
1279 self->stats.tx_packets++;
1280 self->stats.tx_bytes += self->tx_buff.len;
1281 }
1282
1283 /* Check if it's time to change the speed */
1284 if (self->new_speed) {
1285 smsc_ircc_change_speed(self, self->new_speed);
1286 self->new_speed = 0;
1287 }
1288
1289 netif_wake_queue(self->netdev);
1290 }
1291
1292 /*
1293 * Function smsc_ircc_dma_receive(self)
1294 *
1295 * Get ready for receiving a frame. The device will initiate a DMA
1296 * if it starts to receive a frame.
1297 *
1298 */
1299 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1300 {
1301 int iobase = self->io.fir_base;
1302 #if 0
1303 /* Turn off chip DMA */
1304 register_bank(iobase, 1);
1305 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1306 iobase + IRCC_SCE_CFGB);
1307 #endif
1308
1309 /* Disable Tx */
1310 register_bank(iobase, 0);
1311 outb(0x00, iobase + IRCC_LCR_B);
1312
1313 /* Turn off chip DMA */
1314 register_bank(iobase, 1);
1315 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1316 iobase + IRCC_SCE_CFGB);
1317
1318 self->io.direction = IO_RECV;
1319 self->rx_buff.data = self->rx_buff.head;
1320
1321 /* Set max Rx frame size */
1322 register_bank(iobase, 4);
1323 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1324 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1325
1326 /* Setup DMA controller */
1327 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1328 DMA_RX_MODE);
1329
1330 /* Enable burst mode chip Rx DMA */
1331 register_bank(iobase, 1);
1332 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1333 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1334
1335 /* Enable interrupt */
1336 register_bank(iobase, 0);
1337 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1338 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1339
1340 /* Enable receiver */
1341 register_bank(iobase, 0);
1342 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1343 iobase + IRCC_LCR_B);
1344
1345 return 0;
1346 }
1347
1348 /*
1349 * Function smsc_ircc_dma_receive_complete(self)
1350 *
1351 * Finished with receiving frames
1352 *
1353 */
1354 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1355 {
1356 struct sk_buff *skb;
1357 int len, msgcnt, lsr;
1358 int iobase = self->io.fir_base;
1359
1360 register_bank(iobase, 0);
1361
1362 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1363 #if 0
1364 /* Disable Rx */
1365 register_bank(iobase, 0);
1366 outb(0x00, iobase + IRCC_LCR_B);
1367 #endif
1368 register_bank(iobase, 0);
1369 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1370 lsr= inb(iobase + IRCC_LSR);
1371 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1372
1373 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1374 get_dma_residue(self->io.dma));
1375
1376 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1377
1378 /* Look for errors */
1379 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1380 self->stats.rx_errors++;
1381 if (lsr & IRCC_LSR_FRAME_ERROR)
1382 self->stats.rx_frame_errors++;
1383 if (lsr & IRCC_LSR_CRC_ERROR)
1384 self->stats.rx_crc_errors++;
1385 if (lsr & IRCC_LSR_SIZE_ERROR)
1386 self->stats.rx_length_errors++;
1387 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1388 self->stats.rx_length_errors++;
1389 return;
1390 }
1391
1392 /* Remove CRC */
1393 len -= self->io.speed < 4000000 ? 2 : 4;
1394
1395 if (len < 2 || len > 2050) {
1396 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1397 return;
1398 }
1399 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1400
1401 skb = dev_alloc_skb(len + 1);
1402 if (!skb) {
1403 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1404 __FUNCTION__);
1405 return;
1406 }
1407 /* Make sure IP header gets aligned */
1408 skb_reserve(skb, 1);
1409
1410 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1411 self->stats.rx_packets++;
1412 self->stats.rx_bytes += len;
1413
1414 skb->dev = self->netdev;
1415 skb->mac.raw = skb->data;
1416 skb->protocol = htons(ETH_P_IRDA);
1417 netif_rx(skb);
1418 }
1419
1420 /*
1421 * Function smsc_ircc_sir_receive (self)
1422 *
1423 * Receive one frame from the infrared port
1424 *
1425 */
1426 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1427 {
1428 int boguscount = 0;
1429 int iobase;
1430
1431 IRDA_ASSERT(self != NULL, return;);
1432
1433 iobase = self->io.sir_base;
1434
1435 /*
1436 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1437 * async_unwrap_char will deliver all found frames
1438 */
1439 do {
1440 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1441 inb(iobase + UART_RX));
1442
1443 /* Make sure we don't stay here to long */
1444 if (boguscount++ > 32) {
1445 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1446 break;
1447 }
1448 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1449 }
1450
1451
1452 /*
1453 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1454 *
1455 * An interrupt from the chip has arrived. Time to do some work
1456 *
1457 */
1458 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1459 {
1460 struct net_device *dev = (struct net_device *) dev_id;
1461 struct smsc_ircc_cb *self;
1462 int iobase, iir, lcra, lsr;
1463 irqreturn_t ret = IRQ_NONE;
1464
1465 if (dev == NULL) {
1466 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1467 driver_name, irq);
1468 goto irq_ret;
1469 }
1470
1471 self = netdev_priv(dev);
1472 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1473
1474 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1475 spin_lock(&self->lock);
1476
1477 /* Check if we should use the SIR interrupt handler */
1478 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1479 ret = smsc_ircc_interrupt_sir(dev);
1480 goto irq_ret_unlock;
1481 }
1482
1483 iobase = self->io.fir_base;
1484
1485 register_bank(iobase, 0);
1486 iir = inb(iobase + IRCC_IIR);
1487 if (iir == 0)
1488 goto irq_ret_unlock;
1489 ret = IRQ_HANDLED;
1490
1491 /* Disable interrupts */
1492 outb(0, iobase + IRCC_IER);
1493 lcra = inb(iobase + IRCC_LCR_A);
1494 lsr = inb(iobase + IRCC_LSR);
1495
1496 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1497
1498 if (iir & IRCC_IIR_EOM) {
1499 if (self->io.direction == IO_RECV)
1500 smsc_ircc_dma_receive_complete(self);
1501 else
1502 smsc_ircc_dma_xmit_complete(self);
1503
1504 smsc_ircc_dma_receive(self);
1505 }
1506
1507 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1508 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1509 }
1510
1511 /* Enable interrupts again */
1512
1513 register_bank(iobase, 0);
1514 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1515
1516 irq_ret_unlock:
1517 spin_unlock(&self->lock);
1518 irq_ret:
1519 return ret;
1520 }
1521
1522 /*
1523 * Function irport_interrupt_sir (irq, dev_id, regs)
1524 *
1525 * Interrupt handler for SIR modes
1526 */
1527 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1528 {
1529 struct smsc_ircc_cb *self = netdev_priv(dev);
1530 int boguscount = 0;
1531 int iobase;
1532 int iir, lsr;
1533
1534 /* Already locked comming here in smsc_ircc_interrupt() */
1535 /*spin_lock(&self->lock);*/
1536
1537 iobase = self->io.sir_base;
1538
1539 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1540 if (iir == 0)
1541 return IRQ_NONE;
1542 while (iir) {
1543 /* Clear interrupt */
1544 lsr = inb(iobase + UART_LSR);
1545
1546 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1547 __FUNCTION__, iir, lsr, iobase);
1548
1549 switch (iir) {
1550 case UART_IIR_RLSI:
1551 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1552 break;
1553 case UART_IIR_RDI:
1554 /* Receive interrupt */
1555 smsc_ircc_sir_receive(self);
1556 break;
1557 case UART_IIR_THRI:
1558 if (lsr & UART_LSR_THRE)
1559 /* Transmitter ready for data */
1560 smsc_ircc_sir_write_wakeup(self);
1561 break;
1562 default:
1563 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1564 __FUNCTION__, iir);
1565 break;
1566 }
1567
1568 /* Make sure we don't stay here to long */
1569 if (boguscount++ > 100)
1570 break;
1571
1572 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1573 }
1574 /*spin_unlock(&self->lock);*/
1575 return IRQ_HANDLED;
1576 }
1577
1578
1579 #if 0 /* unused */
1580 /*
1581 * Function ircc_is_receiving (self)
1582 *
1583 * Return TRUE is we are currently receiving a frame
1584 *
1585 */
1586 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1587 {
1588 int status = FALSE;
1589 /* int iobase; */
1590
1591 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1592
1593 IRDA_ASSERT(self != NULL, return FALSE;);
1594
1595 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1596 get_dma_residue(self->io.dma));
1597
1598 status = (self->rx_buff.state != OUTSIDE_FRAME);
1599
1600 return status;
1601 }
1602 #endif /* unused */
1603
1604 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1605 {
1606 int error;
1607
1608 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1609 self->netdev->name, self->netdev);
1610 if (error)
1611 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1612 __FUNCTION__, self->io.irq, error);
1613
1614 return error;
1615 }
1616
1617 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1618 {
1619 unsigned long flags;
1620
1621 spin_lock_irqsave(&self->lock, flags);
1622
1623 self->io.speed = 0;
1624 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1625
1626 spin_unlock_irqrestore(&self->lock, flags);
1627 }
1628
1629 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1630 {
1631 int iobase = self->io.fir_base;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&self->lock, flags);
1635
1636 register_bank(iobase, 0);
1637 outb(0, iobase + IRCC_IER);
1638 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1639 outb(0x00, iobase + IRCC_MASTER);
1640
1641 spin_unlock_irqrestore(&self->lock, flags);
1642 }
1643
1644
1645 /*
1646 * Function smsc_ircc_net_open (dev)
1647 *
1648 * Start the device
1649 *
1650 */
1651 static int smsc_ircc_net_open(struct net_device *dev)
1652 {
1653 struct smsc_ircc_cb *self;
1654 char hwname[16];
1655
1656 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1657
1658 IRDA_ASSERT(dev != NULL, return -1;);
1659 self = netdev_priv(dev);
1660 IRDA_ASSERT(self != NULL, return 0;);
1661
1662 if (self->io.suspended) {
1663 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1664 return -EAGAIN;
1665 }
1666
1667 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1668 (void *) dev)) {
1669 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1670 __FUNCTION__, self->io.irq);
1671 return -EAGAIN;
1672 }
1673
1674 smsc_ircc_start_interrupts(self);
1675
1676 /* Give self a hardware name */
1677 /* It would be cool to offer the chip revision here - Jean II */
1678 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1679
1680 /*
1681 * Open new IrLAP layer instance, now that everything should be
1682 * initialized properly
1683 */
1684 self->irlap = irlap_open(dev, &self->qos, hwname);
1685
1686 /*
1687 * Always allocate the DMA channel after the IRQ,
1688 * and clean up on failure.
1689 */
1690 if (request_dma(self->io.dma, dev->name)) {
1691 smsc_ircc_net_close(dev);
1692
1693 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1694 __FUNCTION__, self->io.dma);
1695 return -EAGAIN;
1696 }
1697
1698 netif_start_queue(dev);
1699
1700 return 0;
1701 }
1702
1703 /*
1704 * Function smsc_ircc_net_close (dev)
1705 *
1706 * Stop the device
1707 *
1708 */
1709 static int smsc_ircc_net_close(struct net_device *dev)
1710 {
1711 struct smsc_ircc_cb *self;
1712
1713 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1714
1715 IRDA_ASSERT(dev != NULL, return -1;);
1716 self = netdev_priv(dev);
1717 IRDA_ASSERT(self != NULL, return 0;);
1718
1719 /* Stop device */
1720 netif_stop_queue(dev);
1721
1722 /* Stop and remove instance of IrLAP */
1723 if (self->irlap)
1724 irlap_close(self->irlap);
1725 self->irlap = NULL;
1726
1727 smsc_ircc_stop_interrupts(self);
1728
1729 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1730 if (!self->io.suspended)
1731 free_irq(self->io.irq, dev);
1732
1733 disable_dma(self->io.dma);
1734 free_dma(self->io.dma);
1735
1736 return 0;
1737 }
1738
1739 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1740 {
1741 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1742
1743 if (!self->io.suspended) {
1744 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1745
1746 rtnl_lock();
1747 if (netif_running(self->netdev)) {
1748 netif_device_detach(self->netdev);
1749 smsc_ircc_stop_interrupts(self);
1750 free_irq(self->io.irq, self->netdev);
1751 disable_dma(self->io.dma);
1752 }
1753 self->io.suspended = 1;
1754 rtnl_unlock();
1755 }
1756
1757 return 0;
1758 }
1759
1760 static int smsc_ircc_resume(struct platform_device *dev)
1761 {
1762 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1763
1764 if (self->io.suspended) {
1765 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1766
1767 rtnl_lock();
1768 smsc_ircc_init_chip(self);
1769 if (netif_running(self->netdev)) {
1770 if (smsc_ircc_request_irq(self)) {
1771 /*
1772 * Don't fail resume process, just kill this
1773 * network interface
1774 */
1775 unregister_netdevice(self->netdev);
1776 } else {
1777 enable_dma(self->io.dma);
1778 smsc_ircc_start_interrupts(self);
1779 netif_device_attach(self->netdev);
1780 }
1781 }
1782 self->io.suspended = 0;
1783 rtnl_unlock();
1784 }
1785 return 0;
1786 }
1787
1788 /*
1789 * Function smsc_ircc_close (self)
1790 *
1791 * Close driver instance
1792 *
1793 */
1794 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1795 {
1796 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1797
1798 IRDA_ASSERT(self != NULL, return -1;);
1799
1800 platform_device_unregister(self->pldev);
1801
1802 /* Remove netdevice */
1803 unregister_netdev(self->netdev);
1804
1805 smsc_ircc_stop_interrupts(self);
1806
1807 /* Release the PORTS that this driver is using */
1808 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1809 self->io.fir_base);
1810
1811 release_region(self->io.fir_base, self->io.fir_ext);
1812
1813 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1814 self->io.sir_base);
1815
1816 release_region(self->io.sir_base, self->io.sir_ext);
1817
1818 if (self->tx_buff.head)
1819 dma_free_coherent(NULL, self->tx_buff.truesize,
1820 self->tx_buff.head, self->tx_buff_dma);
1821
1822 if (self->rx_buff.head)
1823 dma_free_coherent(NULL, self->rx_buff.truesize,
1824 self->rx_buff.head, self->rx_buff_dma);
1825
1826 free_netdev(self->netdev);
1827
1828 return 0;
1829 }
1830
1831 static void __exit smsc_ircc_cleanup(void)
1832 {
1833 int i;
1834
1835 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1836
1837 for (i = 0; i < 2; i++) {
1838 if (dev_self[i])
1839 smsc_ircc_close(dev_self[i]);
1840 }
1841
1842 platform_driver_unregister(&smsc_ircc_driver);
1843 }
1844
1845 /*
1846 * Start SIR operations
1847 *
1848 * This function *must* be called with spinlock held, because it may
1849 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1850 */
1851 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1852 {
1853 struct net_device *dev;
1854 int fir_base, sir_base;
1855
1856 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1857
1858 IRDA_ASSERT(self != NULL, return;);
1859 dev = self->netdev;
1860 IRDA_ASSERT(dev != NULL, return;);
1861 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1862
1863 fir_base = self->io.fir_base;
1864 sir_base = self->io.sir_base;
1865
1866 /* Reset everything */
1867 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1868
1869 #if SMSC_IRCC2_C_SIR_STOP
1870 /*smsc_ircc_sir_stop(self);*/
1871 #endif
1872
1873 register_bank(fir_base, 1);
1874 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1875
1876 /* Initialize UART */
1877 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1878 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1879
1880 /* Turn on interrups */
1881 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1882
1883 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1884
1885 outb(0x00, fir_base + IRCC_MASTER);
1886 }
1887
1888 #if SMSC_IRCC2_C_SIR_STOP
1889 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1890 {
1891 int iobase;
1892
1893 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1894 iobase = self->io.sir_base;
1895
1896 /* Reset UART */
1897 outb(0, iobase + UART_MCR);
1898
1899 /* Turn off interrupts */
1900 outb(0, iobase + UART_IER);
1901 }
1902 #endif
1903
1904 /*
1905 * Function smsc_sir_write_wakeup (self)
1906 *
1907 * Called by the SIR interrupt handler when there's room for more data.
1908 * If we have more packets to send, we send them here.
1909 *
1910 */
1911 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1912 {
1913 int actual = 0;
1914 int iobase;
1915 int fcr;
1916
1917 IRDA_ASSERT(self != NULL, return;);
1918
1919 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1920
1921 iobase = self->io.sir_base;
1922
1923 /* Finished with frame? */
1924 if (self->tx_buff.len > 0) {
1925 /* Write data left in transmit buffer */
1926 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1927 self->tx_buff.data, self->tx_buff.len);
1928 self->tx_buff.data += actual;
1929 self->tx_buff.len -= actual;
1930 } else {
1931
1932 /*if (self->tx_buff.len ==0) {*/
1933
1934 /*
1935 * Now serial buffer is almost free & we can start
1936 * transmission of another packet. But first we must check
1937 * if we need to change the speed of the hardware
1938 */
1939 if (self->new_speed) {
1940 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1941 __FUNCTION__, self->new_speed);
1942 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1943 smsc_ircc_change_speed(self, self->new_speed);
1944 self->new_speed = 0;
1945 } else {
1946 /* Tell network layer that we want more frames */
1947 netif_wake_queue(self->netdev);
1948 }
1949 self->stats.tx_packets++;
1950
1951 if (self->io.speed <= 115200) {
1952 /*
1953 * Reset Rx FIFO to make sure that all reflected transmit data
1954 * is discarded. This is needed for half duplex operation
1955 */
1956 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1957 fcr |= self->io.speed < 38400 ?
1958 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1959
1960 outb(fcr, iobase + UART_FCR);
1961
1962 /* Turn on receive interrupts */
1963 outb(UART_IER_RDI, iobase + UART_IER);
1964 }
1965 }
1966 }
1967
1968 /*
1969 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1970 *
1971 * Fill Tx FIFO with transmit data
1972 *
1973 */
1974 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1975 {
1976 int actual = 0;
1977
1978 /* Tx FIFO should be empty! */
1979 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1980 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1981 return 0;
1982 }
1983
1984 /* Fill FIFO with current frame */
1985 while (fifo_size-- > 0 && actual < len) {
1986 /* Transmit next byte */
1987 outb(buf[actual], iobase + UART_TX);
1988 actual++;
1989 }
1990 return actual;
1991 }
1992
1993 /*
1994 * Function smsc_ircc_is_receiving (self)
1995 *
1996 * Returns true is we are currently receiving data
1997 *
1998 */
1999 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2000 {
2001 return (self->rx_buff.state != OUTSIDE_FRAME);
2002 }
2003
2004
2005 /*
2006 * Function smsc_ircc_probe_transceiver(self)
2007 *
2008 * Tries to find the used Transceiver
2009 *
2010 */
2011 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2012 {
2013 unsigned int i;
2014
2015 IRDA_ASSERT(self != NULL, return;);
2016
2017 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2018 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2019 IRDA_MESSAGE(" %s transceiver found\n",
2020 smsc_transceivers[i].name);
2021 self->transceiver= i + 1;
2022 return;
2023 }
2024
2025 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2026 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2027
2028 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2029 }
2030
2031
2032 /*
2033 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2034 *
2035 * Set the transceiver according to the speed
2036 *
2037 */
2038 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2039 {
2040 unsigned int trx;
2041
2042 trx = self->transceiver;
2043 if (trx > 0)
2044 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2045 }
2046
2047 /*
2048 * Function smsc_ircc_wait_hw_transmitter_finish ()
2049 *
2050 * Wait for the real end of HW transmission
2051 *
2052 * The UART is a strict FIFO, and we get called only when we have finished
2053 * pushing data to the FIFO, so the maximum amount of time we must wait
2054 * is only for the FIFO to drain out.
2055 *
2056 * We use a simple calibrated loop. We may need to adjust the loop
2057 * delay (udelay) to balance I/O traffic and latency. And we also need to
2058 * adjust the maximum timeout.
2059 * It would probably be better to wait for the proper interrupt,
2060 * but it doesn't seem to be available.
2061 *
2062 * We can't use jiffies or kernel timers because :
2063 * 1) We are called from the interrupt handler, which disable softirqs,
2064 * so jiffies won't be increased
2065 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2066 * want to wait that long to detect stuck hardware.
2067 * Jean II
2068 */
2069
2070 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2071 {
2072 int iobase = self->io.sir_base;
2073 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2074
2075 /* Calibrated busy loop */
2076 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2077 udelay(1);
2078
2079 if (count == 0)
2080 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2081 }
2082
2083
2084 /* PROBING
2085 *
2086 * REVISIT we can be told about the device by PNP, and should use that info
2087 * instead of probing hardware and creating a platform_device ...
2088 */
2089
2090 static int __init smsc_ircc_look_for_chips(void)
2091 {
2092 struct smsc_chip_address *address;
2093 char *type;
2094 unsigned int cfg_base, found;
2095
2096 found = 0;
2097 address = possible_addresses;
2098
2099 while (address->cfg_base) {
2100 cfg_base = address->cfg_base;
2101
2102 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2103
2104 if (address->type & SMSCSIO_TYPE_FDC) {
2105 type = "FDC";
2106 if (address->type & SMSCSIO_TYPE_FLAT)
2107 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2108 found++;
2109
2110 if (address->type & SMSCSIO_TYPE_PAGED)
2111 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2112 found++;
2113 }
2114 if (address->type & SMSCSIO_TYPE_LPC) {
2115 type = "LPC";
2116 if (address->type & SMSCSIO_TYPE_FLAT)
2117 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2118 found++;
2119
2120 if (address->type & SMSCSIO_TYPE_PAGED)
2121 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2122 found++;
2123 }
2124 address++;
2125 }
2126 return found;
2127 }
2128
2129 /*
2130 * Function smsc_superio_flat (chip, base, type)
2131 *
2132 * Try to get configuration of a smc SuperIO chip with flat register model
2133 *
2134 */
2135 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2136 {
2137 unsigned short firbase, sirbase;
2138 u8 mode, dma, irq;
2139 int ret = -ENODEV;
2140
2141 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2142
2143 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2144 return ret;
2145
2146 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2147 mode = inb(cfgbase + 1);
2148
2149 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2150
2151 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2152 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2153
2154 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2155 sirbase = inb(cfgbase + 1) << 2;
2156
2157 /* FIR iobase */
2158 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2159 firbase = inb(cfgbase + 1) << 3;
2160
2161 /* DMA */
2162 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2163 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2164
2165 /* IRQ */
2166 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2167 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2168
2169 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2170
2171 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2172 ret = 0;
2173
2174 /* Exit configuration */
2175 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2176
2177 return ret;
2178 }
2179
2180 /*
2181 * Function smsc_superio_paged (chip, base, type)
2182 *
2183 * Try to get configuration of a smc SuperIO chip with paged register model
2184 *
2185 */
2186 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2187 {
2188 unsigned short fir_io, sir_io;
2189 int ret = -ENODEV;
2190
2191 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2192
2193 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2194 return ret;
2195
2196 /* Select logical device (UART2) */
2197 outb(0x07, cfg_base);
2198 outb(0x05, cfg_base + 1);
2199
2200 /* SIR iobase */
2201 outb(0x60, cfg_base);
2202 sir_io = inb(cfg_base + 1) << 8;
2203 outb(0x61, cfg_base);
2204 sir_io |= inb(cfg_base + 1);
2205
2206 /* Read FIR base */
2207 outb(0x62, cfg_base);
2208 fir_io = inb(cfg_base + 1) << 8;
2209 outb(0x63, cfg_base);
2210 fir_io |= inb(cfg_base + 1);
2211 outb(0x2b, cfg_base); /* ??? */
2212
2213 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2214 ret = 0;
2215
2216 /* Exit configuration */
2217 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2218
2219 return ret;
2220 }
2221
2222
2223 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2224 {
2225 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2226
2227 outb(reg, cfg_base);
2228 return inb(cfg_base) != reg ? -1 : 0;
2229 }
2230
2231 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2232 {
2233 u8 devid, xdevid, rev;
2234
2235 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2236
2237 /* Leave configuration */
2238
2239 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2240
2241 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2242 return NULL;
2243
2244 outb(reg, cfg_base);
2245
2246 xdevid = inb(cfg_base + 1);
2247
2248 /* Enter configuration */
2249
2250 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2251
2252 #if 0
2253 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2254 return NULL;
2255 #endif
2256
2257 /* probe device ID */
2258
2259 if (smsc_access(cfg_base, reg))
2260 return NULL;
2261
2262 devid = inb(cfg_base + 1);
2263
2264 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2265 return NULL;
2266
2267 /* probe revision ID */
2268
2269 if (smsc_access(cfg_base, reg + 1))
2270 return NULL;
2271
2272 rev = inb(cfg_base + 1);
2273
2274 if (rev >= 128) /* i think this will make no sense */
2275 return NULL;
2276
2277 if (devid == xdevid) /* protection against false positives */
2278 return NULL;
2279
2280 /* Check for expected device ID; are there others? */
2281
2282 while (chip->devid != devid) {
2283
2284 chip++;
2285
2286 if (chip->name == NULL)
2287 return NULL;
2288 }
2289
2290 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2291 devid, rev, cfg_base, type, chip->name);
2292
2293 if (chip->rev > rev) {
2294 IRDA_MESSAGE("Revision higher than expected\n");
2295 return NULL;
2296 }
2297
2298 if (chip->flags & NoIRDA)
2299 IRDA_MESSAGE("chipset does not support IRDA\n");
2300
2301 return chip;
2302 }
2303
2304 static int __init smsc_superio_fdc(unsigned short cfg_base)
2305 {
2306 int ret = -1;
2307
2308 if (!request_region(cfg_base, 2, driver_name)) {
2309 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2310 __FUNCTION__, cfg_base);
2311 } else {
2312 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2313 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2314 ret = 0;
2315
2316 release_region(cfg_base, 2);
2317 }
2318
2319 return ret;
2320 }
2321
2322 static int __init smsc_superio_lpc(unsigned short cfg_base)
2323 {
2324 int ret = -1;
2325
2326 if (!request_region(cfg_base, 2, driver_name)) {
2327 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2328 __FUNCTION__, cfg_base);
2329 } else {
2330 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2331 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2332 ret = 0;
2333
2334 release_region(cfg_base, 2);
2335 }
2336 return ret;
2337 }
2338
2339 /*
2340 * Look for some specific subsystem setups that need
2341 * pre-configuration not properly done by the BIOS (especially laptops)
2342 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2343 * and tosh2450-smcinit.c. The table lists the device entries
2344 * for ISA bridges with an LPC (Low Pin Count) controller which
2345 * handles the communication with the SMSC device. After the LPC
2346 * controller is initialized through PCI, the SMSC device is initialized
2347 * through a dedicated port in the ISA port-mapped I/O area, this latter
2348 * area is used to configure the SMSC device with default
2349 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2350 * used different sets of parameters and different control port
2351 * addresses making a subsystem device table necessary.
2352 */
2353 #ifdef CONFIG_PCI
2354 #define PCIID_VENDOR_INTEL 0x8086
2355 #define PCIID_VENDOR_ALI 0x10b9
2356 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2357 {
2358 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2359 .device = 0x24cc,
2360 .subvendor = 0x103c,
2361 .subdevice = 0x088c,
2362 /* Quite certain these are the same for nc8000 as for nc6000 */
2363 .sir_io = 0x02f8,
2364 .fir_io = 0x0130,
2365 .fir_irq = 0x05,
2366 .fir_dma = 0x03,
2367 .cfg_base = 0x004e,
2368 .preconfigure = preconfigure_through_82801,
2369 .name = "HP nc8000",
2370 },
2371 {
2372 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2373 .device = 0x24cc,
2374 .subvendor = 0x103c,
2375 .subdevice = 0x0890,
2376 .sir_io = 0x02f8,
2377 .fir_io = 0x0130,
2378 .fir_irq = 0x05,
2379 .fir_dma = 0x03,
2380 .cfg_base = 0x004e,
2381 .preconfigure = preconfigure_through_82801,
2382 .name = "HP nc6000",
2383 },
2384 {
2385 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2386 .vendor = PCIID_VENDOR_INTEL,
2387 .device = 0x24c0,
2388 .subvendor = 0x1179,
2389 .subdevice = 0xffff, /* 0xffff is "any" */
2390 .sir_io = 0x03f8,
2391 .fir_io = 0x0130,
2392 .fir_irq = 0x07,
2393 .fir_dma = 0x01,
2394 .cfg_base = 0x002e,
2395 .preconfigure = preconfigure_through_82801,
2396 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2397 },
2398 {
2399 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2400 .device = 0x248c,
2401 .subvendor = 0x1179,
2402 .subdevice = 0xffff, /* 0xffff is "any" */
2403 .sir_io = 0x03f8,
2404 .fir_io = 0x0130,
2405 .fir_irq = 0x03,
2406 .fir_dma = 0x03,
2407 .cfg_base = 0x002e,
2408 .preconfigure = preconfigure_through_82801,
2409 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2410 },
2411 {
2412 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2413 .vendor = PCIID_VENDOR_INTEL,
2414 .device = 0x24cc,
2415 .subvendor = 0x1179,
2416 .subdevice = 0xffff, /* 0xffff is "any" */
2417 .sir_io = 0x03f8,
2418 .fir_io = 0x0130,
2419 .fir_irq = 0x03,
2420 .fir_dma = 0x03,
2421 .cfg_base = 0x002e,
2422 .preconfigure = preconfigure_through_82801,
2423 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2424 },
2425 {
2426 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2427 .vendor = PCIID_VENDOR_ALI,
2428 .device = 0x1533,
2429 .subvendor = 0x1179,
2430 .subdevice = 0xffff, /* 0xffff is "any" */
2431 .sir_io = 0x02e8,
2432 .fir_io = 0x02f8,
2433 .fir_irq = 0x07,
2434 .fir_dma = 0x03,
2435 .cfg_base = 0x002e,
2436 .preconfigure = preconfigure_through_ali,
2437 .name = "Toshiba laptop with ALi ISA bridge",
2438 },
2439 { } // Terminator
2440 };
2441
2442
2443 /*
2444 * This sets up the basic SMSC parameters
2445 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2446 * through the chip configuration port.
2447 */
2448 static int __init preconfigure_smsc_chip(struct
2449 smsc_ircc_subsystem_configuration
2450 *conf)
2451 {
2452 unsigned short iobase = conf->cfg_base;
2453 unsigned char tmpbyte;
2454
2455 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2456 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2457 tmpbyte = inb(iobase +1); // Read device ID
2458 IRDA_DEBUG(0,
2459 "Detected Chip id: 0x%02x, setting up registers...\n",
2460 tmpbyte);
2461
2462 /* Disable UART1 and set up SIR I/O port */
2463 outb(0x24, iobase); // select CR24 - UART1 base addr
2464 outb(0x00, iobase + 1); // disable UART1
2465 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2466 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2467 tmpbyte = inb(iobase + 1);
2468 if (tmpbyte != (conf->sir_io >> 2) ) {
2469 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2470 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2471 return -ENXIO;
2472 }
2473
2474 /* Set up FIR IRQ channel for UART2 */
2475 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2476 tmpbyte = inb(iobase + 1);
2477 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2478 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2479 outb(tmpbyte, iobase + 1);
2480 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2481 if (tmpbyte != conf->fir_irq) {
2482 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2483 return -ENXIO;
2484 }
2485
2486 /* Set up FIR I/O port */
2487 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2488 outb((conf->fir_io >> 3), iobase + 1);
2489 tmpbyte = inb(iobase + 1);
2490 if (tmpbyte != (conf->fir_io >> 3) ) {
2491 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2492 return -ENXIO;
2493 }
2494
2495 /* Set up FIR DMA channel */
2496 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2497 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2498 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2499 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2500 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2501 return -ENXIO;
2502 }
2503
2504 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2505 tmpbyte = inb(iobase + 1);
2506 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2507 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2508 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2509
2510 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2511 tmpbyte = inb(iobase + 1);
2512 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2513
2514 /* This one was not part of tosh1800 */
2515 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2516 tmpbyte = inb(iobase + 1);
2517 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2518
2519 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2520 tmpbyte = inb(iobase + 1);
2521 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2522
2523 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2524 tmpbyte = inb(iobase + 1);
2525 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2526
2527 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2528
2529 return 0;
2530 }
2531
2532 /* 82801CAM generic registers */
2533 #define VID 0x00
2534 #define DID 0x02
2535 #define PIRQ_A_D_ROUT 0x60
2536 #define SIRQ_CNTL 0x64
2537 #define PIRQ_E_H_ROUT 0x68
2538 #define PCI_DMA_C 0x90
2539 /* LPC-specific registers */
2540 #define COM_DEC 0xe0
2541 #define GEN1_DEC 0xe4
2542 #define LPC_EN 0xe6
2543 #define GEN2_DEC 0xec
2544 /*
2545 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2546 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2547 * They all work the same way!
2548 */
2549 static int __init preconfigure_through_82801(struct pci_dev *dev,
2550 struct
2551 smsc_ircc_subsystem_configuration
2552 *conf)
2553 {
2554 unsigned short tmpword;
2555 unsigned char tmpbyte;
2556
2557 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2558 /*
2559 * Select the range for the COMA COM port (SIR)
2560 * Register COM_DEC:
2561 * Bit 7: reserved
2562 * Bit 6-4, COMB decode range
2563 * Bit 3: reserved
2564 * Bit 2-0, COMA decode range
2565 *
2566 * Decode ranges:
2567 * 000 = 0x3f8-0x3ff (COM1)
2568 * 001 = 0x2f8-0x2ff (COM2)
2569 * 010 = 0x220-0x227
2570 * 011 = 0x228-0x22f
2571 * 100 = 0x238-0x23f
2572 * 101 = 0x2e8-0x2ef (COM4)
2573 * 110 = 0x338-0x33f
2574 * 111 = 0x3e8-0x3ef (COM3)
2575 */
2576 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2577 tmpbyte &= 0xf8; /* mask COMA bits */
2578 switch(conf->sir_io) {
2579 case 0x3f8:
2580 tmpbyte |= 0x00;
2581 break;
2582 case 0x2f8:
2583 tmpbyte |= 0x01;
2584 break;
2585 case 0x220:
2586 tmpbyte |= 0x02;
2587 break;
2588 case 0x228:
2589 tmpbyte |= 0x03;
2590 break;
2591 case 0x238:
2592 tmpbyte |= 0x04;
2593 break;
2594 case 0x2e8:
2595 tmpbyte |= 0x05;
2596 break;
2597 case 0x338:
2598 tmpbyte |= 0x06;
2599 break;
2600 case 0x3e8:
2601 tmpbyte |= 0x07;
2602 break;
2603 default:
2604 tmpbyte |= 0x01; /* COM2 default */
2605 }
2606 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2607 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2608
2609 /* Enable Low Pin Count interface */
2610 pci_read_config_word(dev, LPC_EN, &tmpword);
2611 /* These seem to be set up at all times,
2612 * just make sure it is properly set.
2613 */
2614 switch(conf->cfg_base) {
2615 case 0x04e:
2616 tmpword |= 0x2000;
2617 break;
2618 case 0x02e:
2619 tmpword |= 0x1000;
2620 break;
2621 case 0x062:
2622 tmpword |= 0x0800;
2623 break;
2624 case 0x060:
2625 tmpword |= 0x0400;
2626 break;
2627 default:
2628 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2629 conf->cfg_base);
2630 break;
2631 }
2632 tmpword &= 0xfffd; /* disable LPC COMB */
2633 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2634 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2635 pci_write_config_word(dev, LPC_EN, tmpword);
2636
2637 /*
2638 * Configure LPC DMA channel
2639 * PCI_DMA_C bits:
2640 * Bit 15-14: DMA channel 7 select
2641 * Bit 13-12: DMA channel 6 select
2642 * Bit 11-10: DMA channel 5 select
2643 * Bit 9-8: Reserved
2644 * Bit 7-6: DMA channel 3 select
2645 * Bit 5-4: DMA channel 2 select
2646 * Bit 3-2: DMA channel 1 select
2647 * Bit 1-0: DMA channel 0 select
2648 * 00 = Reserved value
2649 * 01 = PC/PCI DMA
2650 * 10 = Reserved value
2651 * 11 = LPC I/F DMA
2652 */
2653 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2654 switch(conf->fir_dma) {
2655 case 0x07:
2656 tmpword |= 0xc000;
2657 break;
2658 case 0x06:
2659 tmpword |= 0x3000;
2660 break;
2661 case 0x05:
2662 tmpword |= 0x0c00;
2663 break;
2664 case 0x03:
2665 tmpword |= 0x00c0;
2666 break;
2667 case 0x02:
2668 tmpword |= 0x0030;
2669 break;
2670 case 0x01:
2671 tmpword |= 0x000c;
2672 break;
2673 case 0x00:
2674 tmpword |= 0x0003;
2675 break;
2676 default:
2677 break; /* do not change settings */
2678 }
2679 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2680 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2681
2682 /*
2683 * GEN2_DEC bits:
2684 * Bit 15-4: Generic I/O range
2685 * Bit 3-1: reserved (read as 0)
2686 * Bit 0: enable GEN2 range on LPC I/F
2687 */
2688 tmpword = conf->fir_io & 0xfff8;
2689 tmpword |= 0x0001;
2690 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2691 pci_write_config_word(dev, GEN2_DEC, tmpword);
2692
2693 /* Pre-configure chip */
2694 return preconfigure_smsc_chip(conf);
2695 }
2696
2697 /*
2698 * Pre-configure a certain port on the ALi 1533 bridge.
2699 * This is based on reverse-engineering since ALi does not
2700 * provide any data sheet for the 1533 chip.
2701 */
2702 static void __init preconfigure_ali_port(struct pci_dev *dev,
2703 unsigned short port)
2704 {
2705 unsigned char reg;
2706 /* These bits obviously control the different ports */
2707 unsigned char mask;
2708 unsigned char tmpbyte;
2709
2710 switch(port) {
2711 case 0x0130:
2712 case 0x0178:
2713 reg = 0xb0;
2714 mask = 0x80;
2715 break;
2716 case 0x03f8:
2717 reg = 0xb4;
2718 mask = 0x80;
2719 break;
2720 case 0x02f8:
2721 reg = 0xb4;
2722 mask = 0x30;
2723 break;
2724 case 0x02e8:
2725 reg = 0xb4;
2726 mask = 0x08;
2727 break;
2728 default:
2729 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2730 return;
2731 }
2732
2733 pci_read_config_byte(dev, reg, &tmpbyte);
2734 /* Turn on the right bits */
2735 tmpbyte |= mask;
2736 pci_write_config_byte(dev, reg, tmpbyte);
2737 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2738 return;
2739 }
2740
2741 static int __init preconfigure_through_ali(struct pci_dev *dev,
2742 struct
2743 smsc_ircc_subsystem_configuration
2744 *conf)
2745 {
2746 /* Configure the two ports on the ALi 1533 */
2747 preconfigure_ali_port(dev, conf->sir_io);
2748 preconfigure_ali_port(dev, conf->fir_io);
2749
2750 /* Pre-configure chip */
2751 return preconfigure_smsc_chip(conf);
2752 }
2753
2754 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2755 unsigned short ircc_fir,
2756 unsigned short ircc_sir,
2757 unsigned char ircc_dma,
2758 unsigned char ircc_irq)
2759 {
2760 struct pci_dev *dev = NULL;
2761 unsigned short ss_vendor = 0x0000;
2762 unsigned short ss_device = 0x0000;
2763 int ret = 0;
2764
2765 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2766
2767 while (dev != NULL) {
2768 struct smsc_ircc_subsystem_configuration *conf;
2769
2770 /*
2771 * Cache the subsystem vendor/device:
2772 * some manufacturers fail to set this for all components,
2773 * so we save it in case there is just 0x0000 0x0000 on the
2774 * device we want to check.
2775 */
2776 if (dev->subsystem_vendor != 0x0000U) {
2777 ss_vendor = dev->subsystem_vendor;
2778 ss_device = dev->subsystem_device;
2779 }
2780 conf = subsystem_configurations;
2781 for( ; conf->subvendor; conf++) {
2782 if(conf->vendor == dev->vendor &&
2783 conf->device == dev->device &&
2784 conf->subvendor == ss_vendor &&
2785 /* Sometimes these are cached values */
2786 (conf->subdevice == ss_device ||
2787 conf->subdevice == 0xffff)) {
2788 struct smsc_ircc_subsystem_configuration
2789 tmpconf;
2790
2791 memcpy(&tmpconf, conf,
2792 sizeof(struct smsc_ircc_subsystem_configuration));
2793
2794 /*
2795 * Override the default values with anything
2796 * passed in as parameter
2797 */
2798 if (ircc_cfg != 0)
2799 tmpconf.cfg_base = ircc_cfg;
2800 if (ircc_fir != 0)
2801 tmpconf.fir_io = ircc_fir;
2802 if (ircc_sir != 0)
2803 tmpconf.sir_io = ircc_sir;
2804 if (ircc_dma != 0xff)
2805 tmpconf.fir_dma = ircc_dma;
2806 if (ircc_irq != 0xff)
2807 tmpconf.fir_irq = ircc_irq;
2808
2809 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2810 if (conf->preconfigure)
2811 ret = conf->preconfigure(dev, &tmpconf);
2812 else
2813 ret = -ENODEV;
2814 }
2815 }
2816 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2817 }
2818
2819 return ret;
2820 }
2821 #endif // CONFIG_PCI
2822
2823 /************************************************
2824 *
2825 * Transceivers specific functions
2826 *
2827 ************************************************/
2828
2829
2830 /*
2831 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2832 *
2833 * Program transceiver through smsc-ircc ATC circuitry
2834 *
2835 */
2836
2837 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2838 {
2839 unsigned long jiffies_now, jiffies_timeout;
2840 u8 val;
2841
2842 jiffies_now = jiffies;
2843 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2844
2845 /* ATC */
2846 register_bank(fir_base, 4);
2847 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2848 fir_base + IRCC_ATC);
2849
2850 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2851 !time_after(jiffies, jiffies_timeout))
2852 /* empty */;
2853
2854 if (val)
2855 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2856 inb(fir_base + IRCC_ATC));
2857 }
2858
2859 /*
2860 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2861 *
2862 * Probe transceiver smsc-ircc ATC circuitry
2863 *
2864 */
2865
2866 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2867 {
2868 return 0;
2869 }
2870
2871 /*
2872 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2873 *
2874 * Set transceiver
2875 *
2876 */
2877
2878 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2879 {
2880 u8 fast_mode;
2881
2882 switch (speed) {
2883 default:
2884 case 576000 :
2885 fast_mode = 0;
2886 break;
2887 case 1152000 :
2888 case 4000000 :
2889 fast_mode = IRCC_LCR_A_FAST;
2890 break;
2891 }
2892 register_bank(fir_base, 0);
2893 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2894 }
2895
2896 /*
2897 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2898 *
2899 * Probe transceiver
2900 *
2901 */
2902
2903 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2904 {
2905 return 0;
2906 }
2907
2908 /*
2909 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2910 *
2911 * Set transceiver
2912 *
2913 */
2914
2915 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2916 {
2917 u8 fast_mode;
2918
2919 switch (speed) {
2920 default:
2921 case 576000 :
2922 fast_mode = 0;
2923 break;
2924 case 1152000 :
2925 case 4000000 :
2926 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2927 break;
2928
2929 }
2930 /* This causes an interrupt */
2931 register_bank(fir_base, 0);
2932 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2933 }
2934
2935 /*
2936 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2937 *
2938 * Probe transceiver
2939 *
2940 */
2941
2942 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2943 {
2944 return 0;
2945 }
2946
2947
2948 module_init(smsc_ircc_init);
2949 module_exit(smsc_ircc_cleanup);
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