2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
11 * Licensed under the GPL-2 or later.
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/plat-ram.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/flash.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/i2c.h>
28 #include <linux/spi/mmc_spi.h>
29 #include <linux/phy.h>
31 #include <asm/bfin5xx_spi.h>
32 #include <asm/reboot.h>
33 #include <asm/portmux.h>
37 * Name the Board for the /proc/cpuinfo
39 const char bfin_board_name
[] = "DNP/5370";
40 #define FLASH_MAC 0x202f0000
41 #define CONFIG_MTD_PHYSMAP_LEN 0x300000
43 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44 static struct platform_device rtc_device
= {
50 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51 #include <linux/bfin_mac.h>
52 #include <linux/export.h>
53 static const unsigned short bfin_mac_peripherals
[] = P_RMII0
;
55 static struct bfin_phydev_platform_data bfin_phydev_data
[] = {
58 .irq
= PHY_POLL
, /* IRQ_MAC_PHYINT */
62 static struct bfin_mii_bus_platform_data bfin_mii_bus_data
= {
64 .phydev_data
= bfin_phydev_data
,
65 .phy_mode
= PHY_INTERFACE_MODE_RMII
,
66 .mac_peripherals
= bfin_mac_peripherals
,
69 static struct platform_device bfin_mii_bus
= {
70 .name
= "bfin_mii_bus",
72 .platform_data
= &bfin_mii_bus_data
,
76 static struct platform_device bfin_mac_device
= {
79 .platform_data
= &bfin_mii_bus
,
84 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
85 static struct mtd_partition asmb_flash_partitions
[] = {
87 .name
= "bootloader(nor)",
91 .name
= "linux kernel and rootfs(nor)",
92 .size
= 0x300000 - 0x30000 - 0x10000,
93 .offset
= MTDPART_OFS_APPEND
,
95 .name
= "MAC address(nor)",
97 .offset
= MTDPART_OFS_APPEND
,
98 .mask_flags
= MTD_WRITEABLE
,
102 static struct physmap_flash_data asmb_flash_data
= {
104 .parts
= asmb_flash_partitions
,
105 .nr_parts
= ARRAY_SIZE(asmb_flash_partitions
),
108 static struct resource asmb_flash_resource
= {
111 .flags
= IORESOURCE_MEM
,
114 /* 4 MB NOR flash attached to async memory banks 0-2,
115 * therefore only 3 MB visible.
117 static struct platform_device asmb_flash_device
= {
118 .name
= "physmap-flash",
121 .platform_data
= &asmb_flash_data
,
124 .resource
= &asmb_flash_resource
,
128 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
130 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
132 static struct bfin5xx_spi_chip mmc_spi_chip_info
= {
133 .enable_dma
= 0, /* use no dma transfer with this chip*/
138 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
139 /* This mapping is for at45db642 it has 1056 page size,
140 * partition size and offset should be page aligned
142 static struct mtd_partition bfin_spi_dataflash_partitions
[] = {
144 .name
= "JFFS2 dataflash(nor)",
145 #ifdef CONFIG_MTD_PAGESIZE_1024
155 static struct flash_platform_data bfin_spi_dataflash_data
= {
156 .name
= "mtd_dataflash",
157 .parts
= bfin_spi_dataflash_partitions
,
158 .nr_parts
= ARRAY_SIZE(bfin_spi_dataflash_partitions
),
159 .type
= "mtd_dataflash",
162 static struct bfin5xx_spi_chip spi_dataflash_chip_info
= {
163 .enable_dma
= 0, /* use no dma transfer with this chip*/
167 static struct spi_board_info bfin_spi_board_info
[] __initdata
= {
168 /* SD/MMC card reader at SPI bus */
169 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
171 .modalias
= "mmc_spi",
172 .max_speed_hz
= 20000000,
175 .controller_data
= &mmc_spi_chip_info
,
180 /* 8 Megabyte Atmel NOR flash chip at SPI bus */
181 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
183 .modalias
= "mtd_dataflash",
184 .max_speed_hz
= 16700000,
187 .platform_data
= &bfin_spi_dataflash_data
,
188 .controller_data
= &spi_dataflash_chip_info
,
189 .mode
= SPI_MODE_3
, /* SPI_CPHA and SPI_CPOL */
194 /* SPI controller data */
196 static struct resource bfin_spi0_resource
[] = {
198 .start
= SPI0_REGBASE
,
199 .end
= SPI0_REGBASE
+ 0xFF,
200 .flags
= IORESOURCE_MEM
,
205 .flags
= IORESOURCE_DMA
,
210 .flags
= IORESOURCE_IRQ
,
214 static struct bfin5xx_spi_master spi_bfin_master_info
= {
216 .enable_dma
= 1, /* master has the ability to do dma transfer */
217 .pin_req
= {P_SPI0_SCK
, P_SPI0_MISO
, P_SPI0_MOSI
, 0},
220 static struct platform_device spi_bfin_master_device
= {
222 .id
= 0, /* Bus number */
223 .num_resources
= ARRAY_SIZE(bfin_spi0_resource
),
224 .resource
= bfin_spi0_resource
,
226 .platform_data
= &spi_bfin_master_info
, /* Passed to driver */
231 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
232 #ifdef CONFIG_SERIAL_BFIN_UART0
233 static struct resource bfin_uart0_resources
[] = {
237 .flags
= IORESOURCE_MEM
,
240 .start
= IRQ_UART0_RX
,
241 .end
= IRQ_UART0_RX
+1,
242 .flags
= IORESOURCE_IRQ
,
245 .start
= IRQ_UART0_ERROR
,
246 .end
= IRQ_UART0_ERROR
,
247 .flags
= IORESOURCE_IRQ
,
250 .start
= CH_UART0_TX
,
252 .flags
= IORESOURCE_DMA
,
255 .start
= CH_UART0_RX
,
257 .flags
= IORESOURCE_DMA
,
261 static unsigned short bfin_uart0_peripherals
[] = {
262 P_UART0_TX
, P_UART0_RX
, 0
265 static struct platform_device bfin_uart0_device
= {
268 .num_resources
= ARRAY_SIZE(bfin_uart0_resources
),
269 .resource
= bfin_uart0_resources
,
271 .platform_data
= &bfin_uart0_peripherals
, /* Passed to driver */
276 #ifdef CONFIG_SERIAL_BFIN_UART1
277 static struct resource bfin_uart1_resources
[] = {
281 .flags
= IORESOURCE_MEM
,
284 .start
= IRQ_UART1_RX
,
285 .end
= IRQ_UART1_RX
+1,
286 .flags
= IORESOURCE_IRQ
,
289 .start
= IRQ_UART1_ERROR
,
290 .end
= IRQ_UART1_ERROR
,
291 .flags
= IORESOURCE_IRQ
,
294 .start
= CH_UART1_TX
,
296 .flags
= IORESOURCE_DMA
,
299 .start
= CH_UART1_RX
,
301 .flags
= IORESOURCE_DMA
,
305 static unsigned short bfin_uart1_peripherals
[] = {
306 P_UART1_TX
, P_UART1_RX
, 0
309 static struct platform_device bfin_uart1_device
= {
312 .num_resources
= ARRAY_SIZE(bfin_uart1_resources
),
313 .resource
= bfin_uart1_resources
,
315 .platform_data
= &bfin_uart1_peripherals
, /* Passed to driver */
321 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
322 static struct resource bfin_twi0_resource
[] = {
324 .start
= TWI0_REGBASE
,
325 .end
= TWI0_REGBASE
+ 0xff,
326 .flags
= IORESOURCE_MEM
,
331 .flags
= IORESOURCE_IRQ
,
335 static struct platform_device i2c_bfin_twi_device
= {
336 .name
= "i2c-bfin-twi",
338 .num_resources
= ARRAY_SIZE(bfin_twi0_resource
),
339 .resource
= bfin_twi0_resource
,
343 static struct platform_device
*dnp5370_devices
[] __initdata
= {
345 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
346 #ifdef CONFIG_SERIAL_BFIN_UART0
349 #ifdef CONFIG_SERIAL_BFIN_UART1
354 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
358 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
363 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
364 &spi_bfin_master_device
,
367 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
368 &i2c_bfin_twi_device
,
371 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
377 static int __init
dnp5370_init(void)
379 printk(KERN_INFO
"DNP/5370: registering device resources\n");
380 platform_add_devices(dnp5370_devices
, ARRAY_SIZE(dnp5370_devices
));
381 printk(KERN_INFO
"DNP/5370: registering %zu SPI slave devices\n",
382 ARRAY_SIZE(bfin_spi_board_info
));
383 spi_register_board_info(bfin_spi_board_info
, ARRAY_SIZE(bfin_spi_board_info
));
384 printk(KERN_INFO
"DNP/5370: MAC %pM\n", (void *)FLASH_MAC
);
387 arch_initcall(dnp5370_init
);
390 * Currently the MAC address is saved in Flash by U-Boot
392 void bfin_get_ether_addr(char *addr
)
394 *(u32
*)(&(addr
[0])) = bfin_read32(FLASH_MAC
);
395 *(u16
*)(&(addr
[4])) = bfin_read16(FLASH_MAC
+ 4);
397 EXPORT_SYMBOL(bfin_get_ether_addr
);