arch/blackfin/mach-common/smp.c

   1 /*
   2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
   3  *
   4  * Copyright 2007-2009 Analog Devices Inc.
   5  *                         Philippe Gerum <rpm@xenomai.org>
   6  *
   7  * Licensed under the GPL-2.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/sched.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/cache.h>
  17 #include <linux/profile.h>
  18 #include <linux/errno.h>
  19 #include <linux/mm.h>
  20 #include <linux/cpu.h>
  21 #include <linux/smp.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/irq.h>
  25 #include <linux/slab.h>
  26 #include <linux/atomic.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/irq_handler.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/pgalloc.h>
  32 #include <asm/processor.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/cpu.h>
  35 #include <asm/time.h>
  36 #include <linux/err.h>
  37
  38 /*
  39  * Anomaly notes:
  40  * 05000120 - we always define corelock as 32-bit integer in L2
  41  */
  42 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  43
  44 #ifdef CONFIG_ICACHE_FLUSH_L1
  45 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
  46 #endif
  47
  48 struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
  49
  50 #define BFIN_IPI_RESCHEDULE   0
  51 #define BFIN_IPI_CALL_FUNC    1
  52 #define BFIN_IPI_CPU_STOP     2
  53
  54 struct blackfin_flush_data {
  55         unsigned long start;
  56         unsigned long end;
  57 };
  58
  59 void *secondary_stack;
  60
  61
  62 struct smp_call_struct {
  63         void (*func)(void *info);
  64         void *info;
  65         int wait;
  66         cpumask_t *waitmask;
  67 };
  68
  69 static struct blackfin_flush_data smp_flush_data;
  70
  71 static DEFINE_SPINLOCK(stop_lock);
  72
  73 struct ipi_message {
  74         unsigned long type;
  75         struct smp_call_struct call_struct;
  76 };
  77
  78 /* A magic number - stress test shows this is safe for common cases */
  79 #define BFIN_IPI_MSGQ_LEN 5
  80
  81 /* Simple FIFO buffer, overflow leads to panic */
  82 struct ipi_message_queue {
  83         spinlock_t lock;
  84         unsigned long count;
  85         unsigned long head; /* head of the queue */
  86         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
  87 };
  88
  89 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
  90
  91 static void ipi_cpu_stop(unsigned int cpu)
  92 {
  93         spin_lock(&stop_lock);
  94         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  95         dump_stack();
  96         spin_unlock(&stop_lock);
  97
  98         set_cpu_online(cpu, false);
  99
 100         local_irq_disable();
 101
 102         while (1)
 103                 SSYNC();
 104 }
 105
 106 static void ipi_flush_icache(void *info)
 107 {
 108         struct blackfin_flush_data *fdata = info;
 109
 110         /* Invalidate the memory holding the bounds of the flushed region. */
 111         blackfin_dcache_invalidate_range((unsigned long)fdata,
 112                                          (unsigned long)fdata + sizeof(*fdata));
 113
 114         /* Make sure all write buffers in the data side of the core
 115          * are flushed before trying to invalidate the icache.  This
 116          * needs to be after the data flush and before the icache
 117          * flush so that the SSYNC does the right thing in preventing
 118          * the instruction prefetcher from hitting things in cached
 119          * memory at the wrong time -- it runs much further ahead than
 120          * the pipeline.
 121          */
 122         SSYNC();
 123
 124         /* ipi_flaush_icache is invoked by generic flush_icache_range,
 125          * so call blackfin arch icache flush directly here.
 126          */
 127         blackfin_icache_flush_range(fdata->start, fdata->end);
 128 }
 129
 130 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
 131 {
 132         int wait;
 133         void (*func)(void *info);
 134         void *info;
 135         func = msg->call_struct.func;
 136         info = msg->call_struct.info;
 137         wait = msg->call_struct.wait;
 138         func(info);
 139         if (wait) {
 140 #ifdef __ARCH_SYNC_CORE_DCACHE
 141                 /*
 142                  * 'wait' usually means synchronization between CPUs.
 143                  * Invalidate D cache in case shared data was changed
 144                  * by func() to ensure cache coherence.
 145                  */
 146                 resync_core_dcache();
 147 #endif
 148                 cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
 149         }
 150 }
 151
 152 /* Use IRQ_SUPPLE_0 to request reschedule.
 153  * When returning from interrupt to user space,
 154  * there is chance to reschedule */
 155 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
 156 {
 157         unsigned int cpu = smp_processor_id();
 158
 159         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
 160         return IRQ_HANDLED;
 161 }
 162
 163 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 164 {
 165         struct ipi_message *msg;
 166         struct ipi_message_queue *msg_queue;
 167         unsigned int cpu = smp_processor_id();
 168         unsigned long flags;
 169
 170         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 171
 172         msg_queue = &__get_cpu_var(ipi_msg_queue);
 173
 174         spin_lock_irqsave(&msg_queue->lock, flags);
 175
 176         while (msg_queue->count) {
 177                 msg = &msg_queue->ipi_message[msg_queue->head];
 178                 switch (msg->type) {
 179                 case BFIN_IPI_RESCHEDULE:
 180                         scheduler_ipi();
 181                         break;
 182                 case BFIN_IPI_CALL_FUNC:
 183                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 184                         ipi_call_function(cpu, msg);
 185                         spin_lock_irqsave(&msg_queue->lock, flags);
 186                         break;
 187                 case BFIN_IPI_CPU_STOP:
 188                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 189                         ipi_cpu_stop(cpu);
 190                         spin_lock_irqsave(&msg_queue->lock, flags);
 191                         break;
 192                 default:
 193                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
 194                                cpu, msg->type);
 195                         break;
 196                 }
 197                 msg_queue->head++;
 198                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
 199                 msg_queue->count--;
 200         }
 201         spin_unlock_irqrestore(&msg_queue->lock, flags);
 202         return IRQ_HANDLED;
 203 }
 204
 205 static void ipi_queue_init(void)
 206 {
 207         unsigned int cpu;
 208         struct ipi_message_queue *msg_queue;
 209         for_each_possible_cpu(cpu) {
 210                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 211                 spin_lock_init(&msg_queue->lock);
 212                 msg_queue->count = 0;
 213                 msg_queue->head = 0;
 214         }
 215 }
 216
 217 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
 218                                         void (*func) (void *info), void *info, int wait)
 219 {
 220         unsigned int cpu;
 221         struct ipi_message_queue *msg_queue;
 222         struct ipi_message *msg;
 223         unsigned long flags, next_msg;
 224         cpumask_t waitmask; /* waitmask is shared by all cpus */
 225
 226         cpumask_copy(&waitmask, &callmap);
 227         for_each_cpu(cpu, &callmap) {
 228                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 229                 spin_lock_irqsave(&msg_queue->lock, flags);
 230                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
 231                         next_msg = (msg_queue->head + msg_queue->count)
 232                                         % BFIN_IPI_MSGQ_LEN;
 233                         msg = &msg_queue->ipi_message[next_msg];
 234                         msg->type = type;
 235                         if (type == BFIN_IPI_CALL_FUNC) {
 236                                 msg->call_struct.func = func;
 237                                 msg->call_struct.info = info;
 238                                 msg->call_struct.wait = wait;
 239                                 msg->call_struct.waitmask = &waitmask;
 240                         }
 241                         msg_queue->count++;
 242                 } else
 243                         panic("IPI message queue overflow\n");
 244                 spin_unlock_irqrestore(&msg_queue->lock, flags);
 245                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
 246         }
 247
 248         if (wait) {
 249                 while (!cpumask_empty(&waitmask))
 250                         blackfin_dcache_invalidate_range(
 251                                 (unsigned long)(&waitmask),
 252                                 (unsigned long)(&waitmask));
 253 #ifdef __ARCH_SYNC_CORE_DCACHE
 254                 /*
 255                  * Invalidate D cache in case shared data was changed by
 256                  * other processors to ensure cache coherence.
 257                  */
 258                 resync_core_dcache();
 259 #endif
 260         }
 261 }
 262
 263 int smp_call_function(void (*func)(void *info), void *info, int wait)
 264 {
 265         cpumask_t callmap;
 266
 267         preempt_disable();
 268         cpumask_copy(&callmap, cpu_online_mask);
 269         cpumask_clear_cpu(smp_processor_id(), &callmap);
 270         if (!cpumask_empty(&callmap))
 271                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 272
 273         preempt_enable();
 274
 275         return 0;
 276 }
 277 EXPORT_SYMBOL_GPL(smp_call_function);
 278
 279 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 280                                 int wait)
 281 {
 282         unsigned int cpu = cpuid;
 283         cpumask_t callmap;
 284
 285         if (cpu_is_offline(cpu))
 286                 return 0;
 287         cpumask_clear(&callmap);
 288         cpumask_set_cpu(cpu, &callmap);
 289
 290         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 291
 292         return 0;
 293 }
 294 EXPORT_SYMBOL_GPL(smp_call_function_single);
 295
 296 void smp_send_reschedule(int cpu)
 297 {
 298         /* simply trigger an ipi */
 299         if (cpu_is_offline(cpu))
 300                 return;
 301         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 302
 303         return;
 304 }
 305
 306 void smp_send_stop(void)
 307 {
 308         cpumask_t callmap;
 309
 310         preempt_disable();
 311         cpumask_copy(&callmap, cpu_online_mask);
 312         cpumask_clear_cpu(smp_processor_id(), &callmap);
 313         if (!cpumask_empty(&callmap))
 314                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 315
 316         preempt_enable();
 317
 318         return;
 319 }
 320
 321 int __cpuinit __cpu_up(unsigned int cpu)
 322 {
 323         int ret;
 324         static struct task_struct *idle;
 325
 326         if (idle)
 327                 free_task(idle);
 328
 329         idle = fork_idle(cpu);
 330         if (IS_ERR(idle)) {
 331                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
 332                 return PTR_ERR(idle);
 333         }
 334
 335         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
 336
 337         ret = platform_boot_secondary(cpu, idle);
 338
 339         secondary_stack = NULL;
 340
 341         return ret;
 342 }
 343
 344 static void __cpuinit setup_secondary(unsigned int cpu)
 345 {
 346         unsigned long ilat;
 347
 348         bfin_write_IMASK(0);
 349         CSYNC();
 350         ilat = bfin_read_ILAT();
 351         CSYNC();
 352         bfin_write_ILAT(ilat);
 353         CSYNC();
 354
 355         /* Enable interrupt levels IVG7-15. IARs have been already
 356          * programmed by the boot CPU.  */
 357         bfin_irq_flags |= IMASK_IVG15 |
 358             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 359             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 360 }
 361
 362 void __cpuinit secondary_start_kernel(void)
 363 {
 364         unsigned int cpu = smp_processor_id();
 365         struct mm_struct *mm = &init_mm;
 366
 367         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
 368                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 369 #ifdef CONFIG_DEBUG_DOUBLEFAULT
 370                 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
 371                         initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
 372                         initial_pda_coreb.retx_doublefault);
 373                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
 374                         initial_pda_coreb.dcplb_doublefault_addr);
 375                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
 376                         initial_pda_coreb.icplb_doublefault_addr);
 377 #endif
 378                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
 379                         initial_pda_coreb.retx);
 380         }
 381
 382         /*
 383          * We want the D-cache to be enabled early, in case the atomic
 384          * support code emulates cache coherence (see
 385          * __ARCH_SYNC_CORE_DCACHE).
 386          */
 387         init_exception_vectors();
 388
 389         local_irq_disable();
 390
 391         /* Attach the new idle task to the global mm. */
 392         atomic_inc(&mm->mm_users);
 393         atomic_inc(&mm->mm_count);
 394         current->active_mm = mm;
 395
 396         preempt_disable();
 397
 398         setup_secondary(cpu);
 399
 400         platform_secondary_init(cpu);
 401
 402         /* setup local core timer */
 403         bfin_local_timer_setup();
 404
 405         local_irq_enable();
 406
 407         bfin_setup_caches(cpu);
 408
 409         /*
 410          * Calibrate loops per jiffy value.
 411          * IRQs need to be enabled here - D-cache can be invalidated
 412          * in timer irq handler, so core B can read correct jiffies.
 413          */
 414         calibrate_delay();
 415
 416         cpu_idle();
 417 }
 418
 419 void __init smp_prepare_boot_cpu(void)
 420 {
 421 }
 422
 423 void __init smp_prepare_cpus(unsigned int max_cpus)
 424 {
 425         platform_prepare_cpus(max_cpus);
 426         ipi_queue_init();
 427         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
 428         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 429 }
 430
 431 void __init smp_cpus_done(unsigned int max_cpus)
 432 {
 433         unsigned long bogosum = 0;
 434         unsigned int cpu;
 435
 436         for_each_online_cpu(cpu)
 437                 bogosum += loops_per_jiffy;
 438
 439         printk(KERN_INFO "SMP: Total of %d processors activated "
 440                "(%lu.%02lu BogoMIPS).\n",
 441                num_online_cpus(),
 442                bogosum / (500000/HZ),
 443                (bogosum / (5000/HZ)) % 100);
 444 }
 445
 446 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
 447 {
 448         smp_flush_data.start = start;
 449         smp_flush_data.end = end;
 450
 451         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
 452                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
 453 }
 454 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
 455
 456 #ifdef __ARCH_SYNC_CORE_ICACHE
 457 unsigned long icache_invld_count[NR_CPUS];
 458 void resync_core_icache(void)
 459 {
 460         unsigned int cpu = get_cpu();
 461         blackfin_invalidate_entire_icache();
 462         icache_invld_count[cpu]++;
 463         put_cpu();
 464 }
 465 EXPORT_SYMBOL(resync_core_icache);
 466 #endif
 467
 468 #ifdef __ARCH_SYNC_CORE_DCACHE
 469 unsigned long dcache_invld_count[NR_CPUS];
 470 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
 471
 472 void resync_core_dcache(void)
 473 {
 474         unsigned int cpu = get_cpu();
 475         blackfin_invalidate_entire_dcache();
 476         dcache_invld_count[cpu]++;
 477         put_cpu();
 478 }
 479 EXPORT_SYMBOL(resync_core_dcache);
 480 #endif
 481
 482 #ifdef CONFIG_HOTPLUG_CPU
 483 int __cpuexit __cpu_disable(void)
 484 {
 485         unsigned int cpu = smp_processor_id();
 486
 487         if (cpu == 0)
 488                 return -EPERM;
 489
 490         set_cpu_online(cpu, false);
 491         return 0;
 492 }
 493
 494 static DECLARE_COMPLETION(cpu_killed);
 495
 496 int __cpuexit __cpu_die(unsigned int cpu)
 497 {
 498         return wait_for_completion_timeout(&cpu_killed, 5000);
 499 }
 500
 501 void cpu_die(void)
 502 {
 503         complete(&cpu_killed);
 504
 505         atomic_dec(&init_mm.mm_users);
 506         atomic_dec(&init_mm.mm_count);
 507
 508         local_irq_disable();
 509         platform_cpu_die();
 510 }
 511 #endif