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include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / gpio / gpio-ep93xx.c
blob468b27dfd5412e5b848fc5f1bbcb8fa4c9dab228
1 /*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/slab.h>
23 #include <linux/basic_mmio_gpio.h>
24 #include <linux/module.h>
25
26 #include <mach/hardware.h>
27
28 struct ep93xx_gpio {
29 void __iomem *mmio_base;
30 struct bgpio_chip bgc[8];
31 };
32
33 /*************************************************************************
34 * Interrupt handling for EP93xx on-chip GPIOs
35 *************************************************************************/
36 static unsigned char gpio_int_unmasked[3];
37 static unsigned char gpio_int_enabled[3];
38 static unsigned char gpio_int_type1[3];
39 static unsigned char gpio_int_type2[3];
40 static unsigned char gpio_int_debounce[3];
41
42 /* Port ordering is: A B F */
43 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
44 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
45 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
46 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
47 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
48
49 static void ep93xx_gpio_update_int_params(unsigned port)
50 {
51 BUG_ON(port > 2);
52
53 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
54
55 __raw_writeb(gpio_int_type2[port],
56 EP93XX_GPIO_REG(int_type2_register_offset[port]));
57
58 __raw_writeb(gpio_int_type1[port],
59 EP93XX_GPIO_REG(int_type1_register_offset[port]));
60
61 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
62 EP93XX_GPIO_REG(int_en_register_offset[port]));
63 }
64
65 static inline void ep93xx_gpio_int_mask(unsigned line)
66 {
67 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
68 }
69
70 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
71 {
72 int line = irq_to_gpio(irq);
73 int port = line >> 3;
74 int port_mask = 1 << (line & 7);
75
76 if (enable)
77 gpio_int_debounce[port] |= port_mask;
78 else
79 gpio_int_debounce[port] &= ~port_mask;
80
81 __raw_writeb(gpio_int_debounce[port],
82 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
83 }
84
85 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
86 {
87 unsigned char status;
88 int i;
89
90 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
91 for (i = 0; i < 8; i++) {
92 if (status & (1 << i)) {
93 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
94 generic_handle_irq(gpio_irq);
95 }
96 }
97
98 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
99 for (i = 0; i < 8; i++) {
100 if (status & (1 << i)) {
101 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
102 generic_handle_irq(gpio_irq);
103 }
104 }
105 }
106
107 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
108 {
109 /*
110 * map discontiguous hw irq range to continuous sw irq range:
111 *
112 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
113 */
114 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
115 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
116
117 generic_handle_irq(gpio_irq);
118 }
119
120 static void ep93xx_gpio_irq_ack(struct irq_data *d)
121 {
122 int line = irq_to_gpio(d->irq);
123 int port = line >> 3;
124 int port_mask = 1 << (line & 7);
125
126 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
127 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
128 ep93xx_gpio_update_int_params(port);
129 }
130
131 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
132 }
133
134 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
135 {
136 int line = irq_to_gpio(d->irq);
137 int port = line >> 3;
138 int port_mask = 1 << (line & 7);
139
140 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
141 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
142
143 gpio_int_unmasked[port] &= ~port_mask;
144 ep93xx_gpio_update_int_params(port);
145
146 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
147 }
148
149 static void ep93xx_gpio_irq_mask(struct irq_data *d)
150 {
151 int line = irq_to_gpio(d->irq);
152 int port = line >> 3;
153
154 gpio_int_unmasked[port] &= ~(1 << (line & 7));
155 ep93xx_gpio_update_int_params(port);
156 }
157
158 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
159 {
160 int line = irq_to_gpio(d->irq);
161 int port = line >> 3;
162
163 gpio_int_unmasked[port] |= 1 << (line & 7);
164 ep93xx_gpio_update_int_params(port);
165 }
166
167 /*
168 * gpio_int_type1 controls whether the interrupt is level (0) or
169 * edge (1) triggered, while gpio_int_type2 controls whether it
170 * triggers on low/falling (0) or high/rising (1).
171 */
172 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
173 {
174 const int gpio = irq_to_gpio(d->irq);
175 const int port = gpio >> 3;
176 const int port_mask = 1 << (gpio & 7);
177 irq_flow_handler_t handler;
178
179 gpio_direction_input(gpio);
180
181 switch (type) {
182 case IRQ_TYPE_EDGE_RISING:
183 gpio_int_type1[port] |= port_mask;
184 gpio_int_type2[port] |= port_mask;
185 handler = handle_edge_irq;
186 break;
187 case IRQ_TYPE_EDGE_FALLING:
188 gpio_int_type1[port] |= port_mask;
189 gpio_int_type2[port] &= ~port_mask;
190 handler = handle_edge_irq;
191 break;
192 case IRQ_TYPE_LEVEL_HIGH:
193 gpio_int_type1[port] &= ~port_mask;
194 gpio_int_type2[port] |= port_mask;
195 handler = handle_level_irq;
196 break;
197 case IRQ_TYPE_LEVEL_LOW:
198 gpio_int_type1[port] &= ~port_mask;
199 gpio_int_type2[port] &= ~port_mask;
200 handler = handle_level_irq;
201 break;
202 case IRQ_TYPE_EDGE_BOTH:
203 gpio_int_type1[port] |= port_mask;
204 /* set initial polarity based on current input level */
205 if (gpio_get_value(gpio))
206 gpio_int_type2[port] &= ~port_mask; /* falling */
207 else
208 gpio_int_type2[port] |= port_mask; /* rising */
209 handler = handle_edge_irq;
210 break;
211 default:
212 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
213 return -EINVAL;
214 }
215
216 __irq_set_handler_locked(d->irq, handler);
217
218 gpio_int_enabled[port] |= port_mask;
219
220 ep93xx_gpio_update_int_params(port);
221
222 return 0;
223 }
224
225 static struct irq_chip ep93xx_gpio_irq_chip = {
226 .name = "GPIO",
227 .irq_ack = ep93xx_gpio_irq_ack,
228 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
229 .irq_mask = ep93xx_gpio_irq_mask,
230 .irq_unmask = ep93xx_gpio_irq_unmask,
231 .irq_set_type = ep93xx_gpio_irq_type,
232 };
233
234 static void ep93xx_gpio_init_irq(void)
235 {
236 int gpio_irq;
237
238 for (gpio_irq = gpio_to_irq(0);
239 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
240 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
241 handle_level_irq);
242 set_irq_flags(gpio_irq, IRQF_VALID);
243 }
244
245 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
246 ep93xx_gpio_ab_irq_handler);
247 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
248 ep93xx_gpio_f_irq_handler);
249 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
250 ep93xx_gpio_f_irq_handler);
251 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
252 ep93xx_gpio_f_irq_handler);
253 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
254 ep93xx_gpio_f_irq_handler);
255 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
256 ep93xx_gpio_f_irq_handler);
257 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
258 ep93xx_gpio_f_irq_handler);
259 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
260 ep93xx_gpio_f_irq_handler);
261 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
262 ep93xx_gpio_f_irq_handler);
263 }
264
265
266 /*************************************************************************
267 * gpiolib interface for EP93xx on-chip GPIOs
268 *************************************************************************/
269 struct ep93xx_gpio_bank {
270 const char *label;
271 int data;
272 int dir;
273 int base;
274 bool has_debounce;
275 };
276
277 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
278 { \
279 .label = _label, \
280 .data = _data, \
281 .dir = _dir, \
282 .base = _base, \
283 .has_debounce = _debounce, \
284 }
285
286 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
287 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
288 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
289 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
290 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
291 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
292 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
293 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
294 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
295 };
296
297 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
298 unsigned offset, unsigned debounce)
299 {
300 int gpio = chip->base + offset;
301 int irq = gpio_to_irq(gpio);
302
303 if (irq < 0)
304 return -EINVAL;
305
306 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
307
308 return 0;
309 }
310
311 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
312 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
313 {
314 void __iomem *data = mmio_base + bank->data;
315 void __iomem *dir = mmio_base + bank->dir;
316 int err;
317
318 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
319 if (err)
320 return err;
321
322 bgc->gc.label = bank->label;
323 bgc->gc.base = bank->base;
324
325 if (bank->has_debounce)
326 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
327
328 return gpiochip_add(&bgc->gc);
329 }
330
331 static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
332 {
333 struct ep93xx_gpio *ep93xx_gpio;
334 struct resource *res;
335 void __iomem *mmio;
336 int i;
337 int ret;
338
339 ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
340 if (!ep93xx_gpio)
341 return -ENOMEM;
342
343 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
344 if (!res) {
345 ret = -ENXIO;
346 goto exit_free;
347 }
348
349 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
350 ret = -EBUSY;
351 goto exit_free;
352 }
353
354 mmio = ioremap(res->start, resource_size(res));
355 if (!mmio) {
356 ret = -ENXIO;
357 goto exit_release;
358 }
359 ep93xx_gpio->mmio_base = mmio;
360
361 /* Default all ports to GPIO */
362 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
363 EP93XX_SYSCON_DEVCFG_GONK |
364 EP93XX_SYSCON_DEVCFG_EONIDE |
365 EP93XX_SYSCON_DEVCFG_GONIDE |
366 EP93XX_SYSCON_DEVCFG_HONIDE);
367
368 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
369 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
370 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
371
372 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
373 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
374 bank->label);
375 }
376
377 ep93xx_gpio_init_irq();
378
379 return 0;
380
381 exit_release:
382 release_mem_region(res->start, resource_size(res));
383 exit_free:
384 kfree(ep93xx_gpio);
385 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
386 return ret;
387 }
388
389 static struct platform_driver ep93xx_gpio_driver = {
390 .driver = {
391 .name = "gpio-ep93xx",
392 .owner = THIS_MODULE,
393 },
394 .probe = ep93xx_gpio_probe,
395 };
396
397 static int __init ep93xx_gpio_init(void)
398 {
399 return platform_driver_register(&ep93xx_gpio_driver);
400 }
401 postcore_initcall(ep93xx_gpio_init);
402
403 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
404 "H Hartley Sweeten <hsweeten@visionengravers.com>");
405 MODULE_DESCRIPTION("EP93XX GPIO driver");
406 MODULE_LICENSE("GPL");
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