?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / iommu / amd_iommu.c
bloba14f8dc23462229c8ba34d6aec18a14eb3fcaf7a
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/pci-ats.h>
22 #include <linux/bitmap.h>
23 #include <linux/slab.h>
24 #include <linux/debugfs.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/iommu-helper.h>
28 #include <linux/iommu.h>
29 #include <linux/delay.h>
30 #include <linux/amd-iommu.h>
31 #include <asm/msidef.h>
32 #include <asm/proto.h>
33 #include <asm/iommu.h>
34 #include <asm/gart.h>
35 #include <asm/dma.h>
36
37 #include "amd_iommu_proto.h"
38 #include "amd_iommu_types.h"
39
40 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
41
42 #define LOOP_TIMEOUT 100000
43
44 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
45
46 /* A list of preallocated protection domains */
47 static LIST_HEAD(iommu_pd_list);
48 static DEFINE_SPINLOCK(iommu_pd_list_lock);
49
50 /* List of all available dev_data structures */
51 static LIST_HEAD(dev_data_list);
52 static DEFINE_SPINLOCK(dev_data_list_lock);
53
54 /*
55 * Domain for untranslated devices - only allocated
56 * if iommu=pt passed on kernel cmd line.
57 */
58 static struct protection_domain *pt_domain;
59
60 static struct iommu_ops amd_iommu_ops;
61
62 /*
63 * general struct to manage commands send to an IOMMU
64 */
65 struct iommu_cmd {
66 u32 data[4];
67 };
68
69 static void update_domain(struct protection_domain *domain);
70
71 /****************************************************************************
72 *
73 * Helper functions
74 *
75 ****************************************************************************/
76
77 static struct iommu_dev_data *alloc_dev_data(u16 devid)
78 {
79 struct iommu_dev_data *dev_data;
80 unsigned long flags;
81
82 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
83 if (!dev_data)
84 return NULL;
85
86 dev_data->devid = devid;
87 atomic_set(&dev_data->bind, 0);
88
89 spin_lock_irqsave(&dev_data_list_lock, flags);
90 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
91 spin_unlock_irqrestore(&dev_data_list_lock, flags);
92
93 return dev_data;
94 }
95
96 static void free_dev_data(struct iommu_dev_data *dev_data)
97 {
98 unsigned long flags;
99
100 spin_lock_irqsave(&dev_data_list_lock, flags);
101 list_del(&dev_data->dev_data_list);
102 spin_unlock_irqrestore(&dev_data_list_lock, flags);
103
104 kfree(dev_data);
105 }
106
107 static struct iommu_dev_data *search_dev_data(u16 devid)
108 {
109 struct iommu_dev_data *dev_data;
110 unsigned long flags;
111
112 spin_lock_irqsave(&dev_data_list_lock, flags);
113 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
114 if (dev_data->devid == devid)
115 goto out_unlock;
116 }
117
118 dev_data = NULL;
119
120 out_unlock:
121 spin_unlock_irqrestore(&dev_data_list_lock, flags);
122
123 return dev_data;
124 }
125
126 static struct iommu_dev_data *find_dev_data(u16 devid)
127 {
128 struct iommu_dev_data *dev_data;
129
130 dev_data = search_dev_data(devid);
131
132 if (dev_data == NULL)
133 dev_data = alloc_dev_data(devid);
134
135 return dev_data;
136 }
137
138 static inline u16 get_device_id(struct device *dev)
139 {
140 struct pci_dev *pdev = to_pci_dev(dev);
141
142 return calc_devid(pdev->bus->number, pdev->devfn);
143 }
144
145 static struct iommu_dev_data *get_dev_data(struct device *dev)
146 {
147 return dev->archdata.iommu;
148 }
149
150 /*
151 * In this function the list of preallocated protection domains is traversed to
152 * find the domain for a specific device
153 */
154 static struct dma_ops_domain *find_protection_domain(u16 devid)
155 {
156 struct dma_ops_domain *entry, *ret = NULL;
157 unsigned long flags;
158 u16 alias = amd_iommu_alias_table[devid];
159
160 if (list_empty(&iommu_pd_list))
161 return NULL;
162
163 spin_lock_irqsave(&iommu_pd_list_lock, flags);
164
165 list_for_each_entry(entry, &iommu_pd_list, list) {
166 if (entry->target_dev == devid ||
167 entry->target_dev == alias) {
168 ret = entry;
169 break;
170 }
171 }
172
173 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
174
175 return ret;
176 }
177
178 /*
179 * This function checks if the driver got a valid device from the caller to
180 * avoid dereferencing invalid pointers.
181 */
182 static bool check_device(struct device *dev)
183 {
184 u16 devid;
185
186 if (!dev || !dev->dma_mask)
187 return false;
188
189 /* No device or no PCI device */
190 if (dev->bus != &pci_bus_type)
191 return false;
192
193 devid = get_device_id(dev);
194
195 /* Out of our scope? */
196 if (devid > amd_iommu_last_bdf)
197 return false;
198
199 if (amd_iommu_rlookup_table[devid] == NULL)
200 return false;
201
202 return true;
203 }
204
205 static int iommu_init_device(struct device *dev)
206 {
207 struct iommu_dev_data *dev_data;
208 u16 alias;
209
210 if (dev->archdata.iommu)
211 return 0;
212
213 dev_data = find_dev_data(get_device_id(dev));
214 if (!dev_data)
215 return -ENOMEM;
216
217 alias = amd_iommu_alias_table[dev_data->devid];
218 if (alias != dev_data->devid) {
219 struct iommu_dev_data *alias_data;
220
221 alias_data = find_dev_data(alias);
222 if (alias_data == NULL) {
223 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
224 dev_name(dev));
225 free_dev_data(dev_data);
226 return -ENOTSUPP;
227 }
228 dev_data->alias_data = alias_data;
229 }
230
231 dev->archdata.iommu = dev_data;
232
233 return 0;
234 }
235
236 static void iommu_ignore_device(struct device *dev)
237 {
238 u16 devid, alias;
239
240 devid = get_device_id(dev);
241 alias = amd_iommu_alias_table[devid];
242
243 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
244 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
245
246 amd_iommu_rlookup_table[devid] = NULL;
247 amd_iommu_rlookup_table[alias] = NULL;
248 }
249
250 static void iommu_uninit_device(struct device *dev)
251 {
252 /*
253 * Nothing to do here - we keep dev_data around for unplugged devices
254 * and reuse it when the device is re-plugged - not doing so would
255 * introduce a ton of races.
256 */
257 }
258
259 void __init amd_iommu_uninit_devices(void)
260 {
261 struct iommu_dev_data *dev_data, *n;
262 struct pci_dev *pdev = NULL;
263
264 for_each_pci_dev(pdev) {
265
266 if (!check_device(&pdev->dev))
267 continue;
268
269 iommu_uninit_device(&pdev->dev);
270 }
271
272 /* Free all of our dev_data structures */
273 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
274 free_dev_data(dev_data);
275 }
276
277 int __init amd_iommu_init_devices(void)
278 {
279 struct pci_dev *pdev = NULL;
280 int ret = 0;
281
282 for_each_pci_dev(pdev) {
283
284 if (!check_device(&pdev->dev))
285 continue;
286
287 ret = iommu_init_device(&pdev->dev);
288 if (ret == -ENOTSUPP)
289 iommu_ignore_device(&pdev->dev);
290 else if (ret)
291 goto out_free;
292 }
293
294 return 0;
295
296 out_free:
297
298 amd_iommu_uninit_devices();
299
300 return ret;
301 }
302 #ifdef CONFIG_AMD_IOMMU_STATS
303
304 /*
305 * Initialization code for statistics collection
306 */
307
308 DECLARE_STATS_COUNTER(compl_wait);
309 DECLARE_STATS_COUNTER(cnt_map_single);
310 DECLARE_STATS_COUNTER(cnt_unmap_single);
311 DECLARE_STATS_COUNTER(cnt_map_sg);
312 DECLARE_STATS_COUNTER(cnt_unmap_sg);
313 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
314 DECLARE_STATS_COUNTER(cnt_free_coherent);
315 DECLARE_STATS_COUNTER(cross_page);
316 DECLARE_STATS_COUNTER(domain_flush_single);
317 DECLARE_STATS_COUNTER(domain_flush_all);
318 DECLARE_STATS_COUNTER(alloced_io_mem);
319 DECLARE_STATS_COUNTER(total_map_requests);
320
321 static struct dentry *stats_dir;
322 static struct dentry *de_fflush;
323
324 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
325 {
326 if (stats_dir == NULL)
327 return;
328
329 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
330 &cnt->value);
331 }
332
333 static void amd_iommu_stats_init(void)
334 {
335 stats_dir = debugfs_create_dir("amd-iommu", NULL);
336 if (stats_dir == NULL)
337 return;
338
339 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
340 (u32 *)&amd_iommu_unmap_flush);
341
342 amd_iommu_stats_add(&compl_wait);
343 amd_iommu_stats_add(&cnt_map_single);
344 amd_iommu_stats_add(&cnt_unmap_single);
345 amd_iommu_stats_add(&cnt_map_sg);
346 amd_iommu_stats_add(&cnt_unmap_sg);
347 amd_iommu_stats_add(&cnt_alloc_coherent);
348 amd_iommu_stats_add(&cnt_free_coherent);
349 amd_iommu_stats_add(&cross_page);
350 amd_iommu_stats_add(&domain_flush_single);
351 amd_iommu_stats_add(&domain_flush_all);
352 amd_iommu_stats_add(&alloced_io_mem);
353 amd_iommu_stats_add(&total_map_requests);
354 }
355
356 #endif
357
358 /****************************************************************************
359 *
360 * Interrupt handling functions
361 *
362 ****************************************************************************/
363
364 static void dump_dte_entry(u16 devid)
365 {
366 int i;
367
368 for (i = 0; i < 8; ++i)
369 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
370 amd_iommu_dev_table[devid].data[i]);
371 }
372
373 static void dump_command(unsigned long phys_addr)
374 {
375 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
376 int i;
377
378 for (i = 0; i < 4; ++i)
379 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
380 }
381
382 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
383 {
384 u32 *event = __evt;
385 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
386 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
387 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
388 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
389 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
390
391 printk(KERN_ERR "AMD-Vi: Event logged [");
392
393 switch (type) {
394 case EVENT_TYPE_ILL_DEV:
395 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
396 "address=0x%016llx flags=0x%04x]\n",
397 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
398 address, flags);
399 dump_dte_entry(devid);
400 break;
401 case EVENT_TYPE_IO_FAULT:
402 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
403 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
404 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
405 domid, address, flags);
406 break;
407 case EVENT_TYPE_DEV_TAB_ERR:
408 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
409 "address=0x%016llx flags=0x%04x]\n",
410 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
411 address, flags);
412 break;
413 case EVENT_TYPE_PAGE_TAB_ERR:
414 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
415 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
416 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
417 domid, address, flags);
418 break;
419 case EVENT_TYPE_ILL_CMD:
420 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
421 dump_command(address);
422 break;
423 case EVENT_TYPE_CMD_HARD_ERR:
424 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
425 "flags=0x%04x]\n", address, flags);
426 break;
427 case EVENT_TYPE_IOTLB_INV_TO:
428 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
429 "address=0x%016llx]\n",
430 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
431 address);
432 break;
433 case EVENT_TYPE_INV_DEV_REQ:
434 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
435 "address=0x%016llx flags=0x%04x]\n",
436 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
437 address, flags);
438 break;
439 default:
440 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
441 }
442 }
443
444 static void iommu_poll_events(struct amd_iommu *iommu)
445 {
446 u32 head, tail;
447 unsigned long flags;
448
449 spin_lock_irqsave(&iommu->lock, flags);
450
451 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
452 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
453
454 while (head != tail) {
455 iommu_print_event(iommu, iommu->evt_buf + head);
456 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
457 }
458
459 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
460
461 spin_unlock_irqrestore(&iommu->lock, flags);
462 }
463
464 irqreturn_t amd_iommu_int_thread(int irq, void *data)
465 {
466 struct amd_iommu *iommu;
467
468 for_each_iommu(iommu)
469 iommu_poll_events(iommu);
470
471 return IRQ_HANDLED;
472 }
473
474 irqreturn_t amd_iommu_int_handler(int irq, void *data)
475 {
476 return IRQ_WAKE_THREAD;
477 }
478
479 /****************************************************************************
480 *
481 * IOMMU command queuing functions
482 *
483 ****************************************************************************/
484
485 static int wait_on_sem(volatile u64 *sem)
486 {
487 int i = 0;
488
489 while (*sem == 0 && i < LOOP_TIMEOUT) {
490 udelay(1);
491 i += 1;
492 }
493
494 if (i == LOOP_TIMEOUT) {
495 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
496 return -EIO;
497 }
498
499 return 0;
500 }
501
502 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
503 struct iommu_cmd *cmd,
504 u32 tail)
505 {
506 u8 *target;
507
508 target = iommu->cmd_buf + tail;
509 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
510
511 /* Copy command to buffer */
512 memcpy(target, cmd, sizeof(*cmd));
513
514 /* Tell the IOMMU about it */
515 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
516 }
517
518 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
519 {
520 WARN_ON(address & 0x7ULL);
521
522 memset(cmd, 0, sizeof(*cmd));
523 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
524 cmd->data[1] = upper_32_bits(__pa(address));
525 cmd->data[2] = 1;
526 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
527 }
528
529 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
530 {
531 memset(cmd, 0, sizeof(*cmd));
532 cmd->data[0] = devid;
533 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
534 }
535
536 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
537 size_t size, u16 domid, int pde)
538 {
539 u64 pages;
540 int s;
541
542 pages = iommu_num_pages(address, size, PAGE_SIZE);
543 s = 0;
544
545 if (pages > 1) {
546 /*
547 * If we have to flush more than one page, flush all
548 * TLB entries for this domain
549 */
550 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
551 s = 1;
552 }
553
554 address &= PAGE_MASK;
555
556 memset(cmd, 0, sizeof(*cmd));
557 cmd->data[1] |= domid;
558 cmd->data[2] = lower_32_bits(address);
559 cmd->data[3] = upper_32_bits(address);
560 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
561 if (s) /* size bit - we flush more than one 4kb page */
562 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
563 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
564 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
565 }
566
567 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
568 u64 address, size_t size)
569 {
570 u64 pages;
571 int s;
572
573 pages = iommu_num_pages(address, size, PAGE_SIZE);
574 s = 0;
575
576 if (pages > 1) {
577 /*
578 * If we have to flush more than one page, flush all
579 * TLB entries for this domain
580 */
581 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
582 s = 1;
583 }
584
585 address &= PAGE_MASK;
586
587 memset(cmd, 0, sizeof(*cmd));
588 cmd->data[0] = devid;
589 cmd->data[0] |= (qdep & 0xff) << 24;
590 cmd->data[1] = devid;
591 cmd->data[2] = lower_32_bits(address);
592 cmd->data[3] = upper_32_bits(address);
593 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
594 if (s)
595 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
596 }
597
598 static void build_inv_all(struct iommu_cmd *cmd)
599 {
600 memset(cmd, 0, sizeof(*cmd));
601 CMD_SET_TYPE(cmd, CMD_INV_ALL);
602 }
603
604 /*
605 * Writes the command to the IOMMUs command buffer and informs the
606 * hardware about the new command.
607 */
608 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
609 {
610 u32 left, tail, head, next_tail;
611 unsigned long flags;
612
613 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
614
615 again:
616 spin_lock_irqsave(&iommu->lock, flags);
617
618 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
619 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
620 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
621 left = (head - next_tail) % iommu->cmd_buf_size;
622
623 if (left <= 2) {
624 struct iommu_cmd sync_cmd;
625 volatile u64 sem = 0;
626 int ret;
627
628 build_completion_wait(&sync_cmd, (u64)&sem);
629 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
630
631 spin_unlock_irqrestore(&iommu->lock, flags);
632
633 if ((ret = wait_on_sem(&sem)) != 0)
634 return ret;
635
636 goto again;
637 }
638
639 copy_cmd_to_buffer(iommu, cmd, tail);
640
641 /* We need to sync now to make sure all commands are processed */
642 iommu->need_sync = true;
643
644 spin_unlock_irqrestore(&iommu->lock, flags);
645
646 return 0;
647 }
648
649 /*
650 * This function queues a completion wait command into the command
651 * buffer of an IOMMU
652 */
653 static int iommu_completion_wait(struct amd_iommu *iommu)
654 {
655 struct iommu_cmd cmd;
656 volatile u64 sem = 0;
657 int ret;
658
659 if (!iommu->need_sync)
660 return 0;
661
662 build_completion_wait(&cmd, (u64)&sem);
663
664 ret = iommu_queue_command(iommu, &cmd);
665 if (ret)
666 return ret;
667
668 return wait_on_sem(&sem);
669 }
670
671 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
672 {
673 struct iommu_cmd cmd;
674
675 build_inv_dte(&cmd, devid);
676
677 return iommu_queue_command(iommu, &cmd);
678 }
679
680 static void iommu_flush_dte_all(struct amd_iommu *iommu)
681 {
682 u32 devid;
683
684 for (devid = 0; devid <= 0xffff; ++devid)
685 iommu_flush_dte(iommu, devid);
686
687 iommu_completion_wait(iommu);
688 }
689
690 /*
691 * This function uses heavy locking and may disable irqs for some time. But
692 * this is no issue because it is only called during resume.
693 */
694 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
695 {
696 u32 dom_id;
697
698 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
699 struct iommu_cmd cmd;
700 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
701 dom_id, 1);
702 iommu_queue_command(iommu, &cmd);
703 }
704
705 iommu_completion_wait(iommu);
706 }
707
708 static void iommu_flush_all(struct amd_iommu *iommu)
709 {
710 struct iommu_cmd cmd;
711
712 build_inv_all(&cmd);
713
714 iommu_queue_command(iommu, &cmd);
715 iommu_completion_wait(iommu);
716 }
717
718 void iommu_flush_all_caches(struct amd_iommu *iommu)
719 {
720 if (iommu_feature(iommu, FEATURE_IA)) {
721 iommu_flush_all(iommu);
722 } else {
723 iommu_flush_dte_all(iommu);
724 iommu_flush_tlb_all(iommu);
725 }
726 }
727
728 /*
729 * Command send function for flushing on-device TLB
730 */
731 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
732 u64 address, size_t size)
733 {
734 struct amd_iommu *iommu;
735 struct iommu_cmd cmd;
736 int qdep;
737
738 qdep = dev_data->ats.qdep;
739 iommu = amd_iommu_rlookup_table[dev_data->devid];
740
741 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
742
743 return iommu_queue_command(iommu, &cmd);
744 }
745
746 /*
747 * Command send function for invalidating a device table entry
748 */
749 static int device_flush_dte(struct iommu_dev_data *dev_data)
750 {
751 struct amd_iommu *iommu;
752 int ret;
753
754 iommu = amd_iommu_rlookup_table[dev_data->devid];
755
756 ret = iommu_flush_dte(iommu, dev_data->devid);
757 if (ret)
758 return ret;
759
760 if (dev_data->ats.enabled)
761 ret = device_flush_iotlb(dev_data, 0, ~0UL);
762
763 return ret;
764 }
765
766 /*
767 * TLB invalidation function which is called from the mapping functions.
768 * It invalidates a single PTE if the range to flush is within a single
769 * page. Otherwise it flushes the whole TLB of the IOMMU.
770 */
771 static void __domain_flush_pages(struct protection_domain *domain,
772 u64 address, size_t size, int pde)
773 {
774 struct iommu_dev_data *dev_data;
775 struct iommu_cmd cmd;
776 int ret = 0, i;
777
778 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
779
780 for (i = 0; i < amd_iommus_present; ++i) {
781 if (!domain->dev_iommu[i])
782 continue;
783
784 /*
785 * Devices of this domain are behind this IOMMU
786 * We need a TLB flush
787 */
788 ret |= iommu_queue_command(amd_iommus[i], &cmd);
789 }
790
791 list_for_each_entry(dev_data, &domain->dev_list, list) {
792
793 if (!dev_data->ats.enabled)
794 continue;
795
796 ret |= device_flush_iotlb(dev_data, address, size);
797 }
798
799 WARN_ON(ret);
800 }
801
802 static void domain_flush_pages(struct protection_domain *domain,
803 u64 address, size_t size)
804 {
805 __domain_flush_pages(domain, address, size, 0);
806 }
807
808 /* Flush the whole IO/TLB for a given protection domain */
809 static void domain_flush_tlb(struct protection_domain *domain)
810 {
811 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
812 }
813
814 /* Flush the whole IO/TLB for a given protection domain - including PDE */
815 static void domain_flush_tlb_pde(struct protection_domain *domain)
816 {
817 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
818 }
819
820 static void domain_flush_complete(struct protection_domain *domain)
821 {
822 int i;
823
824 for (i = 0; i < amd_iommus_present; ++i) {
825 if (!domain->dev_iommu[i])
826 continue;
827
828 /*
829 * Devices of this domain are behind this IOMMU
830 * We need to wait for completion of all commands.
831 */
832 iommu_completion_wait(amd_iommus[i]);
833 }
834 }
835
836
837 /*
838 * This function flushes the DTEs for all devices in domain
839 */
840 static void domain_flush_devices(struct protection_domain *domain)
841 {
842 struct iommu_dev_data *dev_data;
843 unsigned long flags;
844
845 spin_lock_irqsave(&domain->lock, flags);
846
847 list_for_each_entry(dev_data, &domain->dev_list, list)
848 device_flush_dte(dev_data);
849
850 spin_unlock_irqrestore(&domain->lock, flags);
851 }
852
853 /****************************************************************************
854 *
855 * The functions below are used the create the page table mappings for
856 * unity mapped regions.
857 *
858 ****************************************************************************/
859
860 /*
861 * This function is used to add another level to an IO page table. Adding
862 * another level increases the size of the address space by 9 bits to a size up
863 * to 64 bits.
864 */
865 static bool increase_address_space(struct protection_domain *domain,
866 gfp_t gfp)
867 {
868 u64 *pte;
869
870 if (domain->mode == PAGE_MODE_6_LEVEL)
871 /* address space already 64 bit large */
872 return false;
873
874 pte = (void *)get_zeroed_page(gfp);
875 if (!pte)
876 return false;
877
878 *pte = PM_LEVEL_PDE(domain->mode,
879 virt_to_phys(domain->pt_root));
880 domain->pt_root = pte;
881 domain->mode += 1;
882 domain->updated = true;
883
884 return true;
885 }
886
887 static u64 *alloc_pte(struct protection_domain *domain,
888 unsigned long address,
889 unsigned long page_size,
890 u64 **pte_page,
891 gfp_t gfp)
892 {
893 int level, end_lvl;
894 u64 *pte, *page;
895
896 BUG_ON(!is_power_of_2(page_size));
897
898 while (address > PM_LEVEL_SIZE(domain->mode))
899 increase_address_space(domain, gfp);
900
901 level = domain->mode - 1;
902 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
903 address = PAGE_SIZE_ALIGN(address, page_size);
904 end_lvl = PAGE_SIZE_LEVEL(page_size);
905
906 while (level > end_lvl) {
907 if (!IOMMU_PTE_PRESENT(*pte)) {
908 page = (u64 *)get_zeroed_page(gfp);
909 if (!page)
910 return NULL;
911 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
912 }
913
914 /* No level skipping support yet */
915 if (PM_PTE_LEVEL(*pte) != level)
916 return NULL;
917
918 level -= 1;
919
920 pte = IOMMU_PTE_PAGE(*pte);
921
922 if (pte_page && level == end_lvl)
923 *pte_page = pte;
924
925 pte = &pte[PM_LEVEL_INDEX(level, address)];
926 }
927
928 return pte;
929 }
930
931 /*
932 * This function checks if there is a PTE for a given dma address. If
933 * there is one, it returns the pointer to it.
934 */
935 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
936 {
937 int level;
938 u64 *pte;
939
940 if (address > PM_LEVEL_SIZE(domain->mode))
941 return NULL;
942
943 level = domain->mode - 1;
944 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
945
946 while (level > 0) {
947
948 /* Not Present */
949 if (!IOMMU_PTE_PRESENT(*pte))
950 return NULL;
951
952 /* Large PTE */
953 if (PM_PTE_LEVEL(*pte) == 0x07) {
954 unsigned long pte_mask, __pte;
955
956 /*
957 * If we have a series of large PTEs, make
958 * sure to return a pointer to the first one.
959 */
960 pte_mask = PTE_PAGE_SIZE(*pte);
961 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
962 __pte = ((unsigned long)pte) & pte_mask;
963
964 return (u64 *)__pte;
965 }
966
967 /* No level skipping support yet */
968 if (PM_PTE_LEVEL(*pte) != level)
969 return NULL;
970
971 level -= 1;
972
973 /* Walk to the next level */
974 pte = IOMMU_PTE_PAGE(*pte);
975 pte = &pte[PM_LEVEL_INDEX(level, address)];
976 }
977
978 return pte;
979 }
980
981 /*
982 * Generic mapping functions. It maps a physical address into a DMA
983 * address space. It allocates the page table pages if necessary.
984 * In the future it can be extended to a generic mapping function
985 * supporting all features of AMD IOMMU page tables like level skipping
986 * and full 64 bit address spaces.
987 */
988 static int iommu_map_page(struct protection_domain *dom,
989 unsigned long bus_addr,
990 unsigned long phys_addr,
991 int prot,
992 unsigned long page_size)
993 {
994 u64 __pte, *pte;
995 int i, count;
996
997 if (!(prot & IOMMU_PROT_MASK))
998 return -EINVAL;
999
1000 bus_addr = PAGE_ALIGN(bus_addr);
1001 phys_addr = PAGE_ALIGN(phys_addr);
1002 count = PAGE_SIZE_PTE_COUNT(page_size);
1003 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1004
1005 for (i = 0; i < count; ++i)
1006 if (IOMMU_PTE_PRESENT(pte[i]))
1007 return -EBUSY;
1008
1009 if (page_size > PAGE_SIZE) {
1010 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1011 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1012 } else
1013 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1014
1015 if (prot & IOMMU_PROT_IR)
1016 __pte |= IOMMU_PTE_IR;
1017 if (prot & IOMMU_PROT_IW)
1018 __pte |= IOMMU_PTE_IW;
1019
1020 for (i = 0; i < count; ++i)
1021 pte[i] = __pte;
1022
1023 update_domain(dom);
1024
1025 return 0;
1026 }
1027
1028 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1029 unsigned long bus_addr,
1030 unsigned long page_size)
1031 {
1032 unsigned long long unmap_size, unmapped;
1033 u64 *pte;
1034
1035 BUG_ON(!is_power_of_2(page_size));
1036
1037 unmapped = 0;
1038
1039 while (unmapped < page_size) {
1040
1041 pte = fetch_pte(dom, bus_addr);
1042
1043 if (!pte) {
1044 /*
1045 * No PTE for this address
1046 * move forward in 4kb steps
1047 */
1048 unmap_size = PAGE_SIZE;
1049 } else if (PM_PTE_LEVEL(*pte) == 0) {
1050 /* 4kb PTE found for this address */
1051 unmap_size = PAGE_SIZE;
1052 *pte = 0ULL;
1053 } else {
1054 int count, i;
1055
1056 /* Large PTE found which maps this address */
1057 unmap_size = PTE_PAGE_SIZE(*pte);
1058 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1059 for (i = 0; i < count; i++)
1060 pte[i] = 0ULL;
1061 }
1062
1063 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1064 unmapped += unmap_size;
1065 }
1066
1067 BUG_ON(!is_power_of_2(unmapped));
1068
1069 return unmapped;
1070 }
1071
1072 /*
1073 * This function checks if a specific unity mapping entry is needed for
1074 * this specific IOMMU.
1075 */
1076 static int iommu_for_unity_map(struct amd_iommu *iommu,
1077 struct unity_map_entry *entry)
1078 {
1079 u16 bdf, i;
1080
1081 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1082 bdf = amd_iommu_alias_table[i];
1083 if (amd_iommu_rlookup_table[bdf] == iommu)
1084 return 1;
1085 }
1086
1087 return 0;
1088 }
1089
1090 /*
1091 * This function actually applies the mapping to the page table of the
1092 * dma_ops domain.
1093 */
1094 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1095 struct unity_map_entry *e)
1096 {
1097 u64 addr;
1098 int ret;
1099
1100 for (addr = e->address_start; addr < e->address_end;
1101 addr += PAGE_SIZE) {
1102 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1103 PAGE_SIZE);
1104 if (ret)
1105 return ret;
1106 /*
1107 * if unity mapping is in aperture range mark the page
1108 * as allocated in the aperture
1109 */
1110 if (addr < dma_dom->aperture_size)
1111 __set_bit(addr >> PAGE_SHIFT,
1112 dma_dom->aperture[0]->bitmap);
1113 }
1114
1115 return 0;
1116 }
1117
1118 /*
1119 * Init the unity mappings for a specific IOMMU in the system
1120 *
1121 * Basically iterates over all unity mapping entries and applies them to
1122 * the default domain DMA of that IOMMU if necessary.
1123 */
1124 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1125 {
1126 struct unity_map_entry *entry;
1127 int ret;
1128
1129 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1130 if (!iommu_for_unity_map(iommu, entry))
1131 continue;
1132 ret = dma_ops_unity_map(iommu->default_dom, entry);
1133 if (ret)
1134 return ret;
1135 }
1136
1137 return 0;
1138 }
1139
1140 /*
1141 * Inits the unity mappings required for a specific device
1142 */
1143 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1144 u16 devid)
1145 {
1146 struct unity_map_entry *e;
1147 int ret;
1148
1149 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1150 if (!(devid >= e->devid_start && devid <= e->devid_end))
1151 continue;
1152 ret = dma_ops_unity_map(dma_dom, e);
1153 if (ret)
1154 return ret;
1155 }
1156
1157 return 0;
1158 }
1159
1160 /****************************************************************************
1161 *
1162 * The next functions belong to the address allocator for the dma_ops
1163 * interface functions. They work like the allocators in the other IOMMU
1164 * drivers. Its basically a bitmap which marks the allocated pages in
1165 * the aperture. Maybe it could be enhanced in the future to a more
1166 * efficient allocator.
1167 *
1168 ****************************************************************************/
1169
1170 /*
1171 * The address allocator core functions.
1172 *
1173 * called with domain->lock held
1174 */
1175
1176 /*
1177 * Used to reserve address ranges in the aperture (e.g. for exclusion
1178 * ranges.
1179 */
1180 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1181 unsigned long start_page,
1182 unsigned int pages)
1183 {
1184 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1185
1186 if (start_page + pages > last_page)
1187 pages = last_page - start_page;
1188
1189 for (i = start_page; i < start_page + pages; ++i) {
1190 int index = i / APERTURE_RANGE_PAGES;
1191 int page = i % APERTURE_RANGE_PAGES;
1192 __set_bit(page, dom->aperture[index]->bitmap);
1193 }
1194 }
1195
1196 /*
1197 * This function is used to add a new aperture range to an existing
1198 * aperture in case of dma_ops domain allocation or address allocation
1199 * failure.
1200 */
1201 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1202 bool populate, gfp_t gfp)
1203 {
1204 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1205 struct amd_iommu *iommu;
1206 unsigned long i, old_size;
1207
1208 #ifdef CONFIG_IOMMU_STRESS
1209 populate = false;
1210 #endif
1211
1212 if (index >= APERTURE_MAX_RANGES)
1213 return -ENOMEM;
1214
1215 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1216 if (!dma_dom->aperture[index])
1217 return -ENOMEM;
1218
1219 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1220 if (!dma_dom->aperture[index]->bitmap)
1221 goto out_free;
1222
1223 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1224
1225 if (populate) {
1226 unsigned long address = dma_dom->aperture_size;
1227 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1228 u64 *pte, *pte_page;
1229
1230 for (i = 0; i < num_ptes; ++i) {
1231 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1232 &pte_page, gfp);
1233 if (!pte)
1234 goto out_free;
1235
1236 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1237
1238 address += APERTURE_RANGE_SIZE / 64;
1239 }
1240 }
1241
1242 old_size = dma_dom->aperture_size;
1243 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1244
1245 /* Reserve address range used for MSI messages */
1246 if (old_size < MSI_ADDR_BASE_LO &&
1247 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1248 unsigned long spage;
1249 int pages;
1250
1251 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1252 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1253
1254 dma_ops_reserve_addresses(dma_dom, spage, pages);
1255 }
1256
1257 /* Initialize the exclusion range if necessary */
1258 for_each_iommu(iommu) {
1259 if (iommu->exclusion_start &&
1260 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1261 && iommu->exclusion_start < dma_dom->aperture_size) {
1262 unsigned long startpage;
1263 int pages = iommu_num_pages(iommu->exclusion_start,
1264 iommu->exclusion_length,
1265 PAGE_SIZE);
1266 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1267 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1268 }
1269 }
1270
1271 /*
1272 * Check for areas already mapped as present in the new aperture
1273 * range and mark those pages as reserved in the allocator. Such
1274 * mappings may already exist as a result of requested unity
1275 * mappings for devices.
1276 */
1277 for (i = dma_dom->aperture[index]->offset;
1278 i < dma_dom->aperture_size;
1279 i += PAGE_SIZE) {
1280 u64 *pte = fetch_pte(&dma_dom->domain, i);
1281 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1282 continue;
1283
1284 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1285 }
1286
1287 update_domain(&dma_dom->domain);
1288
1289 return 0;
1290
1291 out_free:
1292 update_domain(&dma_dom->domain);
1293
1294 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1295
1296 kfree(dma_dom->aperture[index]);
1297 dma_dom->aperture[index] = NULL;
1298
1299 return -ENOMEM;
1300 }
1301
1302 static unsigned long dma_ops_area_alloc(struct device *dev,
1303 struct dma_ops_domain *dom,
1304 unsigned int pages,
1305 unsigned long align_mask,
1306 u64 dma_mask,
1307 unsigned long start)
1308 {
1309 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1310 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1311 int i = start >> APERTURE_RANGE_SHIFT;
1312 unsigned long boundary_size;
1313 unsigned long address = -1;
1314 unsigned long limit;
1315
1316 next_bit >>= PAGE_SHIFT;
1317
1318 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1319 PAGE_SIZE) >> PAGE_SHIFT;
1320
1321 for (;i < max_index; ++i) {
1322 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1323
1324 if (dom->aperture[i]->offset >= dma_mask)
1325 break;
1326
1327 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1328 dma_mask >> PAGE_SHIFT);
1329
1330 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1331 limit, next_bit, pages, 0,
1332 boundary_size, align_mask);
1333 if (address != -1) {
1334 address = dom->aperture[i]->offset +
1335 (address << PAGE_SHIFT);
1336 dom->next_address = address + (pages << PAGE_SHIFT);
1337 break;
1338 }
1339
1340 next_bit = 0;
1341 }
1342
1343 return address;
1344 }
1345
1346 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1347 struct dma_ops_domain *dom,
1348 unsigned int pages,
1349 unsigned long align_mask,
1350 u64 dma_mask)
1351 {
1352 unsigned long address;
1353
1354 #ifdef CONFIG_IOMMU_STRESS
1355 dom->next_address = 0;
1356 dom->need_flush = true;
1357 #endif
1358
1359 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1360 dma_mask, dom->next_address);
1361
1362 if (address == -1) {
1363 dom->next_address = 0;
1364 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1365 dma_mask, 0);
1366 dom->need_flush = true;
1367 }
1368
1369 if (unlikely(address == -1))
1370 address = DMA_ERROR_CODE;
1371
1372 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1373
1374 return address;
1375 }
1376
1377 /*
1378 * The address free function.
1379 *
1380 * called with domain->lock held
1381 */
1382 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1383 unsigned long address,
1384 unsigned int pages)
1385 {
1386 unsigned i = address >> APERTURE_RANGE_SHIFT;
1387 struct aperture_range *range = dom->aperture[i];
1388
1389 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1390
1391 #ifdef CONFIG_IOMMU_STRESS
1392 if (i < 4)
1393 return;
1394 #endif
1395
1396 if (address >= dom->next_address)
1397 dom->need_flush = true;
1398
1399 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1400
1401 bitmap_clear(range->bitmap, address, pages);
1402
1403 }
1404
1405 /****************************************************************************
1406 *
1407 * The next functions belong to the domain allocation. A domain is
1408 * allocated for every IOMMU as the default domain. If device isolation
1409 * is enabled, every device get its own domain. The most important thing
1410 * about domains is the page table mapping the DMA address space they
1411 * contain.
1412 *
1413 ****************************************************************************/
1414
1415 /*
1416 * This function adds a protection domain to the global protection domain list
1417 */
1418 static void add_domain_to_list(struct protection_domain *domain)
1419 {
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1423 list_add(&domain->list, &amd_iommu_pd_list);
1424 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1425 }
1426
1427 /*
1428 * This function removes a protection domain to the global
1429 * protection domain list
1430 */
1431 static void del_domain_from_list(struct protection_domain *domain)
1432 {
1433 unsigned long flags;
1434
1435 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1436 list_del(&domain->list);
1437 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1438 }
1439
1440 static u16 domain_id_alloc(void)
1441 {
1442 unsigned long flags;
1443 int id;
1444
1445 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1446 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1447 BUG_ON(id == 0);
1448 if (id > 0 && id < MAX_DOMAIN_ID)
1449 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1450 else
1451 id = 0;
1452 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1453
1454 return id;
1455 }
1456
1457 static void domain_id_free(int id)
1458 {
1459 unsigned long flags;
1460
1461 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1462 if (id > 0 && id < MAX_DOMAIN_ID)
1463 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1464 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1465 }
1466
1467 static void free_pagetable(struct protection_domain *domain)
1468 {
1469 int i, j;
1470 u64 *p1, *p2, *p3;
1471
1472 p1 = domain->pt_root;
1473
1474 if (!p1)
1475 return;
1476
1477 for (i = 0; i < 512; ++i) {
1478 if (!IOMMU_PTE_PRESENT(p1[i]))
1479 continue;
1480
1481 p2 = IOMMU_PTE_PAGE(p1[i]);
1482 for (j = 0; j < 512; ++j) {
1483 if (!IOMMU_PTE_PRESENT(p2[j]))
1484 continue;
1485 p3 = IOMMU_PTE_PAGE(p2[j]);
1486 free_page((unsigned long)p3);
1487 }
1488
1489 free_page((unsigned long)p2);
1490 }
1491
1492 free_page((unsigned long)p1);
1493
1494 domain->pt_root = NULL;
1495 }
1496
1497 /*
1498 * Free a domain, only used if something went wrong in the
1499 * allocation path and we need to free an already allocated page table
1500 */
1501 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1502 {
1503 int i;
1504
1505 if (!dom)
1506 return;
1507
1508 del_domain_from_list(&dom->domain);
1509
1510 free_pagetable(&dom->domain);
1511
1512 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1513 if (!dom->aperture[i])
1514 continue;
1515 free_page((unsigned long)dom->aperture[i]->bitmap);
1516 kfree(dom->aperture[i]);
1517 }
1518
1519 kfree(dom);
1520 }
1521
1522 /*
1523 * Allocates a new protection domain usable for the dma_ops functions.
1524 * It also initializes the page table and the address allocator data
1525 * structures required for the dma_ops interface
1526 */
1527 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1528 {
1529 struct dma_ops_domain *dma_dom;
1530
1531 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1532 if (!dma_dom)
1533 return NULL;
1534
1535 spin_lock_init(&dma_dom->domain.lock);
1536
1537 dma_dom->domain.id = domain_id_alloc();
1538 if (dma_dom->domain.id == 0)
1539 goto free_dma_dom;
1540 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1541 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1542 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1543 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1544 dma_dom->domain.priv = dma_dom;
1545 if (!dma_dom->domain.pt_root)
1546 goto free_dma_dom;
1547
1548 dma_dom->need_flush = false;
1549 dma_dom->target_dev = 0xffff;
1550
1551 add_domain_to_list(&dma_dom->domain);
1552
1553 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1554 goto free_dma_dom;
1555
1556 /*
1557 * mark the first page as allocated so we never return 0 as
1558 * a valid dma-address. So we can use 0 as error value
1559 */
1560 dma_dom->aperture[0]->bitmap[0] = 1;
1561 dma_dom->next_address = 0;
1562
1563
1564 return dma_dom;
1565
1566 free_dma_dom:
1567 dma_ops_domain_free(dma_dom);
1568
1569 return NULL;
1570 }
1571
1572 /*
1573 * little helper function to check whether a given protection domain is a
1574 * dma_ops domain
1575 */
1576 static bool dma_ops_domain(struct protection_domain *domain)
1577 {
1578 return domain->flags & PD_DMA_OPS_MASK;
1579 }
1580
1581 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1582 {
1583 u64 pte_root = virt_to_phys(domain->pt_root);
1584 u32 flags = 0;
1585
1586 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1587 << DEV_ENTRY_MODE_SHIFT;
1588 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1589
1590 if (ats)
1591 flags |= DTE_FLAG_IOTLB;
1592
1593 amd_iommu_dev_table[devid].data[3] |= flags;
1594 amd_iommu_dev_table[devid].data[2] = domain->id;
1595 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1596 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1597 }
1598
1599 static void clear_dte_entry(u16 devid)
1600 {
1601 /* remove entry from the device table seen by the hardware */
1602 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1603 amd_iommu_dev_table[devid].data[1] = 0;
1604 amd_iommu_dev_table[devid].data[2] = 0;
1605
1606 amd_iommu_apply_erratum_63(devid);
1607 }
1608
1609 static void do_attach(struct iommu_dev_data *dev_data,
1610 struct protection_domain *domain)
1611 {
1612 struct amd_iommu *iommu;
1613 bool ats;
1614
1615 iommu = amd_iommu_rlookup_table[dev_data->devid];
1616 ats = dev_data->ats.enabled;
1617
1618 /* Update data structures */
1619 dev_data->domain = domain;
1620 list_add(&dev_data->list, &domain->dev_list);
1621 set_dte_entry(dev_data->devid, domain, ats);
1622
1623 /* Do reference counting */
1624 domain->dev_iommu[iommu->index] += 1;
1625 domain->dev_cnt += 1;
1626
1627 /* Flush the DTE entry */
1628 device_flush_dte(dev_data);
1629 }
1630
1631 static void do_detach(struct iommu_dev_data *dev_data)
1632 {
1633 struct amd_iommu *iommu;
1634
1635 iommu = amd_iommu_rlookup_table[dev_data->devid];
1636
1637 /* decrease reference counters */
1638 dev_data->domain->dev_iommu[iommu->index] -= 1;
1639 dev_data->domain->dev_cnt -= 1;
1640
1641 /* Update data structures */
1642 dev_data->domain = NULL;
1643 list_del(&dev_data->list);
1644 clear_dte_entry(dev_data->devid);
1645
1646 /* Flush the DTE entry */
1647 device_flush_dte(dev_data);
1648 }
1649
1650 /*
1651 * If a device is not yet associated with a domain, this function does
1652 * assigns it visible for the hardware
1653 */
1654 static int __attach_device(struct iommu_dev_data *dev_data,
1655 struct protection_domain *domain)
1656 {
1657 int ret;
1658
1659 /* lock domain */
1660 spin_lock(&domain->lock);
1661
1662 if (dev_data->alias_data != NULL) {
1663 struct iommu_dev_data *alias_data = dev_data->alias_data;
1664
1665 /* Some sanity checks */
1666 ret = -EBUSY;
1667 if (alias_data->domain != NULL &&
1668 alias_data->domain != domain)
1669 goto out_unlock;
1670
1671 if (dev_data->domain != NULL &&
1672 dev_data->domain != domain)
1673 goto out_unlock;
1674
1675 /* Do real assignment */
1676 if (alias_data->domain == NULL)
1677 do_attach(alias_data, domain);
1678
1679 atomic_inc(&alias_data->bind);
1680 }
1681
1682 if (dev_data->domain == NULL)
1683 do_attach(dev_data, domain);
1684
1685 atomic_inc(&dev_data->bind);
1686
1687 ret = 0;
1688
1689 out_unlock:
1690
1691 /* ready */
1692 spin_unlock(&domain->lock);
1693
1694 return ret;
1695 }
1696
1697 /*
1698 * If a device is not yet associated with a domain, this function does
1699 * assigns it visible for the hardware
1700 */
1701 static int attach_device(struct device *dev,
1702 struct protection_domain *domain)
1703 {
1704 struct pci_dev *pdev = to_pci_dev(dev);
1705 struct iommu_dev_data *dev_data;
1706 unsigned long flags;
1707 int ret;
1708
1709 dev_data = get_dev_data(dev);
1710
1711 if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1712 dev_data->ats.enabled = true;
1713 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1714 }
1715
1716 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1717 ret = __attach_device(dev_data, domain);
1718 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1719
1720 /*
1721 * We might boot into a crash-kernel here. The crashed kernel
1722 * left the caches in the IOMMU dirty. So we have to flush
1723 * here to evict all dirty stuff.
1724 */
1725 domain_flush_tlb_pde(domain);
1726
1727 return ret;
1728 }
1729
1730 /*
1731 * Removes a device from a protection domain (unlocked)
1732 */
1733 static void __detach_device(struct iommu_dev_data *dev_data)
1734 {
1735 struct protection_domain *domain;
1736 unsigned long flags;
1737
1738 BUG_ON(!dev_data->domain);
1739
1740 domain = dev_data->domain;
1741
1742 spin_lock_irqsave(&domain->lock, flags);
1743
1744 if (dev_data->alias_data != NULL) {
1745 struct iommu_dev_data *alias_data = dev_data->alias_data;
1746
1747 if (atomic_dec_and_test(&alias_data->bind))
1748 do_detach(alias_data);
1749 }
1750
1751 if (atomic_dec_and_test(&dev_data->bind))
1752 do_detach(dev_data);
1753
1754 spin_unlock_irqrestore(&domain->lock, flags);
1755
1756 /*
1757 * If we run in passthrough mode the device must be assigned to the
1758 * passthrough domain if it is detached from any other domain.
1759 * Make sure we can deassign from the pt_domain itself.
1760 */
1761 if (iommu_pass_through &&
1762 (dev_data->domain == NULL && domain != pt_domain))
1763 __attach_device(dev_data, pt_domain);
1764 }
1765
1766 /*
1767 * Removes a device from a protection domain (with devtable_lock held)
1768 */
1769 static void detach_device(struct device *dev)
1770 {
1771 struct iommu_dev_data *dev_data;
1772 unsigned long flags;
1773
1774 dev_data = get_dev_data(dev);
1775
1776 /* lock device table */
1777 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1778 __detach_device(dev_data);
1779 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1780
1781 if (dev_data->ats.enabled) {
1782 pci_disable_ats(to_pci_dev(dev));
1783 dev_data->ats.enabled = false;
1784 }
1785 }
1786
1787 /*
1788 * Find out the protection domain structure for a given PCI device. This
1789 * will give us the pointer to the page table root for example.
1790 */
1791 static struct protection_domain *domain_for_device(struct device *dev)
1792 {
1793 struct iommu_dev_data *dev_data;
1794 struct protection_domain *dom = NULL;
1795 unsigned long flags;
1796
1797 dev_data = get_dev_data(dev);
1798
1799 if (dev_data->domain)
1800 return dev_data->domain;
1801
1802 if (dev_data->alias_data != NULL) {
1803 struct iommu_dev_data *alias_data = dev_data->alias_data;
1804
1805 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1806 if (alias_data->domain != NULL) {
1807 __attach_device(dev_data, alias_data->domain);
1808 dom = alias_data->domain;
1809 }
1810 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1811 }
1812
1813 return dom;
1814 }
1815
1816 static int device_change_notifier(struct notifier_block *nb,
1817 unsigned long action, void *data)
1818 {
1819 struct device *dev = data;
1820 u16 devid;
1821 struct protection_domain *domain;
1822 struct dma_ops_domain *dma_domain;
1823 struct amd_iommu *iommu;
1824 unsigned long flags;
1825
1826 if (!check_device(dev))
1827 return 0;
1828
1829 devid = get_device_id(dev);
1830 iommu = amd_iommu_rlookup_table[devid];
1831
1832 switch (action) {
1833 case BUS_NOTIFY_UNBOUND_DRIVER:
1834
1835 domain = domain_for_device(dev);
1836
1837 if (!domain)
1838 goto out;
1839 if (iommu_pass_through)
1840 break;
1841 detach_device(dev);
1842 break;
1843 case BUS_NOTIFY_ADD_DEVICE:
1844
1845 iommu_init_device(dev);
1846
1847 domain = domain_for_device(dev);
1848
1849 /* allocate a protection domain if a device is added */
1850 dma_domain = find_protection_domain(devid);
1851 if (dma_domain)
1852 goto out;
1853 dma_domain = dma_ops_domain_alloc();
1854 if (!dma_domain)
1855 goto out;
1856 dma_domain->target_dev = devid;
1857
1858 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1859 list_add_tail(&dma_domain->list, &iommu_pd_list);
1860 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1861
1862 break;
1863 case BUS_NOTIFY_DEL_DEVICE:
1864
1865 iommu_uninit_device(dev);
1866
1867 default:
1868 goto out;
1869 }
1870
1871 iommu_completion_wait(iommu);
1872
1873 out:
1874 return 0;
1875 }
1876
1877 static struct notifier_block device_nb = {
1878 .notifier_call = device_change_notifier,
1879 };
1880
1881 void amd_iommu_init_notifier(void)
1882 {
1883 bus_register_notifier(&pci_bus_type, &device_nb);
1884 }
1885
1886 /*****************************************************************************
1887 *
1888 * The next functions belong to the dma_ops mapping/unmapping code.
1889 *
1890 *****************************************************************************/
1891
1892 /*
1893 * In the dma_ops path we only have the struct device. This function
1894 * finds the corresponding IOMMU, the protection domain and the
1895 * requestor id for a given device.
1896 * If the device is not yet associated with a domain this is also done
1897 * in this function.
1898 */
1899 static struct protection_domain *get_domain(struct device *dev)
1900 {
1901 struct protection_domain *domain;
1902 struct dma_ops_domain *dma_dom;
1903 u16 devid = get_device_id(dev);
1904
1905 if (!check_device(dev))
1906 return ERR_PTR(-EINVAL);
1907
1908 domain = domain_for_device(dev);
1909 if (domain != NULL && !dma_ops_domain(domain))
1910 return ERR_PTR(-EBUSY);
1911
1912 if (domain != NULL)
1913 return domain;
1914
1915 /* Device not bount yet - bind it */
1916 dma_dom = find_protection_domain(devid);
1917 if (!dma_dom)
1918 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1919 attach_device(dev, &dma_dom->domain);
1920 DUMP_printk("Using protection domain %d for device %s\n",
1921 dma_dom->domain.id, dev_name(dev));
1922
1923 return &dma_dom->domain;
1924 }
1925
1926 static void update_device_table(struct protection_domain *domain)
1927 {
1928 struct iommu_dev_data *dev_data;
1929
1930 list_for_each_entry(dev_data, &domain->dev_list, list)
1931 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
1932 }
1933
1934 static void update_domain(struct protection_domain *domain)
1935 {
1936 if (!domain->updated)
1937 return;
1938
1939 update_device_table(domain);
1940
1941 domain_flush_devices(domain);
1942 domain_flush_tlb_pde(domain);
1943
1944 domain->updated = false;
1945 }
1946
1947 /*
1948 * This function fetches the PTE for a given address in the aperture
1949 */
1950 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1951 unsigned long address)
1952 {
1953 struct aperture_range *aperture;
1954 u64 *pte, *pte_page;
1955
1956 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1957 if (!aperture)
1958 return NULL;
1959
1960 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1961 if (!pte) {
1962 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1963 GFP_ATOMIC);
1964 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1965 } else
1966 pte += PM_LEVEL_INDEX(0, address);
1967
1968 update_domain(&dom->domain);
1969
1970 return pte;
1971 }
1972
1973 /*
1974 * This is the generic map function. It maps one 4kb page at paddr to
1975 * the given address in the DMA address space for the domain.
1976 */
1977 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1978 unsigned long address,
1979 phys_addr_t paddr,
1980 int direction)
1981 {
1982 u64 *pte, __pte;
1983
1984 WARN_ON(address > dom->aperture_size);
1985
1986 paddr &= PAGE_MASK;
1987
1988 pte = dma_ops_get_pte(dom, address);
1989 if (!pte)
1990 return DMA_ERROR_CODE;
1991
1992 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1993
1994 if (direction == DMA_TO_DEVICE)
1995 __pte |= IOMMU_PTE_IR;
1996 else if (direction == DMA_FROM_DEVICE)
1997 __pte |= IOMMU_PTE_IW;
1998 else if (direction == DMA_BIDIRECTIONAL)
1999 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2000
2001 WARN_ON(*pte);
2002
2003 *pte = __pte;
2004
2005 return (dma_addr_t)address;
2006 }
2007
2008 /*
2009 * The generic unmapping function for on page in the DMA address space.
2010 */
2011 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2012 unsigned long address)
2013 {
2014 struct aperture_range *aperture;
2015 u64 *pte;
2016
2017 if (address >= dom->aperture_size)
2018 return;
2019
2020 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2021 if (!aperture)
2022 return;
2023
2024 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2025 if (!pte)
2026 return;
2027
2028 pte += PM_LEVEL_INDEX(0, address);
2029
2030 WARN_ON(!*pte);
2031
2032 *pte = 0ULL;
2033 }
2034
2035 /*
2036 * This function contains common code for mapping of a physically
2037 * contiguous memory region into DMA address space. It is used by all
2038 * mapping functions provided with this IOMMU driver.
2039 * Must be called with the domain lock held.
2040 */
2041 static dma_addr_t __map_single(struct device *dev,
2042 struct dma_ops_domain *dma_dom,
2043 phys_addr_t paddr,
2044 size_t size,
2045 int dir,
2046 bool align,
2047 u64 dma_mask)
2048 {
2049 dma_addr_t offset = paddr & ~PAGE_MASK;
2050 dma_addr_t address, start, ret;
2051 unsigned int pages;
2052 unsigned long align_mask = 0;
2053 int i;
2054
2055 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2056 paddr &= PAGE_MASK;
2057
2058 INC_STATS_COUNTER(total_map_requests);
2059
2060 if (pages > 1)
2061 INC_STATS_COUNTER(cross_page);
2062
2063 if (align)
2064 align_mask = (1UL << get_order(size)) - 1;
2065
2066 retry:
2067 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2068 dma_mask);
2069 if (unlikely(address == DMA_ERROR_CODE)) {
2070 /*
2071 * setting next_address here will let the address
2072 * allocator only scan the new allocated range in the
2073 * first run. This is a small optimization.
2074 */
2075 dma_dom->next_address = dma_dom->aperture_size;
2076
2077 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2078 goto out;
2079
2080 /*
2081 * aperture was successfully enlarged by 128 MB, try
2082 * allocation again
2083 */
2084 goto retry;
2085 }
2086
2087 start = address;
2088 for (i = 0; i < pages; ++i) {
2089 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2090 if (ret == DMA_ERROR_CODE)
2091 goto out_unmap;
2092
2093 paddr += PAGE_SIZE;
2094 start += PAGE_SIZE;
2095 }
2096 address += offset;
2097
2098 ADD_STATS_COUNTER(alloced_io_mem, size);
2099
2100 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2101 domain_flush_tlb(&dma_dom->domain);
2102 dma_dom->need_flush = false;
2103 } else if (unlikely(amd_iommu_np_cache))
2104 domain_flush_pages(&dma_dom->domain, address, size);
2105
2106 out:
2107 return address;
2108
2109 out_unmap:
2110
2111 for (--i; i >= 0; --i) {
2112 start -= PAGE_SIZE;
2113 dma_ops_domain_unmap(dma_dom, start);
2114 }
2115
2116 dma_ops_free_addresses(dma_dom, address, pages);
2117
2118 return DMA_ERROR_CODE;
2119 }
2120
2121 /*
2122 * Does the reverse of the __map_single function. Must be called with
2123 * the domain lock held too
2124 */
2125 static void __unmap_single(struct dma_ops_domain *dma_dom,
2126 dma_addr_t dma_addr,
2127 size_t size,
2128 int dir)
2129 {
2130 dma_addr_t flush_addr;
2131 dma_addr_t i, start;
2132 unsigned int pages;
2133
2134 if ((dma_addr == DMA_ERROR_CODE) ||
2135 (dma_addr + size > dma_dom->aperture_size))
2136 return;
2137
2138 flush_addr = dma_addr;
2139 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2140 dma_addr &= PAGE_MASK;
2141 start = dma_addr;
2142
2143 for (i = 0; i < pages; ++i) {
2144 dma_ops_domain_unmap(dma_dom, start);
2145 start += PAGE_SIZE;
2146 }
2147
2148 SUB_STATS_COUNTER(alloced_io_mem, size);
2149
2150 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2151
2152 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2153 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2154 dma_dom->need_flush = false;
2155 }
2156 }
2157
2158 /*
2159 * The exported map_single function for dma_ops.
2160 */
2161 static dma_addr_t map_page(struct device *dev, struct page *page,
2162 unsigned long offset, size_t size,
2163 enum dma_data_direction dir,
2164 struct dma_attrs *attrs)
2165 {
2166 unsigned long flags;
2167 struct protection_domain *domain;
2168 dma_addr_t addr;
2169 u64 dma_mask;
2170 phys_addr_t paddr = page_to_phys(page) + offset;
2171
2172 INC_STATS_COUNTER(cnt_map_single);
2173
2174 domain = get_domain(dev);
2175 if (PTR_ERR(domain) == -EINVAL)
2176 return (dma_addr_t)paddr;
2177 else if (IS_ERR(domain))
2178 return DMA_ERROR_CODE;
2179
2180 dma_mask = *dev->dma_mask;
2181
2182 spin_lock_irqsave(&domain->lock, flags);
2183
2184 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2185 dma_mask);
2186 if (addr == DMA_ERROR_CODE)
2187 goto out;
2188
2189 domain_flush_complete(domain);
2190
2191 out:
2192 spin_unlock_irqrestore(&domain->lock, flags);
2193
2194 return addr;
2195 }
2196
2197 /*
2198 * The exported unmap_single function for dma_ops.
2199 */
2200 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2201 enum dma_data_direction dir, struct dma_attrs *attrs)
2202 {
2203 unsigned long flags;
2204 struct protection_domain *domain;
2205
2206 INC_STATS_COUNTER(cnt_unmap_single);
2207
2208 domain = get_domain(dev);
2209 if (IS_ERR(domain))
2210 return;
2211
2212 spin_lock_irqsave(&domain->lock, flags);
2213
2214 __unmap_single(domain->priv, dma_addr, size, dir);
2215
2216 domain_flush_complete(domain);
2217
2218 spin_unlock_irqrestore(&domain->lock, flags);
2219 }
2220
2221 /*
2222 * This is a special map_sg function which is used if we should map a
2223 * device which is not handled by an AMD IOMMU in the system.
2224 */
2225 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2226 int nelems, int dir)
2227 {
2228 struct scatterlist *s;
2229 int i;
2230
2231 for_each_sg(sglist, s, nelems, i) {
2232 s->dma_address = (dma_addr_t)sg_phys(s);
2233 s->dma_length = s->length;
2234 }
2235
2236 return nelems;
2237 }
2238
2239 /*
2240 * The exported map_sg function for dma_ops (handles scatter-gather
2241 * lists).
2242 */
2243 static int map_sg(struct device *dev, struct scatterlist *sglist,
2244 int nelems, enum dma_data_direction dir,
2245 struct dma_attrs *attrs)
2246 {
2247 unsigned long flags;
2248 struct protection_domain *domain;
2249 int i;
2250 struct scatterlist *s;
2251 phys_addr_t paddr;
2252 int mapped_elems = 0;
2253 u64 dma_mask;
2254
2255 INC_STATS_COUNTER(cnt_map_sg);
2256
2257 domain = get_domain(dev);
2258 if (PTR_ERR(domain) == -EINVAL)
2259 return map_sg_no_iommu(dev, sglist, nelems, dir);
2260 else if (IS_ERR(domain))
2261 return 0;
2262
2263 dma_mask = *dev->dma_mask;
2264
2265 spin_lock_irqsave(&domain->lock, flags);
2266
2267 for_each_sg(sglist, s, nelems, i) {
2268 paddr = sg_phys(s);
2269
2270 s->dma_address = __map_single(dev, domain->priv,
2271 paddr, s->length, dir, false,
2272 dma_mask);
2273
2274 if (s->dma_address) {
2275 s->dma_length = s->length;
2276 mapped_elems++;
2277 } else
2278 goto unmap;
2279 }
2280
2281 domain_flush_complete(domain);
2282
2283 out:
2284 spin_unlock_irqrestore(&domain->lock, flags);
2285
2286 return mapped_elems;
2287 unmap:
2288 for_each_sg(sglist, s, mapped_elems, i) {
2289 if (s->dma_address)
2290 __unmap_single(domain->priv, s->dma_address,
2291 s->dma_length, dir);
2292 s->dma_address = s->dma_length = 0;
2293 }
2294
2295 mapped_elems = 0;
2296
2297 goto out;
2298 }
2299
2300 /*
2301 * The exported map_sg function for dma_ops (handles scatter-gather
2302 * lists).
2303 */
2304 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2305 int nelems, enum dma_data_direction dir,
2306 struct dma_attrs *attrs)
2307 {
2308 unsigned long flags;
2309 struct protection_domain *domain;
2310 struct scatterlist *s;
2311 int i;
2312
2313 INC_STATS_COUNTER(cnt_unmap_sg);
2314
2315 domain = get_domain(dev);
2316 if (IS_ERR(domain))
2317 return;
2318
2319 spin_lock_irqsave(&domain->lock, flags);
2320
2321 for_each_sg(sglist, s, nelems, i) {
2322 __unmap_single(domain->priv, s->dma_address,
2323 s->dma_length, dir);
2324 s->dma_address = s->dma_length = 0;
2325 }
2326
2327 domain_flush_complete(domain);
2328
2329 spin_unlock_irqrestore(&domain->lock, flags);
2330 }
2331
2332 /*
2333 * The exported alloc_coherent function for dma_ops.
2334 */
2335 static void *alloc_coherent(struct device *dev, size_t size,
2336 dma_addr_t *dma_addr, gfp_t flag)
2337 {
2338 unsigned long flags;
2339 void *virt_addr;
2340 struct protection_domain *domain;
2341 phys_addr_t paddr;
2342 u64 dma_mask = dev->coherent_dma_mask;
2343
2344 INC_STATS_COUNTER(cnt_alloc_coherent);
2345
2346 domain = get_domain(dev);
2347 if (PTR_ERR(domain) == -EINVAL) {
2348 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2349 *dma_addr = __pa(virt_addr);
2350 return virt_addr;
2351 } else if (IS_ERR(domain))
2352 return NULL;
2353
2354 dma_mask = dev->coherent_dma_mask;
2355 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2356 flag |= __GFP_ZERO;
2357
2358 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2359 if (!virt_addr)
2360 return NULL;
2361
2362 paddr = virt_to_phys(virt_addr);
2363
2364 if (!dma_mask)
2365 dma_mask = *dev->dma_mask;
2366
2367 spin_lock_irqsave(&domain->lock, flags);
2368
2369 *dma_addr = __map_single(dev, domain->priv, paddr,
2370 size, DMA_BIDIRECTIONAL, true, dma_mask);
2371
2372 if (*dma_addr == DMA_ERROR_CODE) {
2373 spin_unlock_irqrestore(&domain->lock, flags);
2374 goto out_free;
2375 }
2376
2377 domain_flush_complete(domain);
2378
2379 spin_unlock_irqrestore(&domain->lock, flags);
2380
2381 return virt_addr;
2382
2383 out_free:
2384
2385 free_pages((unsigned long)virt_addr, get_order(size));
2386
2387 return NULL;
2388 }
2389
2390 /*
2391 * The exported free_coherent function for dma_ops.
2392 */
2393 static void free_coherent(struct device *dev, size_t size,
2394 void *virt_addr, dma_addr_t dma_addr)
2395 {
2396 unsigned long flags;
2397 struct protection_domain *domain;
2398
2399 INC_STATS_COUNTER(cnt_free_coherent);
2400
2401 domain = get_domain(dev);
2402 if (IS_ERR(domain))
2403 goto free_mem;
2404
2405 spin_lock_irqsave(&domain->lock, flags);
2406
2407 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2408
2409 domain_flush_complete(domain);
2410
2411 spin_unlock_irqrestore(&domain->lock, flags);
2412
2413 free_mem:
2414 free_pages((unsigned long)virt_addr, get_order(size));
2415 }
2416
2417 /*
2418 * This function is called by the DMA layer to find out if we can handle a
2419 * particular device. It is part of the dma_ops.
2420 */
2421 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2422 {
2423 return check_device(dev);
2424 }
2425
2426 /*
2427 * The function for pre-allocating protection domains.
2428 *
2429 * If the driver core informs the DMA layer if a driver grabs a device
2430 * we don't need to preallocate the protection domains anymore.
2431 * For now we have to.
2432 */
2433 static void prealloc_protection_domains(void)
2434 {
2435 struct pci_dev *dev = NULL;
2436 struct dma_ops_domain *dma_dom;
2437 u16 devid;
2438
2439 for_each_pci_dev(dev) {
2440
2441 /* Do we handle this device? */
2442 if (!check_device(&dev->dev))
2443 continue;
2444
2445 /* Is there already any domain for it? */
2446 if (domain_for_device(&dev->dev))
2447 continue;
2448
2449 devid = get_device_id(&dev->dev);
2450
2451 dma_dom = dma_ops_domain_alloc();
2452 if (!dma_dom)
2453 continue;
2454 init_unity_mappings_for_device(dma_dom, devid);
2455 dma_dom->target_dev = devid;
2456
2457 attach_device(&dev->dev, &dma_dom->domain);
2458
2459 list_add_tail(&dma_dom->list, &iommu_pd_list);
2460 }
2461 }
2462
2463 static struct dma_map_ops amd_iommu_dma_ops = {
2464 .alloc_coherent = alloc_coherent,
2465 .free_coherent = free_coherent,
2466 .map_page = map_page,
2467 .unmap_page = unmap_page,
2468 .map_sg = map_sg,
2469 .unmap_sg = unmap_sg,
2470 .dma_supported = amd_iommu_dma_supported,
2471 };
2472
2473 static unsigned device_dma_ops_init(void)
2474 {
2475 struct pci_dev *pdev = NULL;
2476 unsigned unhandled = 0;
2477
2478 for_each_pci_dev(pdev) {
2479 if (!check_device(&pdev->dev)) {
2480 unhandled += 1;
2481 continue;
2482 }
2483
2484 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2485 }
2486
2487 return unhandled;
2488 }
2489
2490 /*
2491 * The function which clues the AMD IOMMU driver into dma_ops.
2492 */
2493
2494 void __init amd_iommu_init_api(void)
2495 {
2496 register_iommu(&amd_iommu_ops);
2497 }
2498
2499 int __init amd_iommu_init_dma_ops(void)
2500 {
2501 struct amd_iommu *iommu;
2502 int ret, unhandled;
2503
2504 /*
2505 * first allocate a default protection domain for every IOMMU we
2506 * found in the system. Devices not assigned to any other
2507 * protection domain will be assigned to the default one.
2508 */
2509 for_each_iommu(iommu) {
2510 iommu->default_dom = dma_ops_domain_alloc();
2511 if (iommu->default_dom == NULL)
2512 return -ENOMEM;
2513 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2514 ret = iommu_init_unity_mappings(iommu);
2515 if (ret)
2516 goto free_domains;
2517 }
2518
2519 /*
2520 * Pre-allocate the protection domains for each device.
2521 */
2522 prealloc_protection_domains();
2523
2524 iommu_detected = 1;
2525 swiotlb = 0;
2526
2527 /* Make the driver finally visible to the drivers */
2528 unhandled = device_dma_ops_init();
2529 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2530 /* There are unhandled devices - initialize swiotlb for them */
2531 swiotlb = 1;
2532 }
2533
2534 amd_iommu_stats_init();
2535
2536 return 0;
2537
2538 free_domains:
2539
2540 for_each_iommu(iommu) {
2541 if (iommu->default_dom)
2542 dma_ops_domain_free(iommu->default_dom);
2543 }
2544
2545 return ret;
2546 }
2547
2548 /*****************************************************************************
2549 *
2550 * The following functions belong to the exported interface of AMD IOMMU
2551 *
2552 * This interface allows access to lower level functions of the IOMMU
2553 * like protection domain handling and assignement of devices to domains
2554 * which is not possible with the dma_ops interface.
2555 *
2556 *****************************************************************************/
2557
2558 static void cleanup_domain(struct protection_domain *domain)
2559 {
2560 struct iommu_dev_data *dev_data, *next;
2561 unsigned long flags;
2562
2563 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2564
2565 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2566 __detach_device(dev_data);
2567 atomic_set(&dev_data->bind, 0);
2568 }
2569
2570 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2571 }
2572
2573 static void protection_domain_free(struct protection_domain *domain)
2574 {
2575 if (!domain)
2576 return;
2577
2578 del_domain_from_list(domain);
2579
2580 if (domain->id)
2581 domain_id_free(domain->id);
2582
2583 kfree(domain);
2584 }
2585
2586 static struct protection_domain *protection_domain_alloc(void)
2587 {
2588 struct protection_domain *domain;
2589
2590 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2591 if (!domain)
2592 return NULL;
2593
2594 spin_lock_init(&domain->lock);
2595 mutex_init(&domain->api_lock);
2596 domain->id = domain_id_alloc();
2597 if (!domain->id)
2598 goto out_err;
2599 INIT_LIST_HEAD(&domain->dev_list);
2600
2601 add_domain_to_list(domain);
2602
2603 return domain;
2604
2605 out_err:
2606 kfree(domain);
2607
2608 return NULL;
2609 }
2610
2611 static int amd_iommu_domain_init(struct iommu_domain *dom)
2612 {
2613 struct protection_domain *domain;
2614
2615 domain = protection_domain_alloc();
2616 if (!domain)
2617 goto out_free;
2618
2619 domain->mode = PAGE_MODE_3_LEVEL;
2620 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2621 if (!domain->pt_root)
2622 goto out_free;
2623
2624 dom->priv = domain;
2625
2626 return 0;
2627
2628 out_free:
2629 protection_domain_free(domain);
2630
2631 return -ENOMEM;
2632 }
2633
2634 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2635 {
2636 struct protection_domain *domain = dom->priv;
2637
2638 if (!domain)
2639 return;
2640
2641 if (domain->dev_cnt > 0)
2642 cleanup_domain(domain);
2643
2644 BUG_ON(domain->dev_cnt != 0);
2645
2646 free_pagetable(domain);
2647
2648 protection_domain_free(domain);
2649
2650 dom->priv = NULL;
2651 }
2652
2653 static void amd_iommu_detach_device(struct iommu_domain *dom,
2654 struct device *dev)
2655 {
2656 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2657 struct amd_iommu *iommu;
2658 u16 devid;
2659
2660 if (!check_device(dev))
2661 return;
2662
2663 devid = get_device_id(dev);
2664
2665 if (dev_data->domain != NULL)
2666 detach_device(dev);
2667
2668 iommu = amd_iommu_rlookup_table[devid];
2669 if (!iommu)
2670 return;
2671
2672 iommu_completion_wait(iommu);
2673 }
2674
2675 static int amd_iommu_attach_device(struct iommu_domain *dom,
2676 struct device *dev)
2677 {
2678 struct protection_domain *domain = dom->priv;
2679 struct iommu_dev_data *dev_data;
2680 struct amd_iommu *iommu;
2681 int ret;
2682
2683 if (!check_device(dev))
2684 return -EINVAL;
2685
2686 dev_data = dev->archdata.iommu;
2687
2688 iommu = amd_iommu_rlookup_table[dev_data->devid];
2689 if (!iommu)
2690 return -EINVAL;
2691
2692 if (dev_data->domain)
2693 detach_device(dev);
2694
2695 ret = attach_device(dev, domain);
2696
2697 iommu_completion_wait(iommu);
2698
2699 return ret;
2700 }
2701
2702 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2703 phys_addr_t paddr, int gfp_order, int iommu_prot)
2704 {
2705 unsigned long page_size = 0x1000UL << gfp_order;
2706 struct protection_domain *domain = dom->priv;
2707 int prot = 0;
2708 int ret;
2709
2710 if (iommu_prot & IOMMU_READ)
2711 prot |= IOMMU_PROT_IR;
2712 if (iommu_prot & IOMMU_WRITE)
2713 prot |= IOMMU_PROT_IW;
2714
2715 mutex_lock(&domain->api_lock);
2716 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2717 mutex_unlock(&domain->api_lock);
2718
2719 return ret;
2720 }
2721
2722 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2723 int gfp_order)
2724 {
2725 struct protection_domain *domain = dom->priv;
2726 unsigned long page_size, unmap_size;
2727
2728 page_size = 0x1000UL << gfp_order;
2729
2730 mutex_lock(&domain->api_lock);
2731 unmap_size = iommu_unmap_page(domain, iova, page_size);
2732 mutex_unlock(&domain->api_lock);
2733
2734 domain_flush_tlb_pde(domain);
2735
2736 return get_order(unmap_size);
2737 }
2738
2739 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2740 unsigned long iova)
2741 {
2742 struct protection_domain *domain = dom->priv;
2743 unsigned long offset_mask;
2744 phys_addr_t paddr;
2745 u64 *pte, __pte;
2746
2747 pte = fetch_pte(domain, iova);
2748
2749 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2750 return 0;
2751
2752 if (PM_PTE_LEVEL(*pte) == 0)
2753 offset_mask = PAGE_SIZE - 1;
2754 else
2755 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2756
2757 __pte = *pte & PM_ADDR_MASK;
2758 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2759
2760 return paddr;
2761 }
2762
2763 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2764 unsigned long cap)
2765 {
2766 switch (cap) {
2767 case IOMMU_CAP_CACHE_COHERENCY:
2768 return 1;
2769 }
2770
2771 return 0;
2772 }
2773
2774 static struct iommu_ops amd_iommu_ops = {
2775 .domain_init = amd_iommu_domain_init,
2776 .domain_destroy = amd_iommu_domain_destroy,
2777 .attach_dev = amd_iommu_attach_device,
2778 .detach_dev = amd_iommu_detach_device,
2779 .map = amd_iommu_map,
2780 .unmap = amd_iommu_unmap,
2781 .iova_to_phys = amd_iommu_iova_to_phys,
2782 .domain_has_cap = amd_iommu_domain_has_cap,
2783 };
2784
2785 /*****************************************************************************
2786 *
2787 * The next functions do a basic initialization of IOMMU for pass through
2788 * mode
2789 *
2790 * In passthrough mode the IOMMU is initialized and enabled but not used for
2791 * DMA-API translation.
2792 *
2793 *****************************************************************************/
2794
2795 int __init amd_iommu_init_passthrough(void)
2796 {
2797 struct amd_iommu *iommu;
2798 struct pci_dev *dev = NULL;
2799 u16 devid;
2800
2801 /* allocate passthrough domain */
2802 pt_domain = protection_domain_alloc();
2803 if (!pt_domain)
2804 return -ENOMEM;
2805
2806 pt_domain->mode |= PAGE_MODE_NONE;
2807
2808 for_each_pci_dev(dev) {
2809 if (!check_device(&dev->dev))
2810 continue;
2811
2812 devid = get_device_id(&dev->dev);
2813
2814 iommu = amd_iommu_rlookup_table[devid];
2815 if (!iommu)
2816 continue;
2817
2818 attach_device(&dev->dev, pt_domain);
2819 }
2820
2821 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2822
2823 return 0;
2824 }
linux-next