drivers/media/video/omap3isp/isp.h

   1 /*
   2  * isp.h
   3  *
   4  * TI OMAP3 ISP - Core
   5  *
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  * Copyright (C) 2009 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24  * 02110-1301 USA
  25  */
  26
  27 #ifndef OMAP3_ISP_CORE_H
  28 #define OMAP3_ISP_CORE_H
  29
  30 #include <media/v4l2-device.h>
  31 #include <linux/device.h>
  32 #include <linux/io.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/wait.h>
  35 #include <plat/iommu.h>
  36 #include <plat/iovmm.h>
  37
  38 #include "ispstat.h"
  39 #include "ispccdc.h"
  40 #include "ispreg.h"
  41 #include "ispresizer.h"
  42 #include "isppreview.h"
  43 #include "ispcsiphy.h"
  44 #include "ispcsi2.h"
  45 #include "ispccp2.h"
  46
  47 #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
  48
  49 #define ISP_TOK_TERM            0xFFFFFFFF      /*
  50                                                  * terminating token for ISP
  51                                                  * modules reg list
  52                                                  */
  53 #define to_isp_device(ptr_module)                               \
  54         container_of(ptr_module, struct isp_device, isp_##ptr_module)
  55 #define to_device(ptr_module)                                           \
  56         (to_isp_device(ptr_module)->dev)
  57
  58 enum isp_mem_resources {
  59         OMAP3_ISP_IOMEM_MAIN,
  60         OMAP3_ISP_IOMEM_CCP2,
  61         OMAP3_ISP_IOMEM_CCDC,
  62         OMAP3_ISP_IOMEM_HIST,
  63         OMAP3_ISP_IOMEM_H3A,
  64         OMAP3_ISP_IOMEM_PREV,
  65         OMAP3_ISP_IOMEM_RESZ,
  66         OMAP3_ISP_IOMEM_SBL,
  67         OMAP3_ISP_IOMEM_CSI2A_REGS1,
  68         OMAP3_ISP_IOMEM_CSIPHY2,
  69         OMAP3_ISP_IOMEM_CSI2A_REGS2,
  70         OMAP3_ISP_IOMEM_CSI2C_REGS1,
  71         OMAP3_ISP_IOMEM_CSIPHY1,
  72         OMAP3_ISP_IOMEM_CSI2C_REGS2,
  73         OMAP3_ISP_IOMEM_LAST
  74 };
  75
  76 enum isp_sbl_resource {
  77         OMAP3_ISP_SBL_CSI1_READ         = 0x1,
  78         OMAP3_ISP_SBL_CSI1_WRITE        = 0x2,
  79         OMAP3_ISP_SBL_CSI2A_WRITE       = 0x4,
  80         OMAP3_ISP_SBL_CSI2C_WRITE       = 0x8,
  81         OMAP3_ISP_SBL_CCDC_LSC_READ     = 0x10,
  82         OMAP3_ISP_SBL_CCDC_WRITE        = 0x20,
  83         OMAP3_ISP_SBL_PREVIEW_READ      = 0x40,
  84         OMAP3_ISP_SBL_PREVIEW_WRITE     = 0x80,
  85         OMAP3_ISP_SBL_RESIZER_READ      = 0x100,
  86         OMAP3_ISP_SBL_RESIZER_WRITE     = 0x200,
  87 };
  88
  89 enum isp_subclk_resource {
  90         OMAP3_ISP_SUBCLK_CCDC           = (1 << 0),
  91         OMAP3_ISP_SUBCLK_H3A            = (1 << 1),
  92         OMAP3_ISP_SUBCLK_HIST           = (1 << 2),
  93         OMAP3_ISP_SUBCLK_PREVIEW        = (1 << 3),
  94         OMAP3_ISP_SUBCLK_RESIZER        = (1 << 4),
  95 };
  96
  97 enum isp_interface_type {
  98         ISP_INTERFACE_PARALLEL,
  99         ISP_INTERFACE_CSI2A_PHY2,
 100         ISP_INTERFACE_CCP2B_PHY1,
 101         ISP_INTERFACE_CCP2B_PHY2,
 102         ISP_INTERFACE_CSI2C_PHY1,
 103 };
 104
 105 /* ISP: OMAP 34xx ES 1.0 */
 106 #define ISP_REVISION_1_0                0x10
 107 /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
 108 #define ISP_REVISION_2_0                0x20
 109 /* ISP2P: OMAP 36xx */
 110 #define ISP_REVISION_15_0               0xF0
 111
 112 /*
 113  * struct isp_res_mapping - Map ISP io resources to ISP revision.
 114  * @isp_rev: ISP_REVISION_x_x
 115  * @map: bitmap for enum isp_mem_resources
 116  */
 117 struct isp_res_mapping {
 118         u32 isp_rev;
 119         u32 map;
 120 };
 121
 122 /*
 123  * struct isp_reg - Structure for ISP register values.
 124  * @reg: 32-bit Register address.
 125  * @val: 32-bit Register value.
 126  */
 127 struct isp_reg {
 128         enum isp_mem_resources mmio_range;
 129         u32 reg;
 130         u32 val;
 131 };
 132
 133 /**
 134  * struct isp_parallel_platform_data - Parallel interface platform data
 135  * @data_lane_shift: Data lane shifter
 136  *              0 - CAMEXT[13:0] -> CAM[13:0]
 137  *              1 - CAMEXT[13:2] -> CAM[11:0]
 138  *              2 - CAMEXT[13:4] -> CAM[9:0]
 139  *              3 - CAMEXT[13:6] -> CAM[7:0]
 140  * @clk_pol: Pixel clock polarity
 141  *              0 - Non Inverted, 1 - Inverted
 142  * @hs_pol: Horizontal synchronization polarity
 143  *              0 - Active high, 1 - Active low
 144  * @vs_pol: Vertical synchronization polarity
 145  *              0 - Active high, 1 - Active low
 146  * @bridge: CCDC Bridge input control
 147  *              ISPCTRL_PAR_BRIDGE_DISABLE - Disable
 148  *              ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
 149  *              ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
 150  */
 151 struct isp_parallel_platform_data {
 152         unsigned int data_lane_shift:2;
 153         unsigned int clk_pol:1;
 154         unsigned int hs_pol:1;
 155         unsigned int vs_pol:1;
 156         unsigned int bridge:4;
 157 };
 158
 159 /**
 160  * struct isp_ccp2_platform_data - CCP2 interface platform data
 161  * @strobe_clk_pol: Strobe/clock polarity
 162  *              0 - Non Inverted, 1 - Inverted
 163  * @crc: Enable the cyclic redundancy check
 164  * @ccp2_mode: Enable CCP2 compatibility mode
 165  *              0 - MIPI-CSI1 mode, 1 - CCP2 mode
 166  * @phy_layer: Physical layer selection
 167  *              ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer
 168  *              ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer
 169  * @vpclk_div: Video port output clock control
 170  */
 171 struct isp_ccp2_platform_data {
 172         unsigned int strobe_clk_pol:1;
 173         unsigned int crc:1;
 174         unsigned int ccp2_mode:1;
 175         unsigned int phy_layer:1;
 176         unsigned int vpclk_div:2;
 177 };
 178
 179 /**
 180  * struct isp_csi2_platform_data - CSI2 interface platform data
 181  * @crc: Enable the cyclic redundancy check
 182  * @vpclk_div: Video port output clock control
 183  */
 184 struct isp_csi2_platform_data {
 185         unsigned crc:1;
 186         unsigned vpclk_div:2;
 187 };
 188
 189 struct isp_subdev_i2c_board_info {
 190         struct i2c_board_info *board_info;
 191         int i2c_adapter_id;
 192 };
 193
 194 struct isp_v4l2_subdevs_group {
 195         struct isp_subdev_i2c_board_info *subdevs;
 196         enum isp_interface_type interface;
 197         union {
 198                 struct isp_parallel_platform_data parallel;
 199                 struct isp_ccp2_platform_data ccp2;
 200                 struct isp_csi2_platform_data csi2;
 201         } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
 202 };
 203
 204 struct isp_platform_data {
 205         struct isp_v4l2_subdevs_group *subdevs;
 206         void (*set_constraints)(struct isp_device *isp, bool enable);
 207 };
 208
 209 struct isp_platform_callback {
 210         u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
 211         int (*csiphy_config)(struct isp_csiphy *phy,
 212                              struct isp_csiphy_dphy_cfg *dphy,
 213                              struct isp_csiphy_lanes_cfg *lanes);
 214         void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
 215 };
 216
 217 /*
 218  * struct isp_device - ISP device structure.
 219  * @dev: Device pointer specific to the OMAP3 ISP.
 220  * @revision: Stores current ISP module revision.
 221  * @irq_num: Currently used IRQ number.
 222  * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 223  *             regions.
 224  * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 225  *                  regions.
 226  * @mmio_size: Array with ISP register regions size in bytes.
 227  * @raw_dmamask: Raw DMA mask
 228  * @stat_lock: Spinlock for handling statistics
 229  * @isp_mutex: Mutex for serializing requests to ISP.
 230  * @has_context: Context has been saved at least once and can be restored.
 231  * @ref_count: Reference count for handling multiple ISP requests.
 232  * @cam_ick: Pointer to camera interface clock structure.
 233  * @cam_mclk: Pointer to camera functional clock structure.
 234  * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
 235  * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 236  * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 237  * @irq: Currently attached ISP ISR callbacks information structure.
 238  * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 239  * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 240  * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 241  *           White Balance SCM.
 242  * @isp_res: Pointer to current settings for ISP Resizer.
 243  * @isp_prev: Pointer to current settings for ISP Preview.
 244  * @isp_ccdc: Pointer to current settings for ISP CCDC.
 245  * @iommu: Pointer to requested IOMMU instance for ISP.
 246  * @platform_cb: ISP driver callback function pointers for platform code
 247  *
 248  * This structure is used to store the OMAP ISP Information.
 249  */
 250 struct isp_device {
 251         struct v4l2_device v4l2_dev;
 252         struct media_device media_dev;
 253         struct device *dev;
 254         u32 revision;
 255
 256         /* platform HW resources */
 257         struct isp_platform_data *pdata;
 258         unsigned int irq_num;
 259
 260         void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
 261         unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
 262         resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
 263
 264         u64 raw_dmamask;
 265
 266         /* ISP Obj */
 267         spinlock_t stat_lock;   /* common lock for statistic drivers */
 268         struct mutex isp_mutex; /* For handling ref_count field */
 269         bool needs_reset;
 270         int has_context;
 271         int ref_count;
 272         unsigned int autoidle;
 273         u32 xclk_divisor[2];    /* Two clocks, a and b. */
 274 #define ISP_CLK_CAM_ICK         0
 275 #define ISP_CLK_CAM_MCLK        1
 276 #define ISP_CLK_DPLL4_M5_CK     2
 277 #define ISP_CLK_CSI2_FCK        3
 278 #define ISP_CLK_L3_ICK          4
 279         struct clk *clock[5];
 280
 281         /* ISP modules */
 282         struct ispstat isp_af;
 283         struct ispstat isp_aewb;
 284         struct ispstat isp_hist;
 285         struct isp_res_device isp_res;
 286         struct isp_prev_device isp_prev;
 287         struct isp_ccdc_device isp_ccdc;
 288         struct isp_csi2_device isp_csi2a;
 289         struct isp_csi2_device isp_csi2c;
 290         struct isp_ccp2_device isp_ccp2;
 291         struct isp_csiphy isp_csiphy1;
 292         struct isp_csiphy isp_csiphy2;
 293
 294         unsigned int sbl_resources;
 295         unsigned int subclk_resources;
 296
 297         struct iommu *iommu;
 298
 299         struct isp_platform_callback platform_cb;
 300 };
 301
 302 #define v4l2_dev_to_isp_device(dev) \
 303         container_of(dev, struct isp_device, v4l2_dev)
 304
 305 void omap3isp_hist_dma_done(struct isp_device *isp);
 306
 307 void omap3isp_flush(struct isp_device *isp);
 308
 309 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 310                               atomic_t *stopping);
 311
 312 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
 313                                      atomic_t *stopping);
 314
 315 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
 316                                  enum isp_pipeline_stream_state state);
 317 void omap3isp_configure_bridge(struct isp_device *isp,
 318                                enum ccdc_input_entity input,
 319                                const struct isp_parallel_platform_data *pdata,
 320                                unsigned int shift);
 321
 322 #define ISP_XCLK_NONE                   0
 323 #define ISP_XCLK_A                      1
 324 #define ISP_XCLK_B                      2
 325
 326 struct isp_device *omap3isp_get(struct isp_device *isp);
 327 void omap3isp_put(struct isp_device *isp);
 328
 329 void omap3isp_print_status(struct isp_device *isp);
 330
 331 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
 332 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
 333
 334 void omap3isp_subclk_enable(struct isp_device *isp,
 335                             enum isp_subclk_resource res);
 336 void omap3isp_subclk_disable(struct isp_device *isp,
 337                              enum isp_subclk_resource res);
 338
 339 int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
 340
 341 int omap3isp_register_entities(struct platform_device *pdev,
 342                                struct v4l2_device *v4l2_dev);
 343 void omap3isp_unregister_entities(struct platform_device *pdev);
 344
 345 /*
 346  * isp_reg_readl - Read value of an OMAP3 ISP register
 347  * @dev: Device pointer specific to the OMAP3 ISP.
 348  * @isp_mmio_range: Range to which the register offset refers to.
 349  * @reg_offset: Register offset to read from.
 350  *
 351  * Returns an unsigned 32 bit value with the required register contents.
 352  */
 353 static inline
 354 u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
 355                   u32 reg_offset)
 356 {
 357         return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
 358 }
 359
 360 /*
 361  * isp_reg_writel - Write value to an OMAP3 ISP register
 362  * @dev: Device pointer specific to the OMAP3 ISP.
 363  * @reg_value: 32 bit value to write to the register.
 364  * @isp_mmio_range: Range to which the register offset refers to.
 365  * @reg_offset: Register offset to write into.
 366  */
 367 static inline
 368 void isp_reg_writel(struct isp_device *isp, u32 reg_value,
 369                     enum isp_mem_resources isp_mmio_range, u32 reg_offset)
 370 {
 371         __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
 372 }
 373
 374 /*
 375  * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 376  * @dev: Device pointer specific to the OMAP3 ISP.
 377  * @mmio_range: Range to which the register offset refers to.
 378  * @reg: Register offset to work on.
 379  * @clr_bits: 32 bit value which would be cleared in the register.
 380  */
 381 static inline
 382 void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
 383                  u32 reg, u32 clr_bits)
 384 {
 385         u32 v = isp_reg_readl(isp, mmio_range, reg);
 386
 387         isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
 388 }
 389
 390 /*
 391  * isp_reg_set - Set individual bits in an OMAP3 ISP register
 392  * @dev: Device pointer specific to the OMAP3 ISP.
 393  * @mmio_range: Range to which the register offset refers to.
 394  * @reg: Register offset to work on.
 395  * @set_bits: 32 bit value which would be set in the register.
 396  */
 397 static inline
 398 void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 399                  u32 reg, u32 set_bits)
 400 {
 401         u32 v = isp_reg_readl(isp, mmio_range, reg);
 402
 403         isp_reg_writel(isp, v | set_bits, mmio_range, reg);
 404 }
 405
 406 /*
 407  * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 408  * @dev: Device pointer specific to the OMAP3 ISP.
 409  * @mmio_range: Range to which the register offset refers to.
 410  * @reg: Register offset to work on.
 411  * @clr_bits: 32 bit value which would be cleared in the register.
 412  * @set_bits: 32 bit value which would be set in the register.
 413  *
 414  * The clear operation is done first, and then the set operation.
 415  */
 416 static inline
 417 void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 418                      u32 reg, u32 clr_bits, u32 set_bits)
 419 {
 420         u32 v = isp_reg_readl(isp, mmio_range, reg);
 421
 422         isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
 423 }
 424
 425 static inline enum v4l2_buf_type
 426 isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
 427 {
 428         if (pad >= subdev->entity.num_pads)
 429                 return 0;
 430
 431         if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
 432                 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
 433         else
 434                 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
 435 }
 436
 437 #endif  /* OMAP3_ISP_CORE_H */