4 * Compaq ASIC3 support.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
29 #include <linux/mfd/asic3.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/ds1wm.h>
32 #include <linux/mfd/tmio.h>
55 #define INIT_CDEX(_name, _rate) \
56 [ASIC3_CLOCK_##_name] = { \
57 .cdex = CLOCK_CDEX_##_name, \
61 static struct asic3_clk asic3_clk_init
[] __initdata
= {
63 INIT_CDEX(OWM
, 5000000),
69 INIT_CDEX(SD_HOST
, 24576000),
70 INIT_CDEX(SD_BUS
, 12288000),
72 INIT_CDEX(EX0
, 32768),
73 INIT_CDEX(EX1
, 24576000),
77 void __iomem
*mapping
;
78 unsigned int bus_shift
;
80 unsigned int irq_base
;
83 struct gpio_chip gpio
;
85 void __iomem
*tmio_cnf
;
87 struct asic3_clk clocks
[ARRAY_SIZE(asic3_clk_init
)];
90 static int asic3_gpio_get(struct gpio_chip
*chip
, unsigned offset
);
92 void asic3_write_register(struct asic3
*asic
, unsigned int reg
, u32 value
)
94 iowrite16(value
, asic
->mapping
+
95 (reg
>> asic
->bus_shift
));
97 EXPORT_SYMBOL_GPL(asic3_write_register
);
99 u32
asic3_read_register(struct asic3
*asic
, unsigned int reg
)
101 return ioread16(asic
->mapping
+
102 (reg
>> asic
->bus_shift
));
104 EXPORT_SYMBOL_GPL(asic3_read_register
);
106 static void asic3_set_register(struct asic3
*asic
, u32 reg
, u32 bits
, bool set
)
111 spin_lock_irqsave(&asic
->lock
, flags
);
112 val
= asic3_read_register(asic
, reg
);
117 asic3_write_register(asic
, reg
, val
);
118 spin_unlock_irqrestore(&asic
->lock
, flags
);
122 #define MAX_ASIC_ISR_LOOPS 20
123 #define ASIC3_GPIO_BASE_INCR \
124 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
126 static void asic3_irq_flip_edge(struct asic3
*asic
,
132 spin_lock_irqsave(&asic
->lock
, flags
);
133 edge
= asic3_read_register(asic
,
134 base
+ ASIC3_GPIO_EDGE_TRIGGER
);
136 asic3_write_register(asic
,
137 base
+ ASIC3_GPIO_EDGE_TRIGGER
, edge
);
138 spin_unlock_irqrestore(&asic
->lock
, flags
);
141 static void asic3_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
143 struct asic3
*asic
= irq_desc_get_handler_data(desc
);
144 struct irq_data
*data
= irq_desc_get_irq_data(desc
);
148 data
->chip
->irq_ack(data
);
150 for (iter
= 0 ; iter
< MAX_ASIC_ISR_LOOPS
; iter
++) {
154 spin_lock_irqsave(&asic
->lock
, flags
);
155 status
= asic3_read_register(asic
,
156 ASIC3_OFFSET(INTR
, P_INT_STAT
));
157 spin_unlock_irqrestore(&asic
->lock
, flags
);
159 /* Check all ten register bits */
160 if ((status
& 0x3ff) == 0)
163 /* Handle GPIO IRQs */
164 for (bank
= 0; bank
< ASIC3_NUM_GPIO_BANKS
; bank
++) {
165 if (status
& (1 << bank
)) {
166 unsigned long base
, istat
;
168 base
= ASIC3_GPIO_A_BASE
169 + bank
* ASIC3_GPIO_BASE_INCR
;
171 spin_lock_irqsave(&asic
->lock
, flags
);
172 istat
= asic3_read_register(asic
,
174 ASIC3_GPIO_INT_STATUS
);
175 /* Clearing IntStatus */
176 asic3_write_register(asic
,
178 ASIC3_GPIO_INT_STATUS
, 0);
179 spin_unlock_irqrestore(&asic
->lock
, flags
);
181 for (i
= 0; i
< ASIC3_GPIOS_PER_BANK
; i
++) {
188 irqnr
= asic
->irq_base
+
189 (ASIC3_GPIOS_PER_BANK
* bank
)
191 generic_handle_irq(irqnr
);
192 if (asic
->irq_bothedge
[bank
] & bit
)
193 asic3_irq_flip_edge(asic
, base
,
199 /* Handle remaining IRQs in the status register */
200 for (i
= ASIC3_NUM_GPIOS
; i
< ASIC3_NR_IRQS
; i
++) {
201 /* They start at bit 4 and go up */
202 if (status
& (1 << (i
- ASIC3_NUM_GPIOS
+ 4)))
203 generic_handle_irq(asic
->irq_base
+ i
);
207 if (iter
>= MAX_ASIC_ISR_LOOPS
)
208 dev_err(asic
->dev
, "interrupt processing overrun\n");
211 static inline int asic3_irq_to_bank(struct asic3
*asic
, int irq
)
215 n
= (irq
- asic
->irq_base
) >> 4;
217 return (n
* (ASIC3_GPIO_B_BASE
- ASIC3_GPIO_A_BASE
));
220 static inline int asic3_irq_to_index(struct asic3
*asic
, int irq
)
222 return (irq
- asic
->irq_base
) & 0xf;
225 static void asic3_mask_gpio_irq(struct irq_data
*data
)
227 struct asic3
*asic
= irq_data_get_irq_chip_data(data
);
228 u32 val
, bank
, index
;
231 bank
= asic3_irq_to_bank(asic
, data
->irq
);
232 index
= asic3_irq_to_index(asic
, data
->irq
);
234 spin_lock_irqsave(&asic
->lock
, flags
);
235 val
= asic3_read_register(asic
, bank
+ ASIC3_GPIO_MASK
);
237 asic3_write_register(asic
, bank
+ ASIC3_GPIO_MASK
, val
);
238 spin_unlock_irqrestore(&asic
->lock
, flags
);
241 static void asic3_mask_irq(struct irq_data
*data
)
243 struct asic3
*asic
= irq_data_get_irq_chip_data(data
);
247 spin_lock_irqsave(&asic
->lock
, flags
);
248 regval
= asic3_read_register(asic
,
250 ASIC3_INTR_INT_MASK
);
252 regval
&= ~(ASIC3_INTMASK_MASK0
<<
253 (data
->irq
- (asic
->irq_base
+ ASIC3_NUM_GPIOS
)));
255 asic3_write_register(asic
,
259 spin_unlock_irqrestore(&asic
->lock
, flags
);
262 static void asic3_unmask_gpio_irq(struct irq_data
*data
)
264 struct asic3
*asic
= irq_data_get_irq_chip_data(data
);
265 u32 val
, bank
, index
;
268 bank
= asic3_irq_to_bank(asic
, data
->irq
);
269 index
= asic3_irq_to_index(asic
, data
->irq
);
271 spin_lock_irqsave(&asic
->lock
, flags
);
272 val
= asic3_read_register(asic
, bank
+ ASIC3_GPIO_MASK
);
273 val
&= ~(1 << index
);
274 asic3_write_register(asic
, bank
+ ASIC3_GPIO_MASK
, val
);
275 spin_unlock_irqrestore(&asic
->lock
, flags
);
278 static void asic3_unmask_irq(struct irq_data
*data
)
280 struct asic3
*asic
= irq_data_get_irq_chip_data(data
);
284 spin_lock_irqsave(&asic
->lock
, flags
);
285 regval
= asic3_read_register(asic
,
287 ASIC3_INTR_INT_MASK
);
289 regval
|= (ASIC3_INTMASK_MASK0
<<
290 (data
->irq
- (asic
->irq_base
+ ASIC3_NUM_GPIOS
)));
292 asic3_write_register(asic
,
296 spin_unlock_irqrestore(&asic
->lock
, flags
);
299 static int asic3_gpio_irq_type(struct irq_data
*data
, unsigned int type
)
301 struct asic3
*asic
= irq_data_get_irq_chip_data(data
);
303 u16 trigger
, level
, edge
, bit
;
306 bank
= asic3_irq_to_bank(asic
, data
->irq
);
307 index
= asic3_irq_to_index(asic
, data
->irq
);
310 spin_lock_irqsave(&asic
->lock
, flags
);
311 level
= asic3_read_register(asic
,
312 bank
+ ASIC3_GPIO_LEVEL_TRIGGER
);
313 edge
= asic3_read_register(asic
,
314 bank
+ ASIC3_GPIO_EDGE_TRIGGER
);
315 trigger
= asic3_read_register(asic
,
316 bank
+ ASIC3_GPIO_TRIGGER_TYPE
);
317 asic
->irq_bothedge
[(data
->irq
- asic
->irq_base
) >> 4] &= ~bit
;
319 if (type
== IRQ_TYPE_EDGE_RISING
) {
322 } else if (type
== IRQ_TYPE_EDGE_FALLING
) {
325 } else if (type
== IRQ_TYPE_EDGE_BOTH
) {
327 if (asic3_gpio_get(&asic
->gpio
, data
->irq
- asic
->irq_base
))
331 asic
->irq_bothedge
[(data
->irq
- asic
->irq_base
) >> 4] |= bit
;
332 } else if (type
== IRQ_TYPE_LEVEL_LOW
) {
335 } else if (type
== IRQ_TYPE_LEVEL_HIGH
) {
340 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
341 * be careful to not unmask them if mask was also called.
342 * Probably need internal state for mask.
344 dev_notice(asic
->dev
, "irq type not changed\n");
346 asic3_write_register(asic
, bank
+ ASIC3_GPIO_LEVEL_TRIGGER
,
348 asic3_write_register(asic
, bank
+ ASIC3_GPIO_EDGE_TRIGGER
,
350 asic3_write_register(asic
, bank
+ ASIC3_GPIO_TRIGGER_TYPE
,
352 spin_unlock_irqrestore(&asic
->lock
, flags
);
356 static struct irq_chip asic3_gpio_irq_chip
= {
357 .name
= "ASIC3-GPIO",
358 .irq_ack
= asic3_mask_gpio_irq
,
359 .irq_mask
= asic3_mask_gpio_irq
,
360 .irq_unmask
= asic3_unmask_gpio_irq
,
361 .irq_set_type
= asic3_gpio_irq_type
,
364 static struct irq_chip asic3_irq_chip
= {
366 .irq_ack
= asic3_mask_irq
,
367 .irq_mask
= asic3_mask_irq
,
368 .irq_unmask
= asic3_unmask_irq
,
371 static int __init
asic3_irq_probe(struct platform_device
*pdev
)
373 struct asic3
*asic
= platform_get_drvdata(pdev
);
374 unsigned long clksel
= 0;
375 unsigned int irq
, irq_base
;
378 ret
= platform_get_irq(pdev
, 0);
383 /* turn on clock to IRQ controller */
384 clksel
|= CLOCK_SEL_CX
;
385 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
),
388 irq_base
= asic
->irq_base
;
390 for (irq
= irq_base
; irq
< irq_base
+ ASIC3_NR_IRQS
; irq
++) {
391 if (irq
< asic
->irq_base
+ ASIC3_NUM_GPIOS
)
392 irq_set_chip(irq
, &asic3_gpio_irq_chip
);
394 irq_set_chip(irq
, &asic3_irq_chip
);
396 irq_set_chip_data(irq
, asic
);
397 irq_set_handler(irq
, handle_level_irq
);
398 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
401 asic3_write_register(asic
, ASIC3_OFFSET(INTR
, INT_MASK
),
402 ASIC3_INTMASK_GINTMASK
);
404 irq_set_chained_handler(asic
->irq_nr
, asic3_irq_demux
);
405 irq_set_irq_type(asic
->irq_nr
, IRQ_TYPE_EDGE_RISING
);
406 irq_set_handler_data(asic
->irq_nr
, asic
);
411 static void asic3_irq_remove(struct platform_device
*pdev
)
413 struct asic3
*asic
= platform_get_drvdata(pdev
);
414 unsigned int irq
, irq_base
;
416 irq_base
= asic
->irq_base
;
418 for (irq
= irq_base
; irq
< irq_base
+ ASIC3_NR_IRQS
; irq
++) {
419 set_irq_flags(irq
, 0);
420 irq_set_chip_and_handler(irq
, NULL
, NULL
);
421 irq_set_chip_data(irq
, NULL
);
423 irq_set_chained_handler(asic
->irq_nr
, NULL
);
427 static int asic3_gpio_direction(struct gpio_chip
*chip
,
428 unsigned offset
, int out
)
430 u32 mask
= ASIC3_GPIO_TO_MASK(offset
), out_reg
;
431 unsigned int gpio_base
;
435 asic
= container_of(chip
, struct asic3
, gpio
);
436 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
438 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
439 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
444 spin_lock_irqsave(&asic
->lock
, flags
);
446 out_reg
= asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_DIRECTION
);
448 /* Input is 0, Output is 1 */
454 asic3_write_register(asic
, gpio_base
+ ASIC3_GPIO_DIRECTION
, out_reg
);
456 spin_unlock_irqrestore(&asic
->lock
, flags
);
462 static int asic3_gpio_direction_input(struct gpio_chip
*chip
,
465 return asic3_gpio_direction(chip
, offset
, 0);
468 static int asic3_gpio_direction_output(struct gpio_chip
*chip
,
469 unsigned offset
, int value
)
471 return asic3_gpio_direction(chip
, offset
, 1);
474 static int asic3_gpio_get(struct gpio_chip
*chip
,
477 unsigned int gpio_base
;
478 u32 mask
= ASIC3_GPIO_TO_MASK(offset
);
481 asic
= container_of(chip
, struct asic3
, gpio
);
482 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
484 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
485 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
490 return asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_STATUS
) & mask
;
493 static void asic3_gpio_set(struct gpio_chip
*chip
,
494 unsigned offset
, int value
)
497 unsigned int gpio_base
;
501 asic
= container_of(chip
, struct asic3
, gpio
);
502 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
504 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
505 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
510 mask
= ASIC3_GPIO_TO_MASK(offset
);
512 spin_lock_irqsave(&asic
->lock
, flags
);
514 out_reg
= asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_OUT
);
521 asic3_write_register(asic
, gpio_base
+ ASIC3_GPIO_OUT
, out_reg
);
523 spin_unlock_irqrestore(&asic
->lock
, flags
);
528 static __init
int asic3_gpio_probe(struct platform_device
*pdev
,
529 u16
*gpio_config
, int num
)
531 struct asic3
*asic
= platform_get_drvdata(pdev
);
532 u16 alt_reg
[ASIC3_NUM_GPIO_BANKS
];
533 u16 out_reg
[ASIC3_NUM_GPIO_BANKS
];
534 u16 dir_reg
[ASIC3_NUM_GPIO_BANKS
];
537 memset(alt_reg
, 0, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
538 memset(out_reg
, 0, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
539 memset(dir_reg
, 0, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
541 /* Enable all GPIOs */
542 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(A
, MASK
), 0xffff);
543 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(B
, MASK
), 0xffff);
544 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(C
, MASK
), 0xffff);
545 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(D
, MASK
), 0xffff);
547 for (i
= 0; i
< num
; i
++) {
548 u8 alt
, pin
, dir
, init
, bank_num
, bit_num
;
549 u16 config
= gpio_config
[i
];
551 pin
= ASIC3_CONFIG_GPIO_PIN(config
);
552 alt
= ASIC3_CONFIG_GPIO_ALT(config
);
553 dir
= ASIC3_CONFIG_GPIO_DIR(config
);
554 init
= ASIC3_CONFIG_GPIO_INIT(config
);
556 bank_num
= ASIC3_GPIO_TO_BANK(pin
);
557 bit_num
= ASIC3_GPIO_TO_BIT(pin
);
559 alt_reg
[bank_num
] |= (alt
<< bit_num
);
560 out_reg
[bank_num
] |= (init
<< bit_num
);
561 dir_reg
[bank_num
] |= (dir
<< bit_num
);
564 for (i
= 0; i
< ASIC3_NUM_GPIO_BANKS
; i
++) {
565 asic3_write_register(asic
,
566 ASIC3_BANK_TO_BASE(i
) +
567 ASIC3_GPIO_DIRECTION
,
569 asic3_write_register(asic
,
570 ASIC3_BANK_TO_BASE(i
) + ASIC3_GPIO_OUT
,
572 asic3_write_register(asic
,
573 ASIC3_BANK_TO_BASE(i
) +
574 ASIC3_GPIO_ALT_FUNCTION
,
578 return gpiochip_add(&asic
->gpio
);
581 static int asic3_gpio_remove(struct platform_device
*pdev
)
583 struct asic3
*asic
= platform_get_drvdata(pdev
);
585 return gpiochip_remove(&asic
->gpio
);
588 static int asic3_clk_enable(struct asic3
*asic
, struct asic3_clk
*clk
)
593 spin_lock_irqsave(&asic
->lock
, flags
);
594 if (clk
->enabled
++ == 0) {
595 cdex
= asic3_read_register(asic
, ASIC3_OFFSET(CLOCK
, CDEX
));
597 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, CDEX
), cdex
);
599 spin_unlock_irqrestore(&asic
->lock
, flags
);
604 static void asic3_clk_disable(struct asic3
*asic
, struct asic3_clk
*clk
)
609 WARN_ON(clk
->enabled
== 0);
611 spin_lock_irqsave(&asic
->lock
, flags
);
612 if (--clk
->enabled
== 0) {
613 cdex
= asic3_read_register(asic
, ASIC3_OFFSET(CLOCK
, CDEX
));
615 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, CDEX
), cdex
);
617 spin_unlock_irqrestore(&asic
->lock
, flags
);
620 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
621 static struct ds1wm_driver_data ds1wm_pdata
= {
623 .reset_recover_delay
= 1,
626 static struct resource ds1wm_resources
[] = {
628 .start
= ASIC3_OWM_BASE
,
629 .end
= ASIC3_OWM_BASE
+ 0x13,
630 .flags
= IORESOURCE_MEM
,
633 .start
= ASIC3_IRQ_OWM
,
634 .end
= ASIC3_IRQ_OWM
,
635 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_HIGHEDGE
,
639 static int ds1wm_enable(struct platform_device
*pdev
)
641 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
643 /* Turn on external clocks and the OWM clock */
644 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX0
]);
645 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX1
]);
646 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_OWM
]);
649 /* Reset and enable DS1WM */
650 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, RESET
),
651 ASIC3_EXTCF_OWM_RESET
, 1);
653 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, RESET
),
654 ASIC3_EXTCF_OWM_RESET
, 0);
656 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, SELECT
),
657 ASIC3_EXTCF_OWM_EN
, 1);
663 static int ds1wm_disable(struct platform_device
*pdev
)
665 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
667 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, SELECT
),
668 ASIC3_EXTCF_OWM_EN
, 0);
670 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_OWM
]);
671 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX0
]);
672 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX1
]);
677 static struct mfd_cell asic3_cell_ds1wm
= {
679 .enable
= ds1wm_enable
,
680 .disable
= ds1wm_disable
,
681 .platform_data
= &ds1wm_pdata
,
682 .pdata_size
= sizeof(ds1wm_pdata
),
683 .num_resources
= ARRAY_SIZE(ds1wm_resources
),
684 .resources
= ds1wm_resources
,
687 static void asic3_mmc_pwr(struct platform_device
*pdev
, int state
)
689 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
691 tmio_core_mmc_pwr(asic
->tmio_cnf
, 1 - asic
->bus_shift
, state
);
694 static void asic3_mmc_clk_div(struct platform_device
*pdev
, int state
)
696 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
698 tmio_core_mmc_clk_div(asic
->tmio_cnf
, 1 - asic
->bus_shift
, state
);
701 static struct tmio_mmc_data asic3_mmc_data
= {
703 .set_pwr
= asic3_mmc_pwr
,
704 .set_clk_div
= asic3_mmc_clk_div
,
707 static struct resource asic3_mmc_resources
[] = {
709 .start
= ASIC3_SD_CTRL_BASE
,
710 .end
= ASIC3_SD_CTRL_BASE
+ 0x3ff,
711 .flags
= IORESOURCE_MEM
,
716 .flags
= IORESOURCE_IRQ
,
720 static int asic3_mmc_enable(struct platform_device
*pdev
)
722 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
724 /* Not sure if it must be done bit by bit, but leaving as-is */
725 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
726 ASIC3_SDHWCTRL_LEVCD
, 1);
727 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
728 ASIC3_SDHWCTRL_LEVWP
, 1);
729 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
730 ASIC3_SDHWCTRL_SUSPEND
, 0);
731 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
732 ASIC3_SDHWCTRL_PCLR
, 0);
734 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX0
]);
735 /* CLK32 used for card detection and for interruption detection
736 * when HCLK is stopped.
738 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX1
]);
741 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
742 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
),
743 CLOCK_SEL_CX
| CLOCK_SEL_SD_HCLK_SEL
);
745 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_SD_HOST
]);
746 asic3_clk_enable(asic
, &asic
->clocks
[ASIC3_CLOCK_SD_BUS
]);
749 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, SELECT
),
750 ASIC3_EXTCF_SD_MEM_ENABLE
, 1);
752 /* Enable SD card slot 3.3V power supply */
753 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
754 ASIC3_SDHWCTRL_SDPWR
, 1);
756 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
757 tmio_core_mmc_enable(asic
->tmio_cnf
, 1 - asic
->bus_shift
,
758 ASIC3_SD_CTRL_BASE
>> 1);
763 static int asic3_mmc_disable(struct platform_device
*pdev
)
765 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
767 /* Put in suspend mode */
768 asic3_set_register(asic
, ASIC3_OFFSET(SDHWCTRL
, SDCONF
),
769 ASIC3_SDHWCTRL_SUSPEND
, 1);
772 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_SD_HOST
]);
773 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_SD_BUS
]);
774 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX0
]);
775 asic3_clk_disable(asic
, &asic
->clocks
[ASIC3_CLOCK_EX1
]);
779 static struct mfd_cell asic3_cell_mmc
= {
781 .enable
= asic3_mmc_enable
,
782 .disable
= asic3_mmc_disable
,
783 .platform_data
= &asic3_mmc_data
,
784 .pdata_size
= sizeof(asic3_mmc_data
),
785 .num_resources
= ARRAY_SIZE(asic3_mmc_resources
),
786 .resources
= asic3_mmc_resources
,
789 static const int clock_ledn
[ASIC3_NUM_LEDS
] = {
790 [0] = ASIC3_CLOCK_LED0
,
791 [1] = ASIC3_CLOCK_LED1
,
792 [2] = ASIC3_CLOCK_LED2
,
795 static int asic3_leds_enable(struct platform_device
*pdev
)
797 const struct mfd_cell
*cell
= mfd_get_cell(pdev
);
798 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
800 asic3_clk_enable(asic
, &asic
->clocks
[clock_ledn
[cell
->id
]]);
805 static int asic3_leds_disable(struct platform_device
*pdev
)
807 const struct mfd_cell
*cell
= mfd_get_cell(pdev
);
808 struct asic3
*asic
= dev_get_drvdata(pdev
->dev
.parent
);
810 asic3_clk_disable(asic
, &asic
->clocks
[clock_ledn
[cell
->id
]]);
815 static struct mfd_cell asic3_cell_leds
[ASIC3_NUM_LEDS
] = {
817 .name
= "leds-asic3",
819 .enable
= asic3_leds_enable
,
820 .disable
= asic3_leds_disable
,
823 .name
= "leds-asic3",
825 .enable
= asic3_leds_enable
,
826 .disable
= asic3_leds_disable
,
829 .name
= "leds-asic3",
831 .enable
= asic3_leds_enable
,
832 .disable
= asic3_leds_disable
,
836 static int __init
asic3_mfd_probe(struct platform_device
*pdev
,
837 struct asic3_platform_data
*pdata
,
838 struct resource
*mem
)
840 struct asic3
*asic
= platform_get_drvdata(pdev
);
841 struct resource
*mem_sdio
;
844 mem_sdio
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
846 dev_dbg(asic
->dev
, "no SDIO MEM resource\n");
848 irq
= platform_get_irq(pdev
, 1);
850 dev_dbg(asic
->dev
, "no SDIO IRQ resource\n");
853 asic3_set_register(asic
, ASIC3_OFFSET(EXTCF
, SELECT
),
854 ASIC3_EXTCF_OWM_SMB
, 0);
856 ds1wm_resources
[0].start
>>= asic
->bus_shift
;
857 ds1wm_resources
[0].end
>>= asic
->bus_shift
;
860 asic
->tmio_cnf
= ioremap((ASIC3_SD_CONFIG_BASE
>> asic
->bus_shift
) +
862 ASIC3_SD_CONFIG_SIZE
>> asic
->bus_shift
);
863 if (!asic
->tmio_cnf
) {
865 dev_dbg(asic
->dev
, "Couldn't ioremap SD_CONFIG\n");
868 asic3_mmc_resources
[0].start
>>= asic
->bus_shift
;
869 asic3_mmc_resources
[0].end
>>= asic
->bus_shift
;
871 ret
= mfd_add_devices(&pdev
->dev
, pdev
->id
,
872 &asic3_cell_ds1wm
, 1, mem
, asic
->irq_base
);
876 if (mem_sdio
&& (irq
>= 0)) {
877 ret
= mfd_add_devices(&pdev
->dev
, pdev
->id
,
878 &asic3_cell_mmc
, 1, mem_sdio
, irq
);
886 for (i
= 0; i
< ASIC3_NUM_LEDS
; ++i
) {
887 asic3_cell_leds
[i
].platform_data
= &pdata
->leds
[i
];
888 asic3_cell_leds
[i
].pdata_size
= sizeof(pdata
->leds
[i
]);
890 ret
= mfd_add_devices(&pdev
->dev
, 0,
891 asic3_cell_leds
, ASIC3_NUM_LEDS
, NULL
, 0);
898 static void asic3_mfd_remove(struct platform_device
*pdev
)
900 struct asic3
*asic
= platform_get_drvdata(pdev
);
902 mfd_remove_devices(&pdev
->dev
);
903 iounmap(asic
->tmio_cnf
);
907 static int __init
asic3_probe(struct platform_device
*pdev
)
909 struct asic3_platform_data
*pdata
= pdev
->dev
.platform_data
;
911 struct resource
*mem
;
912 unsigned long clksel
;
915 asic
= kzalloc(sizeof(struct asic3
), GFP_KERNEL
);
917 printk(KERN_ERR
"kzalloc failed\n");
921 spin_lock_init(&asic
->lock
);
922 platform_set_drvdata(pdev
, asic
);
923 asic
->dev
= &pdev
->dev
;
925 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
928 dev_err(asic
->dev
, "no MEM resource\n");
932 asic
->mapping
= ioremap(mem
->start
, resource_size(mem
));
933 if (!asic
->mapping
) {
935 dev_err(asic
->dev
, "Couldn't ioremap\n");
939 asic
->irq_base
= pdata
->irq_base
;
941 /* calculate bus shift from mem resource */
942 asic
->bus_shift
= 2 - (resource_size(mem
) >> 12);
945 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
), clksel
);
947 ret
= asic3_irq_probe(pdev
);
949 dev_err(asic
->dev
, "Couldn't probe IRQs\n");
953 asic
->gpio
.base
= pdata
->gpio_base
;
954 asic
->gpio
.ngpio
= ASIC3_NUM_GPIOS
;
955 asic
->gpio
.get
= asic3_gpio_get
;
956 asic
->gpio
.set
= asic3_gpio_set
;
957 asic
->gpio
.direction_input
= asic3_gpio_direction_input
;
958 asic
->gpio
.direction_output
= asic3_gpio_direction_output
;
960 ret
= asic3_gpio_probe(pdev
,
962 pdata
->gpio_config_num
);
964 dev_err(asic
->dev
, "GPIO probe failed\n");
968 /* Making a per-device copy is only needed for the
969 * theoretical case of multiple ASIC3s on one board:
971 memcpy(asic
->clocks
, asic3_clk_init
, sizeof(asic3_clk_init
));
973 asic3_mfd_probe(pdev
, pdata
, mem
);
975 dev_info(asic
->dev
, "ASIC3 Core driver\n");
980 asic3_irq_remove(pdev
);
983 iounmap(asic
->mapping
);
991 static int __devexit
asic3_remove(struct platform_device
*pdev
)
994 struct asic3
*asic
= platform_get_drvdata(pdev
);
996 asic3_mfd_remove(pdev
);
998 ret
= asic3_gpio_remove(pdev
);
1001 asic3_irq_remove(pdev
);
1003 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
), 0);
1005 iounmap(asic
->mapping
);
1012 static void asic3_shutdown(struct platform_device
*pdev
)
1016 static struct platform_driver asic3_device_driver
= {
1020 .remove
= __devexit_p(asic3_remove
),
1021 .shutdown
= asic3_shutdown
,
1024 static int __init
asic3_init(void)
1027 retval
= platform_driver_probe(&asic3_device_driver
, asic3_probe
);
1031 subsys_initcall(asic3_init
);