?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / mfd / omap-usb-host.c
blob03debe880432d404ac70dd1ca75a48e822f35756
1 /**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spinlock.h>
28 #include <linux/gpio.h>
29 #include <plat/usb.h>
30
31 #define USBHS_DRIVER_NAME "usbhs-omap"
32 #define OMAP_EHCI_DEVICE "ehci-omap"
33 #define OMAP_OHCI_DEVICE "ohci-omap3"
34
35 /* OMAP USBHOST Register addresses */
36
37 /* TLL Register Set */
38 #define OMAP_USBTLL_REVISION (0x00)
39 #define OMAP_USBTLL_SYSCONFIG (0x10)
40 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
41 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
42 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
43 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
44 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
45
46 #define OMAP_USBTLL_SYSSTATUS (0x14)
47 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
48
49 #define OMAP_USBTLL_IRQSTATUS (0x18)
50 #define OMAP_USBTLL_IRQENABLE (0x1C)
51
52 #define OMAP_TLL_SHARED_CONF (0x30)
53 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
54 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
55 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
56 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
57 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
58
59 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
60 #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
61 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
62 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
63 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
64 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
65 #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
66 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
67
68 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
69 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
70 #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
71 #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
72 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
73 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
74 #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
75 #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
76 #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
77 #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
78
79 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
80 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
81 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
82 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
83 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
84 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
85 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
86 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
87 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
88
89 #define OMAP_TLL_CHANNEL_COUNT 3
90 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
91 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
92 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
93
94 /* UHH Register Set */
95 #define OMAP_UHH_REVISION (0x00)
96 #define OMAP_UHH_SYSCONFIG (0x10)
97 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
98 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
99 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
100 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
101 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
102 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
103
104 #define OMAP_UHH_SYSSTATUS (0x14)
105 #define OMAP_UHH_HOSTCONFIG (0x40)
106 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
107 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
108 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
109 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
110 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
111 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
112 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
113 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
114 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
115 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
116 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
117 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
118
119 /* OMAP4-specific defines */
120 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
121 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
122 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
123 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
124 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
125
126 #define OMAP4_P1_MODE_CLEAR (3 << 16)
127 #define OMAP4_P1_MODE_TLL (1 << 16)
128 #define OMAP4_P1_MODE_HSIC (3 << 16)
129 #define OMAP4_P2_MODE_CLEAR (3 << 18)
130 #define OMAP4_P2_MODE_TLL (1 << 18)
131 #define OMAP4_P2_MODE_HSIC (3 << 18)
132
133 #define OMAP_REV2_TLL_CHANNEL_COUNT 2
134
135 #define OMAP_UHH_DEBUG_CSR (0x44)
136
137 /* Values of UHH_REVISION - Note: these are not given in the TRM */
138 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
139 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
140
141 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
142 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
143
144 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
145 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
146 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
147
148
149 struct usbhs_hcd_omap {
150 struct clk *usbhost_ick;
151 struct clk *usbhost_hs_fck;
152 struct clk *usbhost_fs_fck;
153 struct clk *xclk60mhsp1_ck;
154 struct clk *xclk60mhsp2_ck;
155 struct clk *utmi_p1_fck;
156 struct clk *usbhost_p1_fck;
157 struct clk *usbtll_p1_fck;
158 struct clk *utmi_p2_fck;
159 struct clk *usbhost_p2_fck;
160 struct clk *usbtll_p2_fck;
161 struct clk *init_60m_fclk;
162 struct clk *usbtll_fck;
163 struct clk *usbtll_ick;
164
165 void __iomem *uhh_base;
166 void __iomem *tll_base;
167
168 struct usbhs_omap_platform_data platdata;
169
170 u32 usbhs_rev;
171 spinlock_t lock;
172 int count;
173 };
174 /*-------------------------------------------------------------------------*/
175
176 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
177 static u64 usbhs_dmamask = ~(u32)0;
178
179 /*-------------------------------------------------------------------------*/
180
181 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
182 {
183 __raw_writel(val, base + reg);
184 }
185
186 static inline u32 usbhs_read(void __iomem *base, u32 reg)
187 {
188 return __raw_readl(base + reg);
189 }
190
191 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
192 {
193 __raw_writeb(val, base + reg);
194 }
195
196 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
197 {
198 return __raw_readb(base + reg);
199 }
200
201 /*-------------------------------------------------------------------------*/
202
203 static struct platform_device *omap_usbhs_alloc_child(const char *name,
204 struct resource *res, int num_resources, void *pdata,
205 size_t pdata_size, struct device *dev)
206 {
207 struct platform_device *child;
208 int ret;
209
210 child = platform_device_alloc(name, 0);
211
212 if (!child) {
213 dev_err(dev, "platform_device_alloc %s failed\n", name);
214 goto err_end;
215 }
216
217 ret = platform_device_add_resources(child, res, num_resources);
218 if (ret) {
219 dev_err(dev, "platform_device_add_resources failed\n");
220 goto err_alloc;
221 }
222
223 ret = platform_device_add_data(child, pdata, pdata_size);
224 if (ret) {
225 dev_err(dev, "platform_device_add_data failed\n");
226 goto err_alloc;
227 }
228
229 child->dev.dma_mask = &usbhs_dmamask;
230 child->dev.coherent_dma_mask = 0xffffffff;
231 child->dev.parent = dev;
232
233 ret = platform_device_add(child);
234 if (ret) {
235 dev_err(dev, "platform_device_add failed\n");
236 goto err_alloc;
237 }
238
239 return child;
240
241 err_alloc:
242 platform_device_put(child);
243
244 err_end:
245 return NULL;
246 }
247
248 static int omap_usbhs_alloc_children(struct platform_device *pdev)
249 {
250 struct device *dev = &pdev->dev;
251 struct usbhs_hcd_omap *omap;
252 struct ehci_hcd_omap_platform_data *ehci_data;
253 struct ohci_hcd_omap_platform_data *ohci_data;
254 struct platform_device *ehci;
255 struct platform_device *ohci;
256 struct resource *res;
257 struct resource resources[2];
258 int ret;
259
260 omap = platform_get_drvdata(pdev);
261 ehci_data = omap->platdata.ehci_data;
262 ohci_data = omap->platdata.ohci_data;
263
264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
265 if (!res) {
266 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
267 ret = -ENODEV;
268 goto err_end;
269 }
270 resources[0] = *res;
271
272 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
273 if (!res) {
274 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
275 ret = -ENODEV;
276 goto err_end;
277 }
278 resources[1] = *res;
279
280 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
281 sizeof(*ehci_data), dev);
282
283 if (!ehci) {
284 dev_err(dev, "omap_usbhs_alloc_child failed\n");
285 ret = -ENOMEM;
286 goto err_end;
287 }
288
289 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
290 if (!res) {
291 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
292 ret = -ENODEV;
293 goto err_ehci;
294 }
295 resources[0] = *res;
296
297 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
298 if (!res) {
299 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
300 ret = -ENODEV;
301 goto err_ehci;
302 }
303 resources[1] = *res;
304
305 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
306 sizeof(*ohci_data), dev);
307 if (!ohci) {
308 dev_err(dev, "omap_usbhs_alloc_child failed\n");
309 ret = -ENOMEM;
310 goto err_ehci;
311 }
312
313 return 0;
314
315 err_ehci:
316 platform_device_unregister(ehci);
317
318 err_end:
319 return ret;
320 }
321
322 /**
323 * usbhs_omap_probe - initialize TI-based HCDs
324 *
325 * Allocates basic resources for this USB host controller.
326 */
327 static int __devinit usbhs_omap_probe(struct platform_device *pdev)
328 {
329 struct device *dev = &pdev->dev;
330 struct usbhs_omap_platform_data *pdata = dev->platform_data;
331 struct usbhs_hcd_omap *omap;
332 struct resource *res;
333 int ret = 0;
334 int i;
335
336 if (!pdata) {
337 dev_err(dev, "Missing platform data\n");
338 ret = -ENOMEM;
339 goto end_probe;
340 }
341
342 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
343 if (!omap) {
344 dev_err(dev, "Memory allocation failed\n");
345 ret = -ENOMEM;
346 goto end_probe;
347 }
348
349 spin_lock_init(&omap->lock);
350
351 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
352 omap->platdata.port_mode[i] = pdata->port_mode[i];
353
354 omap->platdata.ehci_data = pdata->ehci_data;
355 omap->platdata.ohci_data = pdata->ohci_data;
356
357 omap->usbhost_ick = clk_get(dev, "usbhost_ick");
358 if (IS_ERR(omap->usbhost_ick)) {
359 ret = PTR_ERR(omap->usbhost_ick);
360 dev_err(dev, "usbhost_ick failed error:%d\n", ret);
361 goto err_end;
362 }
363
364 omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
365 if (IS_ERR(omap->usbhost_hs_fck)) {
366 ret = PTR_ERR(omap->usbhost_hs_fck);
367 dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
368 goto err_usbhost_ick;
369 }
370
371 omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
372 if (IS_ERR(omap->usbhost_fs_fck)) {
373 ret = PTR_ERR(omap->usbhost_fs_fck);
374 dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
375 goto err_usbhost_hs_fck;
376 }
377
378 omap->usbtll_fck = clk_get(dev, "usbtll_fck");
379 if (IS_ERR(omap->usbtll_fck)) {
380 ret = PTR_ERR(omap->usbtll_fck);
381 dev_err(dev, "usbtll_fck failed error:%d\n", ret);
382 goto err_usbhost_fs_fck;
383 }
384
385 omap->usbtll_ick = clk_get(dev, "usbtll_ick");
386 if (IS_ERR(omap->usbtll_ick)) {
387 ret = PTR_ERR(omap->usbtll_ick);
388 dev_err(dev, "usbtll_ick failed error:%d\n", ret);
389 goto err_usbtll_fck;
390 }
391
392 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
393 if (IS_ERR(omap->utmi_p1_fck)) {
394 ret = PTR_ERR(omap->utmi_p1_fck);
395 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
396 goto err_usbtll_ick;
397 }
398
399 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
400 if (IS_ERR(omap->xclk60mhsp1_ck)) {
401 ret = PTR_ERR(omap->xclk60mhsp1_ck);
402 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
403 goto err_utmi_p1_fck;
404 }
405
406 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
407 if (IS_ERR(omap->utmi_p2_fck)) {
408 ret = PTR_ERR(omap->utmi_p2_fck);
409 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
410 goto err_xclk60mhsp1_ck;
411 }
412
413 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
414 if (IS_ERR(omap->xclk60mhsp2_ck)) {
415 ret = PTR_ERR(omap->xclk60mhsp2_ck);
416 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
417 goto err_utmi_p2_fck;
418 }
419
420 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
421 if (IS_ERR(omap->usbhost_p1_fck)) {
422 ret = PTR_ERR(omap->usbhost_p1_fck);
423 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
424 goto err_xclk60mhsp2_ck;
425 }
426
427 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
428 if (IS_ERR(omap->usbtll_p1_fck)) {
429 ret = PTR_ERR(omap->usbtll_p1_fck);
430 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
431 goto err_usbhost_p1_fck;
432 }
433
434 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
435 if (IS_ERR(omap->usbhost_p2_fck)) {
436 ret = PTR_ERR(omap->usbhost_p2_fck);
437 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
438 goto err_usbtll_p1_fck;
439 }
440
441 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
442 if (IS_ERR(omap->usbtll_p2_fck)) {
443 ret = PTR_ERR(omap->usbtll_p2_fck);
444 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
445 goto err_usbhost_p2_fck;
446 }
447
448 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
449 if (IS_ERR(omap->init_60m_fclk)) {
450 ret = PTR_ERR(omap->init_60m_fclk);
451 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
452 goto err_usbtll_p2_fck;
453 }
454
455 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
456 if (!res) {
457 dev_err(dev, "UHH EHCI get resource failed\n");
458 ret = -ENODEV;
459 goto err_init_60m_fclk;
460 }
461
462 omap->uhh_base = ioremap(res->start, resource_size(res));
463 if (!omap->uhh_base) {
464 dev_err(dev, "UHH ioremap failed\n");
465 ret = -ENOMEM;
466 goto err_init_60m_fclk;
467 }
468
469 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
470 if (!res) {
471 dev_err(dev, "UHH EHCI get resource failed\n");
472 ret = -ENODEV;
473 goto err_tll;
474 }
475
476 omap->tll_base = ioremap(res->start, resource_size(res));
477 if (!omap->tll_base) {
478 dev_err(dev, "TLL ioremap failed\n");
479 ret = -ENOMEM;
480 goto err_tll;
481 }
482
483 platform_set_drvdata(pdev, omap);
484
485 ret = omap_usbhs_alloc_children(pdev);
486 if (ret) {
487 dev_err(dev, "omap_usbhs_alloc_children failed\n");
488 goto err_alloc;
489 }
490
491 goto end_probe;
492
493 err_alloc:
494 iounmap(omap->tll_base);
495
496 err_tll:
497 iounmap(omap->uhh_base);
498
499 err_init_60m_fclk:
500 clk_put(omap->init_60m_fclk);
501
502 err_usbtll_p2_fck:
503 clk_put(omap->usbtll_p2_fck);
504
505 err_usbhost_p2_fck:
506 clk_put(omap->usbhost_p2_fck);
507
508 err_usbtll_p1_fck:
509 clk_put(omap->usbtll_p1_fck);
510
511 err_usbhost_p1_fck:
512 clk_put(omap->usbhost_p1_fck);
513
514 err_xclk60mhsp2_ck:
515 clk_put(omap->xclk60mhsp2_ck);
516
517 err_utmi_p2_fck:
518 clk_put(omap->utmi_p2_fck);
519
520 err_xclk60mhsp1_ck:
521 clk_put(omap->xclk60mhsp1_ck);
522
523 err_utmi_p1_fck:
524 clk_put(omap->utmi_p1_fck);
525
526 err_usbtll_ick:
527 clk_put(omap->usbtll_ick);
528
529 err_usbtll_fck:
530 clk_put(omap->usbtll_fck);
531
532 err_usbhost_fs_fck:
533 clk_put(omap->usbhost_fs_fck);
534
535 err_usbhost_hs_fck:
536 clk_put(omap->usbhost_hs_fck);
537
538 err_usbhost_ick:
539 clk_put(omap->usbhost_ick);
540
541 err_end:
542 kfree(omap);
543
544 end_probe:
545 return ret;
546 }
547
548 /**
549 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
550 * @pdev: USB Host Controller being removed
551 *
552 * Reverses the effect of usbhs_omap_probe().
553 */
554 static int __devexit usbhs_omap_remove(struct platform_device *pdev)
555 {
556 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
557
558 if (omap->count != 0) {
559 dev_err(&pdev->dev,
560 "Either EHCI or OHCI is still using usbhs core\n");
561 return -EBUSY;
562 }
563
564 iounmap(omap->tll_base);
565 iounmap(omap->uhh_base);
566 clk_put(omap->init_60m_fclk);
567 clk_put(omap->usbtll_p2_fck);
568 clk_put(omap->usbhost_p2_fck);
569 clk_put(omap->usbtll_p1_fck);
570 clk_put(omap->usbhost_p1_fck);
571 clk_put(omap->xclk60mhsp2_ck);
572 clk_put(omap->utmi_p2_fck);
573 clk_put(omap->xclk60mhsp1_ck);
574 clk_put(omap->utmi_p1_fck);
575 clk_put(omap->usbtll_ick);
576 clk_put(omap->usbtll_fck);
577 clk_put(omap->usbhost_fs_fck);
578 clk_put(omap->usbhost_hs_fck);
579 clk_put(omap->usbhost_ick);
580 kfree(omap);
581
582 return 0;
583 }
584
585 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
586 {
587 switch (pmode) {
588 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
589 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
590 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
591 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
592 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
593 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
594 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
595 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
596 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
597 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
598 return true;
599
600 default:
601 return false;
602 }
603 }
604
605 /*
606 * convert the port-mode enum to a value we can use in the FSLSMODE
607 * field of USBTLL_CHANNEL_CONF
608 */
609 static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
610 {
611 switch (mode) {
612 case OMAP_USBHS_PORT_MODE_UNUSED:
613 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
614 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
615
616 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
617 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
618
619 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
620 return OMAP_TLL_FSLSMODE_3PIN_PHY;
621
622 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
623 return OMAP_TLL_FSLSMODE_4PIN_PHY;
624
625 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
626 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
627
628 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
629 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
630
631 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
632 return OMAP_TLL_FSLSMODE_3PIN_TLL;
633
634 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
635 return OMAP_TLL_FSLSMODE_4PIN_TLL;
636
637 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
638 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
639
640 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
641 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
642 default:
643 pr_warning("Invalid port mode, using default\n");
644 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
645 }
646 }
647
648 static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
649 {
650 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
651 struct usbhs_omap_platform_data *pdata = dev->platform_data;
652 unsigned reg;
653 int i;
654
655 /* Program Common TLL register */
656 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
657 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
658 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
659 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
660 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
661
662 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
663
664 /* Enable channels now */
665 for (i = 0; i < tll_channel_count; i++) {
666 reg = usbhs_read(omap->tll_base,
667 OMAP_TLL_CHANNEL_CONF(i));
668
669 if (is_ohci_port(pdata->port_mode[i])) {
670 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
671 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
672 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
673 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
674
675 /* Disable AutoIdle, BitStuffing and use SDR Mode */
676 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
677 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
678 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
679
680 reg |= (1 << (i + 1));
681 } else
682 continue;
683
684 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
685 usbhs_write(omap->tll_base,
686 OMAP_TLL_CHANNEL_CONF(i), reg);
687
688 usbhs_writeb(omap->tll_base,
689 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
690 }
691 }
692
693 static int usbhs_enable(struct device *dev)
694 {
695 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
696 struct usbhs_omap_platform_data *pdata = &omap->platdata;
697 unsigned long flags = 0;
698 int ret = 0;
699 unsigned long timeout;
700 unsigned reg;
701
702 dev_dbg(dev, "starting TI HSUSB Controller\n");
703 if (!pdata) {
704 dev_dbg(dev, "missing platform_data\n");
705 return -ENODEV;
706 }
707
708 spin_lock_irqsave(&omap->lock, flags);
709 if (omap->count > 0)
710 goto end_count;
711
712 clk_enable(omap->usbhost_ick);
713 clk_enable(omap->usbhost_hs_fck);
714 clk_enable(omap->usbhost_fs_fck);
715 clk_enable(omap->usbtll_fck);
716 clk_enable(omap->usbtll_ick);
717
718 if (pdata->ehci_data->phy_reset) {
719 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
720 gpio_request(pdata->ehci_data->reset_gpio_port[0],
721 "USB1 PHY reset");
722 gpio_direction_output
723 (pdata->ehci_data->reset_gpio_port[0], 0);
724 }
725
726 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
727 gpio_request(pdata->ehci_data->reset_gpio_port[1],
728 "USB2 PHY reset");
729 gpio_direction_output
730 (pdata->ehci_data->reset_gpio_port[1], 0);
731 }
732
733 /* Hold the PHY in RESET for enough time till DIR is high */
734 udelay(10);
735 }
736
737 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
738 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
739
740 /* perform TLL soft reset, and wait until reset is complete */
741 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
742 OMAP_USBTLL_SYSCONFIG_SOFTRESET);
743
744 /* Wait for TLL reset to complete */
745 timeout = jiffies + msecs_to_jiffies(1000);
746 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
747 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
748 cpu_relax();
749
750 if (time_after(jiffies, timeout)) {
751 dev_dbg(dev, "operation timed out\n");
752 ret = -EINVAL;
753 goto err_tll;
754 }
755 }
756
757 dev_dbg(dev, "TLL RESET DONE\n");
758
759 /* (1<<3) = no idle mode only for initial debugging */
760 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
761 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
762 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
763 OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
764
765 /* Put UHH in NoIdle/NoStandby mode */
766 reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
767 if (is_omap_usbhs_rev1(omap)) {
768 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
769 | OMAP_UHH_SYSCONFIG_SIDLEMODE
770 | OMAP_UHH_SYSCONFIG_CACTIVITY
771 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
772 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
773
774
775 } else if (is_omap_usbhs_rev2(omap)) {
776 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
777 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
778 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
779 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
780 }
781
782 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
783
784 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
785 /* setup ULPI bypass and burst configurations */
786 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
787 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
788 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
789 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
790 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
791
792 if (is_omap_usbhs_rev1(omap)) {
793 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
794 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
795 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
796 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
797 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
798 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
799
800 /* Bypass the TLL module for PHY mode operation */
801 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
802 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
803 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
804 is_ehci_phy_mode(pdata->port_mode[1]) ||
805 is_ehci_phy_mode(pdata->port_mode[2]))
806 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
807 else
808 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
809 } else {
810 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
811 if (is_ehci_phy_mode(pdata->port_mode[0]))
812 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
813 else
814 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
815 if (is_ehci_phy_mode(pdata->port_mode[1]))
816 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
817 else
818 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
819 if (is_ehci_phy_mode(pdata->port_mode[2]))
820 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
821 else
822 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
823 }
824 } else if (is_omap_usbhs_rev2(omap)) {
825 /* Clear port mode fields for PHY mode*/
826 reg &= ~OMAP4_P1_MODE_CLEAR;
827 reg &= ~OMAP4_P2_MODE_CLEAR;
828
829 if (is_ehci_phy_mode(pdata->port_mode[0])) {
830 ret = clk_set_parent(omap->utmi_p1_fck,
831 omap->xclk60mhsp1_ck);
832 if (ret != 0) {
833 dev_err(dev, "xclk60mhsp1_ck set parent"
834 "failed error:%d\n", ret);
835 goto err_tll;
836 }
837 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
838 ret = clk_set_parent(omap->utmi_p1_fck,
839 omap->init_60m_fclk);
840 if (ret != 0) {
841 dev_err(dev, "init_60m_fclk set parent"
842 "failed error:%d\n", ret);
843 goto err_tll;
844 }
845 clk_enable(omap->usbhost_p1_fck);
846 clk_enable(omap->usbtll_p1_fck);
847 }
848
849 if (is_ehci_phy_mode(pdata->port_mode[1])) {
850 ret = clk_set_parent(omap->utmi_p2_fck,
851 omap->xclk60mhsp2_ck);
852 if (ret != 0) {
853 dev_err(dev, "xclk60mhsp1_ck set parent"
854 "failed error:%d\n", ret);
855 goto err_tll;
856 }
857 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
858 ret = clk_set_parent(omap->utmi_p2_fck,
859 omap->init_60m_fclk);
860 if (ret != 0) {
861 dev_err(dev, "init_60m_fclk set parent"
862 "failed error:%d\n", ret);
863 goto err_tll;
864 }
865 clk_enable(omap->usbhost_p2_fck);
866 clk_enable(omap->usbtll_p2_fck);
867 }
868
869 clk_enable(omap->utmi_p1_fck);
870 clk_enable(omap->utmi_p2_fck);
871
872 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
873 (is_ohci_port(pdata->port_mode[0])))
874 reg |= OMAP4_P1_MODE_TLL;
875 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
876 reg |= OMAP4_P1_MODE_HSIC;
877
878 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
879 (is_ohci_port(pdata->port_mode[1])))
880 reg |= OMAP4_P2_MODE_TLL;
881 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
882 reg |= OMAP4_P2_MODE_HSIC;
883 }
884
885 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
886 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
887
888 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
889 is_ehci_tll_mode(pdata->port_mode[1]) ||
890 is_ehci_tll_mode(pdata->port_mode[2]) ||
891 (is_ohci_port(pdata->port_mode[0])) ||
892 (is_ohci_port(pdata->port_mode[1])) ||
893 (is_ohci_port(pdata->port_mode[2]))) {
894
895 /* Enable UTMI mode for required TLL channels */
896 if (is_omap_usbhs_rev2(omap))
897 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
898 else
899 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
900 }
901
902 if (pdata->ehci_data->phy_reset) {
903 /* Hold the PHY in RESET for enough time till
904 * PHY is settled and ready
905 */
906 udelay(10);
907
908 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
909 gpio_set_value
910 (pdata->ehci_data->reset_gpio_port[0], 1);
911
912 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
913 gpio_set_value
914 (pdata->ehci_data->reset_gpio_port[1], 1);
915 }
916
917 end_count:
918 omap->count++;
919 spin_unlock_irqrestore(&omap->lock, flags);
920 return 0;
921
922 err_tll:
923 if (pdata->ehci_data->phy_reset) {
924 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
925 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
926
927 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
928 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
929 }
930
931 clk_disable(omap->usbtll_ick);
932 clk_disable(omap->usbtll_fck);
933 clk_disable(omap->usbhost_fs_fck);
934 clk_disable(omap->usbhost_hs_fck);
935 clk_disable(omap->usbhost_ick);
936 spin_unlock_irqrestore(&omap->lock, flags);
937 return ret;
938 }
939
940 static void usbhs_disable(struct device *dev)
941 {
942 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
943 struct usbhs_omap_platform_data *pdata = &omap->platdata;
944 unsigned long flags = 0;
945 unsigned long timeout;
946
947 dev_dbg(dev, "stopping TI HSUSB Controller\n");
948
949 spin_lock_irqsave(&omap->lock, flags);
950
951 if (omap->count == 0)
952 goto end_disble;
953
954 omap->count--;
955
956 if (omap->count != 0)
957 goto end_disble;
958
959 /* Reset OMAP modules for insmod/rmmod to work */
960 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
961 is_omap_usbhs_rev2(omap) ?
962 OMAP4_UHH_SYSCONFIG_SOFTRESET :
963 OMAP_UHH_SYSCONFIG_SOFTRESET);
964
965 timeout = jiffies + msecs_to_jiffies(100);
966 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
967 & (1 << 0))) {
968 cpu_relax();
969
970 if (time_after(jiffies, timeout))
971 dev_dbg(dev, "operation timed out\n");
972 }
973
974 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
975 & (1 << 1))) {
976 cpu_relax();
977
978 if (time_after(jiffies, timeout))
979 dev_dbg(dev, "operation timed out\n");
980 }
981
982 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
983 & (1 << 2))) {
984 cpu_relax();
985
986 if (time_after(jiffies, timeout))
987 dev_dbg(dev, "operation timed out\n");
988 }
989
990 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
991
992 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
993 & (1 << 0))) {
994 cpu_relax();
995
996 if (time_after(jiffies, timeout))
997 dev_dbg(dev, "operation timed out\n");
998 }
999
1000 if (is_omap_usbhs_rev2(omap)) {
1001 if (is_ehci_tll_mode(pdata->port_mode[0]))
1002 clk_disable(omap->usbtll_p1_fck);
1003 if (is_ehci_tll_mode(pdata->port_mode[1]))
1004 clk_disable(omap->usbtll_p2_fck);
1005 clk_disable(omap->utmi_p2_fck);
1006 clk_disable(omap->utmi_p1_fck);
1007 }
1008
1009 clk_disable(omap->usbtll_ick);
1010 clk_disable(omap->usbtll_fck);
1011 clk_disable(omap->usbhost_fs_fck);
1012 clk_disable(omap->usbhost_hs_fck);
1013 clk_disable(omap->usbhost_ick);
1014
1015 /* The gpio_free migh sleep; so unlock the spinlock */
1016 spin_unlock_irqrestore(&omap->lock, flags);
1017
1018 if (pdata->ehci_data->phy_reset) {
1019 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
1020 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
1021
1022 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
1023 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
1024 }
1025 return;
1026
1027 end_disble:
1028 spin_unlock_irqrestore(&omap->lock, flags);
1029 }
1030
1031 int omap_usbhs_enable(struct device *dev)
1032 {
1033 return usbhs_enable(dev->parent);
1034 }
1035 EXPORT_SYMBOL_GPL(omap_usbhs_enable);
1036
1037 void omap_usbhs_disable(struct device *dev)
1038 {
1039 usbhs_disable(dev->parent);
1040 }
1041 EXPORT_SYMBOL_GPL(omap_usbhs_disable);
1042
1043 static struct platform_driver usbhs_omap_driver = {
1044 .driver = {
1045 .name = (char *)usbhs_driver_name,
1046 .owner = THIS_MODULE,
1047 },
1048 .remove = __exit_p(usbhs_omap_remove),
1049 };
1050
1051 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
1052 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
1053 MODULE_LICENSE("GPL v2");
1054 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
1055
1056 static int __init omap_usbhs_drvinit(void)
1057 {
1058 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
1059 }
1060
1061 /*
1062 * init before ehci and ohci drivers;
1063 * The usbhs core driver should be initialized much before
1064 * the omap ehci and ohci probe functions are called.
1065 */
1066 fs_initcall(omap_usbhs_drvinit);
1067
1068 static void __exit omap_usbhs_drvexit(void)
1069 {
1070 platform_driver_unregister(&usbhs_omap_driver);
1071 }
1072 module_exit(omap_usbhs_drvexit);
linux-next