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include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / mmc / host / sdhci-pci.c
blob25513262b7d5fe472876d43448a60b21ce8147ec
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/pci.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/device.h>
21 #include <linux/mmc/host.h>
22 #include <linux/scatterlist.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25
26 #include "sdhci.h"
27
28 /*
29 * PCI registers
30 */
31
32 #define PCI_SDHCI_IFPIO 0x00
33 #define PCI_SDHCI_IFDMA 0x01
34 #define PCI_SDHCI_IFVENDOR 0x02
35
36 #define PCI_SLOT_INFO 0x40 /* 8 bits */
37 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
38 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
39
40 #define MAX_SLOTS 8
41
42 struct sdhci_pci_chip;
43 struct sdhci_pci_slot;
44
45 struct sdhci_pci_fixes {
46 unsigned int quirks;
47
48 int (*probe) (struct sdhci_pci_chip *);
49
50 int (*probe_slot) (struct sdhci_pci_slot *);
51 void (*remove_slot) (struct sdhci_pci_slot *, int);
52
53 int (*suspend) (struct sdhci_pci_chip *,
54 pm_message_t);
55 int (*resume) (struct sdhci_pci_chip *);
56 };
57
58 struct sdhci_pci_slot {
59 struct sdhci_pci_chip *chip;
60 struct sdhci_host *host;
61
62 int pci_bar;
63 };
64
65 struct sdhci_pci_chip {
66 struct pci_dev *pdev;
67
68 unsigned int quirks;
69 const struct sdhci_pci_fixes *fixes;
70
71 int num_slots; /* Slots on controller */
72 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
73 };
74
75
76 /*****************************************************************************\
77 * *
78 * Hardware specific quirk handling *
79 * *
80 \*****************************************************************************/
81
82 static int ricoh_probe(struct sdhci_pci_chip *chip)
83 {
84 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
85 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
86 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
87 return 0;
88 }
89
90 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
91 {
92 slot->host->caps =
93 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
94 & SDHCI_TIMEOUT_CLK_MASK) |
95
96 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
97 & SDHCI_CLOCK_BASE_MASK) |
98
99 SDHCI_TIMEOUT_CLK_UNIT |
100 SDHCI_CAN_VDD_330 |
101 SDHCI_CAN_DO_SDMA;
102 return 0;
103 }
104
105 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
106 {
107 /* Apply a delay to allow controller to settle */
108 /* Otherwise it becomes confused if card state changed
109 during suspend */
110 msleep(500);
111 return 0;
112 }
113
114 static const struct sdhci_pci_fixes sdhci_ricoh = {
115 .probe = ricoh_probe,
116 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
117 SDHCI_QUIRK_FORCE_DMA |
118 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
119 };
120
121 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
122 .probe_slot = ricoh_mmc_probe_slot,
123 .resume = ricoh_mmc_resume,
124 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
125 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
126 SDHCI_QUIRK_NO_CARD_NO_RESET |
127 SDHCI_QUIRK_MISSING_CAPS
128 };
129
130 static const struct sdhci_pci_fixes sdhci_ene_712 = {
131 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
132 SDHCI_QUIRK_BROKEN_DMA,
133 };
134
135 static const struct sdhci_pci_fixes sdhci_ene_714 = {
136 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
137 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
138 SDHCI_QUIRK_BROKEN_DMA,
139 };
140
141 static const struct sdhci_pci_fixes sdhci_cafe = {
142 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
143 SDHCI_QUIRK_NO_BUSY_IRQ |
144 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
145 };
146
147 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
148 {
149 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
150 return 0;
151 }
152
153 /*
154 * ADMA operation is disabled for Moorestown platform due to
155 * hardware bugs.
156 */
157 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
158 {
159 /*
160 * slots number is fixed here for MRST as SDIO3/5 are never used and
161 * have hardware bugs.
162 */
163 chip->num_slots = 1;
164 return 0;
165 }
166
167 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
168 {
169 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
170 return 0;
171 }
172
173 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
174 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
175 .probe_slot = mrst_hc_probe_slot,
176 };
177
178 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
179 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
180 .probe = mrst_hc_probe,
181 };
182
183 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
184 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
185 };
186
187 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
188 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
189 };
190
191 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
192 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
193 .probe_slot = mfd_emmc_probe_slot,
194 };
195
196 /* O2Micro extra registers */
197 #define O2_SD_LOCK_WP 0xD3
198 #define O2_SD_MULTI_VCC3V 0xEE
199 #define O2_SD_CLKREQ 0xEC
200 #define O2_SD_CAPS 0xE0
201 #define O2_SD_ADMA1 0xE2
202 #define O2_SD_ADMA2 0xE7
203 #define O2_SD_INF_MOD 0xF1
204
205 static int o2_probe(struct sdhci_pci_chip *chip)
206 {
207 int ret;
208 u8 scratch;
209
210 switch (chip->pdev->device) {
211 case PCI_DEVICE_ID_O2_8220:
212 case PCI_DEVICE_ID_O2_8221:
213 case PCI_DEVICE_ID_O2_8320:
214 case PCI_DEVICE_ID_O2_8321:
215 /* This extra setup is required due to broken ADMA. */
216 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
217 if (ret)
218 return ret;
219 scratch &= 0x7f;
220 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
221
222 /* Set Multi 3 to VCC3V# */
223 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
224
225 /* Disable CLK_REQ# support after media DET */
226 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
227 if (ret)
228 return ret;
229 scratch |= 0x20;
230 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
231
232 /* Choose capabilities, enable SDMA. We have to write 0x01
233 * to the capabilities register first to unlock it.
234 */
235 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
236 if (ret)
237 return ret;
238 scratch |= 0x01;
239 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
240 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
241
242 /* Disable ADMA1/2 */
243 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
244 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
245
246 /* Disable the infinite transfer mode */
247 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
248 if (ret)
249 return ret;
250 scratch |= 0x08;
251 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
252
253 /* Lock WP */
254 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
255 if (ret)
256 return ret;
257 scratch |= 0x80;
258 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
259 }
260
261 return 0;
262 }
263
264 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
265 {
266 u8 scratch;
267 int ret;
268
269 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
270 if (ret)
271 return ret;
272
273 /*
274 * Turn PMOS on [bit 0], set over current detection to 2.4 V
275 * [bit 1:2] and enable over current debouncing [bit 6].
276 */
277 if (on)
278 scratch |= 0x47;
279 else
280 scratch &= ~0x47;
281
282 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
283 if (ret)
284 return ret;
285
286 return 0;
287 }
288
289 static int jmicron_probe(struct sdhci_pci_chip *chip)
290 {
291 int ret;
292 u16 mmcdev = 0;
293
294 if (chip->pdev->revision == 0) {
295 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
296 SDHCI_QUIRK_32BIT_DMA_SIZE |
297 SDHCI_QUIRK_32BIT_ADMA_SIZE |
298 SDHCI_QUIRK_RESET_AFTER_REQUEST |
299 SDHCI_QUIRK_BROKEN_SMALL_PIO;
300 }
301
302 /*
303 * JMicron chips can have two interfaces to the same hardware
304 * in order to work around limitations in Microsoft's driver.
305 * We need to make sure we only bind to one of them.
306 *
307 * This code assumes two things:
308 *
309 * 1. The PCI code adds subfunctions in order.
310 *
311 * 2. The MMC interface has a lower subfunction number
312 * than the SD interface.
313 */
314 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
315 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
316 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
317 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
318
319 if (mmcdev) {
320 struct pci_dev *sd_dev;
321
322 sd_dev = NULL;
323 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
324 mmcdev, sd_dev)) != NULL) {
325 if ((PCI_SLOT(chip->pdev->devfn) ==
326 PCI_SLOT(sd_dev->devfn)) &&
327 (chip->pdev->bus == sd_dev->bus))
328 break;
329 }
330
331 if (sd_dev) {
332 pci_dev_put(sd_dev);
333 dev_info(&chip->pdev->dev, "Refusing to bind to "
334 "secondary interface.\n");
335 return -ENODEV;
336 }
337 }
338
339 /*
340 * JMicron chips need a bit of a nudge to enable the power
341 * output pins.
342 */
343 ret = jmicron_pmos(chip, 1);
344 if (ret) {
345 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
346 return ret;
347 }
348
349 /* quirk for unsable RO-detection on JM388 chips */
350 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
351 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
352 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
353
354 return 0;
355 }
356
357 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
358 {
359 u8 scratch;
360
361 scratch = readb(host->ioaddr + 0xC0);
362
363 if (on)
364 scratch |= 0x01;
365 else
366 scratch &= ~0x01;
367
368 writeb(scratch, host->ioaddr + 0xC0);
369 }
370
371 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
372 {
373 if (slot->chip->pdev->revision == 0) {
374 u16 version;
375
376 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
377 version = (version & SDHCI_VENDOR_VER_MASK) >>
378 SDHCI_VENDOR_VER_SHIFT;
379
380 /*
381 * Older versions of the chip have lots of nasty glitches
382 * in the ADMA engine. It's best just to avoid it
383 * completely.
384 */
385 if (version < 0xAC)
386 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
387 }
388
389 /* JM388 MMC doesn't support 1.8V while SD supports it */
390 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
391 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
392 MMC_VDD_29_30 | MMC_VDD_30_31 |
393 MMC_VDD_165_195; /* allow 1.8V */
394 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
395 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
396 }
397
398 /*
399 * The secondary interface requires a bit set to get the
400 * interrupts.
401 */
402 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
403 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
404 jmicron_enable_mmc(slot->host, 1);
405
406 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
407
408 return 0;
409 }
410
411 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
412 {
413 if (dead)
414 return;
415
416 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
417 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
418 jmicron_enable_mmc(slot->host, 0);
419 }
420
421 static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
422 {
423 int i;
424
425 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
426 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
427 for (i = 0; i < chip->num_slots; i++)
428 jmicron_enable_mmc(chip->slots[i]->host, 0);
429 }
430
431 return 0;
432 }
433
434 static int jmicron_resume(struct sdhci_pci_chip *chip)
435 {
436 int ret, i;
437
438 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
439 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
440 for (i = 0; i < chip->num_slots; i++)
441 jmicron_enable_mmc(chip->slots[i]->host, 1);
442 }
443
444 ret = jmicron_pmos(chip, 1);
445 if (ret) {
446 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
447 return ret;
448 }
449
450 return 0;
451 }
452
453 static const struct sdhci_pci_fixes sdhci_o2 = {
454 .probe = o2_probe,
455 };
456
457 static const struct sdhci_pci_fixes sdhci_jmicron = {
458 .probe = jmicron_probe,
459
460 .probe_slot = jmicron_probe_slot,
461 .remove_slot = jmicron_remove_slot,
462
463 .suspend = jmicron_suspend,
464 .resume = jmicron_resume,
465 };
466
467 /* SysKonnect CardBus2SDIO extra registers */
468 #define SYSKT_CTRL 0x200
469 #define SYSKT_RDFIFO_STAT 0x204
470 #define SYSKT_WRFIFO_STAT 0x208
471 #define SYSKT_POWER_DATA 0x20c
472 #define SYSKT_POWER_330 0xef
473 #define SYSKT_POWER_300 0xf8
474 #define SYSKT_POWER_184 0xcc
475 #define SYSKT_POWER_CMD 0x20d
476 #define SYSKT_POWER_START (1 << 7)
477 #define SYSKT_POWER_STATUS 0x20e
478 #define SYSKT_POWER_STATUS_OK (1 << 0)
479 #define SYSKT_BOARD_REV 0x210
480 #define SYSKT_CHIP_REV 0x211
481 #define SYSKT_CONF_DATA 0x212
482 #define SYSKT_CONF_DATA_1V8 (1 << 2)
483 #define SYSKT_CONF_DATA_2V5 (1 << 1)
484 #define SYSKT_CONF_DATA_3V3 (1 << 0)
485
486 static int syskt_probe(struct sdhci_pci_chip *chip)
487 {
488 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
489 chip->pdev->class &= ~0x0000FF;
490 chip->pdev->class |= PCI_SDHCI_IFDMA;
491 }
492 return 0;
493 }
494
495 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
496 {
497 int tm, ps;
498
499 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
500 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
501 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
502 "board rev %d.%d, chip rev %d.%d\n",
503 board_rev >> 4, board_rev & 0xf,
504 chip_rev >> 4, chip_rev & 0xf);
505 if (chip_rev >= 0x20)
506 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
507
508 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
509 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
510 udelay(50);
511 tm = 10; /* Wait max 1 ms */
512 do {
513 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
514 if (ps & SYSKT_POWER_STATUS_OK)
515 break;
516 udelay(100);
517 } while (--tm);
518 if (!tm) {
519 dev_err(&slot->chip->pdev->dev,
520 "power regulator never stabilized");
521 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
522 return -ENODEV;
523 }
524
525 return 0;
526 }
527
528 static const struct sdhci_pci_fixes sdhci_syskt = {
529 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
530 .probe = syskt_probe,
531 .probe_slot = syskt_probe_slot,
532 };
533
534 static int via_probe(struct sdhci_pci_chip *chip)
535 {
536 if (chip->pdev->revision == 0x10)
537 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
538
539 return 0;
540 }
541
542 static const struct sdhci_pci_fixes sdhci_via = {
543 .probe = via_probe,
544 };
545
546 static const struct pci_device_id pci_ids[] __devinitdata = {
547 {
548 .vendor = PCI_VENDOR_ID_RICOH,
549 .device = PCI_DEVICE_ID_RICOH_R5C822,
550 .subvendor = PCI_ANY_ID,
551 .subdevice = PCI_ANY_ID,
552 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
553 },
554
555 {
556 .vendor = PCI_VENDOR_ID_RICOH,
557 .device = 0x843,
558 .subvendor = PCI_ANY_ID,
559 .subdevice = PCI_ANY_ID,
560 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
561 },
562
563 {
564 .vendor = PCI_VENDOR_ID_RICOH,
565 .device = 0xe822,
566 .subvendor = PCI_ANY_ID,
567 .subdevice = PCI_ANY_ID,
568 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
569 },
570
571 {
572 .vendor = PCI_VENDOR_ID_RICOH,
573 .device = 0xe823,
574 .subvendor = PCI_ANY_ID,
575 .subdevice = PCI_ANY_ID,
576 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
577 },
578
579 {
580 .vendor = PCI_VENDOR_ID_ENE,
581 .device = PCI_DEVICE_ID_ENE_CB712_SD,
582 .subvendor = PCI_ANY_ID,
583 .subdevice = PCI_ANY_ID,
584 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
585 },
586
587 {
588 .vendor = PCI_VENDOR_ID_ENE,
589 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
590 .subvendor = PCI_ANY_ID,
591 .subdevice = PCI_ANY_ID,
592 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
593 },
594
595 {
596 .vendor = PCI_VENDOR_ID_ENE,
597 .device = PCI_DEVICE_ID_ENE_CB714_SD,
598 .subvendor = PCI_ANY_ID,
599 .subdevice = PCI_ANY_ID,
600 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
601 },
602
603 {
604 .vendor = PCI_VENDOR_ID_ENE,
605 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
606 .subvendor = PCI_ANY_ID,
607 .subdevice = PCI_ANY_ID,
608 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
609 },
610
611 {
612 .vendor = PCI_VENDOR_ID_MARVELL,
613 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
614 .subvendor = PCI_ANY_ID,
615 .subdevice = PCI_ANY_ID,
616 .driver_data = (kernel_ulong_t)&sdhci_cafe,
617 },
618
619 {
620 .vendor = PCI_VENDOR_ID_JMICRON,
621 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
622 .subvendor = PCI_ANY_ID,
623 .subdevice = PCI_ANY_ID,
624 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
625 },
626
627 {
628 .vendor = PCI_VENDOR_ID_JMICRON,
629 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
630 .subvendor = PCI_ANY_ID,
631 .subdevice = PCI_ANY_ID,
632 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
633 },
634
635 {
636 .vendor = PCI_VENDOR_ID_JMICRON,
637 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
638 .subvendor = PCI_ANY_ID,
639 .subdevice = PCI_ANY_ID,
640 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
641 },
642
643 {
644 .vendor = PCI_VENDOR_ID_JMICRON,
645 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
646 .subvendor = PCI_ANY_ID,
647 .subdevice = PCI_ANY_ID,
648 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
649 },
650
651 {
652 .vendor = PCI_VENDOR_ID_SYSKONNECT,
653 .device = 0x8000,
654 .subvendor = PCI_ANY_ID,
655 .subdevice = PCI_ANY_ID,
656 .driver_data = (kernel_ulong_t)&sdhci_syskt,
657 },
658
659 {
660 .vendor = PCI_VENDOR_ID_VIA,
661 .device = 0x95d0,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 .driver_data = (kernel_ulong_t)&sdhci_via,
665 },
666
667 {
668 .vendor = PCI_VENDOR_ID_INTEL,
669 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
673 },
674
675 {
676 .vendor = PCI_VENDOR_ID_INTEL,
677 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
678 .subvendor = PCI_ANY_ID,
679 .subdevice = PCI_ANY_ID,
680 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
681 },
682
683 {
684 .vendor = PCI_VENDOR_ID_INTEL,
685 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
686 .subvendor = PCI_ANY_ID,
687 .subdevice = PCI_ANY_ID,
688 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
689 },
690
691 {
692 .vendor = PCI_VENDOR_ID_INTEL,
693 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
694 .subvendor = PCI_ANY_ID,
695 .subdevice = PCI_ANY_ID,
696 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
697 },
698
699 {
700 .vendor = PCI_VENDOR_ID_INTEL,
701 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
702 .subvendor = PCI_ANY_ID,
703 .subdevice = PCI_ANY_ID,
704 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
705 },
706
707 {
708 .vendor = PCI_VENDOR_ID_INTEL,
709 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
710 .subvendor = PCI_ANY_ID,
711 .subdevice = PCI_ANY_ID,
712 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
713 },
714
715 {
716 .vendor = PCI_VENDOR_ID_INTEL,
717 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
718 .subvendor = PCI_ANY_ID,
719 .subdevice = PCI_ANY_ID,
720 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
721 },
722
723 {
724 .vendor = PCI_VENDOR_ID_INTEL,
725 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
726 .subvendor = PCI_ANY_ID,
727 .subdevice = PCI_ANY_ID,
728 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
729 },
730
731 {
732 .vendor = PCI_VENDOR_ID_O2,
733 .device = PCI_DEVICE_ID_O2_8120,
734 .subvendor = PCI_ANY_ID,
735 .subdevice = PCI_ANY_ID,
736 .driver_data = (kernel_ulong_t)&sdhci_o2,
737 },
738
739 {
740 .vendor = PCI_VENDOR_ID_O2,
741 .device = PCI_DEVICE_ID_O2_8220,
742 .subvendor = PCI_ANY_ID,
743 .subdevice = PCI_ANY_ID,
744 .driver_data = (kernel_ulong_t)&sdhci_o2,
745 },
746
747 {
748 .vendor = PCI_VENDOR_ID_O2,
749 .device = PCI_DEVICE_ID_O2_8221,
750 .subvendor = PCI_ANY_ID,
751 .subdevice = PCI_ANY_ID,
752 .driver_data = (kernel_ulong_t)&sdhci_o2,
753 },
754
755 {
756 .vendor = PCI_VENDOR_ID_O2,
757 .device = PCI_DEVICE_ID_O2_8320,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .driver_data = (kernel_ulong_t)&sdhci_o2,
761 },
762
763 {
764 .vendor = PCI_VENDOR_ID_O2,
765 .device = PCI_DEVICE_ID_O2_8321,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .driver_data = (kernel_ulong_t)&sdhci_o2,
769 },
770
771 { /* Generic SD host controller */
772 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
773 },
774
775 { /* end: all zeroes */ },
776 };
777
778 MODULE_DEVICE_TABLE(pci, pci_ids);
779
780 /*****************************************************************************\
781 * *
782 * SDHCI core callbacks *
783 * *
784 \*****************************************************************************/
785
786 static int sdhci_pci_enable_dma(struct sdhci_host *host)
787 {
788 struct sdhci_pci_slot *slot;
789 struct pci_dev *pdev;
790 int ret;
791
792 slot = sdhci_priv(host);
793 pdev = slot->chip->pdev;
794
795 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
796 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
797 (host->flags & SDHCI_USE_SDMA)) {
798 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
799 "doesn't fully claim to support it.\n");
800 }
801
802 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
803 if (ret)
804 return ret;
805
806 pci_set_master(pdev);
807
808 return 0;
809 }
810
811 static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
812 {
813 u8 ctrl;
814
815 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
816
817 switch (width) {
818 case MMC_BUS_WIDTH_8:
819 ctrl |= SDHCI_CTRL_8BITBUS;
820 ctrl &= ~SDHCI_CTRL_4BITBUS;
821 break;
822 case MMC_BUS_WIDTH_4:
823 ctrl |= SDHCI_CTRL_4BITBUS;
824 ctrl &= ~SDHCI_CTRL_8BITBUS;
825 break;
826 default:
827 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
828 break;
829 }
830
831 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
832
833 return 0;
834 }
835
836 static struct sdhci_ops sdhci_pci_ops = {
837 .enable_dma = sdhci_pci_enable_dma,
838 .platform_8bit_width = sdhci_pci_8bit_width,
839 };
840
841 /*****************************************************************************\
842 * *
843 * Suspend/resume *
844 * *
845 \*****************************************************************************/
846
847 #ifdef CONFIG_PM
848
849 static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
850 {
851 struct sdhci_pci_chip *chip;
852 struct sdhci_pci_slot *slot;
853 mmc_pm_flag_t slot_pm_flags;
854 mmc_pm_flag_t pm_flags = 0;
855 int i, ret;
856
857 chip = pci_get_drvdata(pdev);
858 if (!chip)
859 return 0;
860
861 for (i = 0; i < chip->num_slots; i++) {
862 slot = chip->slots[i];
863 if (!slot)
864 continue;
865
866 ret = sdhci_suspend_host(slot->host, state);
867
868 if (ret) {
869 for (i--; i >= 0; i--)
870 sdhci_resume_host(chip->slots[i]->host);
871 return ret;
872 }
873
874 slot_pm_flags = slot->host->mmc->pm_flags;
875 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
876 sdhci_enable_irq_wakeups(slot->host);
877
878 pm_flags |= slot_pm_flags;
879 }
880
881 if (chip->fixes && chip->fixes->suspend) {
882 ret = chip->fixes->suspend(chip, state);
883 if (ret) {
884 for (i = chip->num_slots - 1; i >= 0; i--)
885 sdhci_resume_host(chip->slots[i]->host);
886 return ret;
887 }
888 }
889
890 pci_save_state(pdev);
891 if (pm_flags & MMC_PM_KEEP_POWER) {
892 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
893 pci_pme_active(pdev, true);
894 pci_enable_wake(pdev, PCI_D3hot, 1);
895 }
896 pci_set_power_state(pdev, PCI_D3hot);
897 } else {
898 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
899 pci_disable_device(pdev);
900 pci_set_power_state(pdev, pci_choose_state(pdev, state));
901 }
902
903 return 0;
904 }
905
906 static int sdhci_pci_resume(struct pci_dev *pdev)
907 {
908 struct sdhci_pci_chip *chip;
909 struct sdhci_pci_slot *slot;
910 int i, ret;
911
912 chip = pci_get_drvdata(pdev);
913 if (!chip)
914 return 0;
915
916 pci_set_power_state(pdev, PCI_D0);
917 pci_restore_state(pdev);
918 ret = pci_enable_device(pdev);
919 if (ret)
920 return ret;
921
922 if (chip->fixes && chip->fixes->resume) {
923 ret = chip->fixes->resume(chip);
924 if (ret)
925 return ret;
926 }
927
928 for (i = 0; i < chip->num_slots; i++) {
929 slot = chip->slots[i];
930 if (!slot)
931 continue;
932
933 ret = sdhci_resume_host(slot->host);
934 if (ret)
935 return ret;
936 }
937
938 return 0;
939 }
940
941 #else /* CONFIG_PM */
942
943 #define sdhci_pci_suspend NULL
944 #define sdhci_pci_resume NULL
945
946 #endif /* CONFIG_PM */
947
948 /*****************************************************************************\
949 * *
950 * Device probing/removal *
951 * *
952 \*****************************************************************************/
953
954 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
955 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
956 {
957 struct sdhci_pci_slot *slot;
958 struct sdhci_host *host;
959 int ret;
960
961 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
962 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
963 return ERR_PTR(-ENODEV);
964 }
965
966 if (pci_resource_len(pdev, bar) != 0x100) {
967 dev_err(&pdev->dev, "Invalid iomem size. You may "
968 "experience problems.\n");
969 }
970
971 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
972 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
973 return ERR_PTR(-ENODEV);
974 }
975
976 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
977 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
978 return ERR_PTR(-ENODEV);
979 }
980
981 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
982 if (IS_ERR(host)) {
983 dev_err(&pdev->dev, "cannot allocate host\n");
984 return ERR_CAST(host);
985 }
986
987 slot = sdhci_priv(host);
988
989 slot->chip = chip;
990 slot->host = host;
991 slot->pci_bar = bar;
992
993 host->hw_name = "PCI";
994 host->ops = &sdhci_pci_ops;
995 host->quirks = chip->quirks;
996
997 host->irq = pdev->irq;
998
999 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1000 if (ret) {
1001 dev_err(&pdev->dev, "cannot request region\n");
1002 goto free;
1003 }
1004
1005 host->ioaddr = pci_ioremap_bar(pdev, bar);
1006 if (!host->ioaddr) {
1007 dev_err(&pdev->dev, "failed to remap registers\n");
1008 ret = -ENOMEM;
1009 goto release;
1010 }
1011
1012 if (chip->fixes && chip->fixes->probe_slot) {
1013 ret = chip->fixes->probe_slot(slot);
1014 if (ret)
1015 goto unmap;
1016 }
1017
1018 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1019
1020 ret = sdhci_add_host(host);
1021 if (ret)
1022 goto remove;
1023
1024 return slot;
1025
1026 remove:
1027 if (chip->fixes && chip->fixes->remove_slot)
1028 chip->fixes->remove_slot(slot, 0);
1029
1030 unmap:
1031 iounmap(host->ioaddr);
1032
1033 release:
1034 pci_release_region(pdev, bar);
1035
1036 free:
1037 sdhci_free_host(host);
1038
1039 return ERR_PTR(ret);
1040 }
1041
1042 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1043 {
1044 int dead;
1045 u32 scratch;
1046
1047 dead = 0;
1048 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1049 if (scratch == (u32)-1)
1050 dead = 1;
1051
1052 sdhci_remove_host(slot->host, dead);
1053
1054 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1055 slot->chip->fixes->remove_slot(slot, dead);
1056
1057 pci_release_region(slot->chip->pdev, slot->pci_bar);
1058
1059 sdhci_free_host(slot->host);
1060 }
1061
1062 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1063 const struct pci_device_id *ent)
1064 {
1065 struct sdhci_pci_chip *chip;
1066 struct sdhci_pci_slot *slot;
1067
1068 u8 slots, first_bar;
1069 int ret, i;
1070
1071 BUG_ON(pdev == NULL);
1072 BUG_ON(ent == NULL);
1073
1074 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1075 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1076
1077 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1078 if (ret)
1079 return ret;
1080
1081 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1082 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1083 if (slots == 0)
1084 return -ENODEV;
1085
1086 BUG_ON(slots > MAX_SLOTS);
1087
1088 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1089 if (ret)
1090 return ret;
1091
1092 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1093
1094 if (first_bar > 5) {
1095 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1096 return -ENODEV;
1097 }
1098
1099 ret = pci_enable_device(pdev);
1100 if (ret)
1101 return ret;
1102
1103 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1104 if (!chip) {
1105 ret = -ENOMEM;
1106 goto err;
1107 }
1108
1109 chip->pdev = pdev;
1110 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1111 if (chip->fixes)
1112 chip->quirks = chip->fixes->quirks;
1113 chip->num_slots = slots;
1114
1115 pci_set_drvdata(pdev, chip);
1116
1117 if (chip->fixes && chip->fixes->probe) {
1118 ret = chip->fixes->probe(chip);
1119 if (ret)
1120 goto free;
1121 }
1122
1123 slots = chip->num_slots; /* Quirk may have changed this */
1124
1125 for (i = 0; i < slots; i++) {
1126 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1127 if (IS_ERR(slot)) {
1128 for (i--; i >= 0; i--)
1129 sdhci_pci_remove_slot(chip->slots[i]);
1130 ret = PTR_ERR(slot);
1131 goto free;
1132 }
1133
1134 chip->slots[i] = slot;
1135 }
1136
1137 return 0;
1138
1139 free:
1140 pci_set_drvdata(pdev, NULL);
1141 kfree(chip);
1142
1143 err:
1144 pci_disable_device(pdev);
1145 return ret;
1146 }
1147
1148 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1149 {
1150 int i;
1151 struct sdhci_pci_chip *chip;
1152
1153 chip = pci_get_drvdata(pdev);
1154
1155 if (chip) {
1156 for (i = 0; i < chip->num_slots; i++)
1157 sdhci_pci_remove_slot(chip->slots[i]);
1158
1159 pci_set_drvdata(pdev, NULL);
1160 kfree(chip);
1161 }
1162
1163 pci_disable_device(pdev);
1164 }
1165
1166 static struct pci_driver sdhci_driver = {
1167 .name = "sdhci-pci",
1168 .id_table = pci_ids,
1169 .probe = sdhci_pci_probe,
1170 .remove = __devexit_p(sdhci_pci_remove),
1171 .suspend = sdhci_pci_suspend,
1172 .resume = sdhci_pci_resume,
1173 };
1174
1175 /*****************************************************************************\
1176 * *
1177 * Driver init/exit *
1178 * *
1179 \*****************************************************************************/
1180
1181 static int __init sdhci_drv_init(void)
1182 {
1183 return pci_register_driver(&sdhci_driver);
1184 }
1185
1186 static void __exit sdhci_drv_exit(void)
1187 {
1188 pci_unregister_driver(&sdhci_driver);
1189 }
1190
1191 module_init(sdhci_drv_init);
1192 module_exit(sdhci_drv_exit);
1193
1194 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1195 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1196 MODULE_LICENSE("GPL");
linux-next