1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
24 #include <linux/mmc/host.h>
26 #include <plat/sdhci.h>
27 #include <plat/regs-sdhci.h>
31 #define MAX_BUS_CLK (4)
34 * struct sdhci_s3c - S3C SDHCI instance
35 * @host: The SDHCI host created
36 * @pdev: The platform device we where created from.
37 * @ioarea: The resource created when we claimed the IO area.
38 * @pdata: The platform data for this controller.
39 * @cur_clk: The index of the current bus clock.
40 * @clk_io: The clock for the internal bus interface.
41 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
44 struct sdhci_host
*host
;
45 struct platform_device
*pdev
;
46 struct resource
*ioarea
;
47 struct s3c_sdhci_platdata
*pdata
;
53 struct clk
*clk_bus
[MAX_BUS_CLK
];
56 static inline struct sdhci_s3c
*to_s3c(struct sdhci_host
*host
)
58 return sdhci_priv(host
);
62 * get_curclk - convert ctrl2 register to clock source number
63 * @ctrl2: Control2 register value.
65 static u32
get_curclk(u32 ctrl2
)
67 ctrl2
&= S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
68 ctrl2
>>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
73 static void sdhci_s3c_check_sclk(struct sdhci_host
*host
)
75 struct sdhci_s3c
*ourhost
= to_s3c(host
);
76 u32 tmp
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
78 if (get_curclk(tmp
) != ourhost
->cur_clk
) {
79 dev_dbg(&ourhost
->pdev
->dev
, "restored ctrl2 clock setting\n");
81 tmp
&= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
82 tmp
|= ourhost
->cur_clk
<< S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
83 writel(tmp
, host
->ioaddr
+ 0x80);
88 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
89 * @host: The SDHCI host instance.
91 * Callback to return the maximum clock rate acheivable by the controller.
93 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host
*host
)
95 struct sdhci_s3c
*ourhost
= to_s3c(host
);
97 unsigned int rate
, max
;
100 /* note, a reset will reset the clock source */
102 sdhci_s3c_check_sclk(host
);
104 for (max
= 0, clk
= 0; clk
< MAX_BUS_CLK
; clk
++) {
105 busclk
= ourhost
->clk_bus
[clk
];
109 rate
= clk_get_rate(busclk
);
118 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
119 * @ourhost: Our SDHCI instance.
120 * @src: The source clock index.
121 * @wanted: The clock frequency wanted.
123 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c
*ourhost
,
128 struct clk
*clksrc
= ourhost
->clk_bus
[src
];
135 * Clock divider's step is different as 1 from that of host controller
136 * when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
138 if (ourhost
->pdata
->clk_type
) {
139 rate
= clk_round_rate(clksrc
, wanted
);
140 return wanted
- rate
;
143 rate
= clk_get_rate(clksrc
);
145 for (div
= 1; div
< 256; div
*= 2) {
146 if ((rate
/ div
) <= wanted
)
150 dev_dbg(&ourhost
->pdev
->dev
, "clk %d: rate %ld, want %d, got %ld\n",
151 src
, rate
, wanted
, rate
/ div
);
153 return (wanted
- (rate
/ div
));
157 * sdhci_s3c_set_clock - callback on clock change
158 * @host: The SDHCI host being changed
159 * @clock: The clock rate being requested.
161 * When the card's clock is going to be changed, look at the new frequency
162 * and find the best clock source to go with it.
164 static void sdhci_s3c_set_clock(struct sdhci_host
*host
, unsigned int clock
)
166 struct sdhci_s3c
*ourhost
= to_s3c(host
);
167 unsigned int best
= UINT_MAX
;
173 /* don't bother if the clock is going off. */
177 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
178 delta
= sdhci_s3c_consider_clock(ourhost
, src
, clock
);
185 dev_dbg(&ourhost
->pdev
->dev
,
186 "selected source %d, clock %d, delta %d\n",
187 best_src
, clock
, best
);
189 /* select the new clock source */
191 if (ourhost
->cur_clk
!= best_src
) {
192 struct clk
*clk
= ourhost
->clk_bus
[best_src
];
194 /* turn clock off to card before changing clock source */
195 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
197 ourhost
->cur_clk
= best_src
;
198 host
->max_clk
= clk_get_rate(clk
);
200 ctrl
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
201 ctrl
&= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
202 ctrl
|= best_src
<< S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
203 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
206 /* reconfigure the hardware for new clock rate */
213 if (ourhost
->pdata
->cfg_card
)
214 (ourhost
->pdata
->cfg_card
)(ourhost
->pdev
, host
->ioaddr
,
220 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
221 * @host: The SDHCI host being queried
223 * To init mmc host properly a minimal clock value is needed. For high system
224 * bus clock's values the standard formula gives values out of allowed range.
225 * The clock still can be set to lower values, if clock source other then
226 * system bus is selected.
228 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host
*host
)
230 struct sdhci_s3c
*ourhost
= to_s3c(host
);
231 unsigned int delta
, min
= UINT_MAX
;
234 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
235 delta
= sdhci_s3c_consider_clock(ourhost
, src
, 0);
236 if (delta
== UINT_MAX
)
238 /* delta is a negative value in this case */
245 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
246 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host
*host
)
248 struct sdhci_s3c
*ourhost
= to_s3c(host
);
250 return clk_round_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], UINT_MAX
);
253 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
254 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host
*host
)
256 struct sdhci_s3c
*ourhost
= to_s3c(host
);
259 * initial clock can be in the frequency range of
260 * 100KHz-400KHz, so we set it as max value.
262 return clk_round_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], 400000);
265 /* sdhci_cmu_set_clock - callback on clock change.*/
266 static void sdhci_cmu_set_clock(struct sdhci_host
*host
, unsigned int clock
)
268 struct sdhci_s3c
*ourhost
= to_s3c(host
);
270 /* don't bother if the clock is going off */
274 sdhci_s3c_set_clock(host
, clock
);
276 clk_set_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], clock
);
282 * sdhci_s3c_platform_8bit_width - support 8bit buswidth
283 * @host: The SDHCI host being queried
284 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
286 * We have 8-bit width support but is not a v3 controller.
287 * So we add platform_8bit_width() and support 8bit width.
289 static int sdhci_s3c_platform_8bit_width(struct sdhci_host
*host
, int width
)
293 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
296 case MMC_BUS_WIDTH_8
:
297 ctrl
|= SDHCI_CTRL_8BITBUS
;
298 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
300 case MMC_BUS_WIDTH_4
:
301 ctrl
|= SDHCI_CTRL_4BITBUS
;
302 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
308 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
313 static struct sdhci_ops sdhci_s3c_ops
= {
314 .get_max_clock
= sdhci_s3c_get_max_clk
,
315 .set_clock
= sdhci_s3c_set_clock
,
316 .get_min_clock
= sdhci_s3c_get_min_clock
,
317 .platform_8bit_width
= sdhci_s3c_platform_8bit_width
,
320 static void sdhci_s3c_notify_change(struct platform_device
*dev
, int state
)
322 struct sdhci_host
*host
= platform_get_drvdata(dev
);
326 spin_lock_irqsave(&host
->lock
, flags
);
328 dev_dbg(&dev
->dev
, "card inserted.\n");
329 host
->flags
&= ~SDHCI_DEVICE_DEAD
;
330 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
332 dev_dbg(&dev
->dev
, "card removed.\n");
333 host
->flags
|= SDHCI_DEVICE_DEAD
;
334 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
336 tasklet_schedule(&host
->card_tasklet
);
337 spin_unlock_irqrestore(&host
->lock
, flags
);
341 static irqreturn_t
sdhci_s3c_gpio_card_detect_thread(int irq
, void *dev_id
)
343 struct sdhci_s3c
*sc
= dev_id
;
344 int status
= gpio_get_value(sc
->ext_cd_gpio
);
345 if (sc
->pdata
->ext_cd_gpio_invert
)
347 sdhci_s3c_notify_change(sc
->pdev
, status
);
351 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c
*sc
)
353 struct s3c_sdhci_platdata
*pdata
= sc
->pdata
;
354 struct device
*dev
= &sc
->pdev
->dev
;
356 if (gpio_request(pdata
->ext_cd_gpio
, "SDHCI EXT CD") == 0) {
357 sc
->ext_cd_gpio
= pdata
->ext_cd_gpio
;
358 sc
->ext_cd_irq
= gpio_to_irq(pdata
->ext_cd_gpio
);
359 if (sc
->ext_cd_irq
&&
360 request_threaded_irq(sc
->ext_cd_irq
, NULL
,
361 sdhci_s3c_gpio_card_detect_thread
,
362 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
,
363 dev_name(dev
), sc
) == 0) {
364 int status
= gpio_get_value(sc
->ext_cd_gpio
);
365 if (pdata
->ext_cd_gpio_invert
)
367 sdhci_s3c_notify_change(sc
->pdev
, status
);
369 dev_warn(dev
, "cannot request irq for card detect\n");
373 dev_err(dev
, "cannot request gpio for card detect\n");
377 static int __devinit
sdhci_s3c_probe(struct platform_device
*pdev
)
379 struct s3c_sdhci_platdata
*pdata
= pdev
->dev
.platform_data
;
380 struct device
*dev
= &pdev
->dev
;
381 struct sdhci_host
*host
;
382 struct sdhci_s3c
*sc
;
383 struct resource
*res
;
384 int ret
, irq
, ptr
, clks
;
387 dev_err(dev
, "no device data specified\n");
391 irq
= platform_get_irq(pdev
, 0);
393 dev_err(dev
, "no irq specified\n");
397 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
399 dev_err(dev
, "no memory specified\n");
403 host
= sdhci_alloc_host(dev
, sizeof(struct sdhci_s3c
));
405 dev_err(dev
, "sdhci_alloc_host() failed\n");
406 return PTR_ERR(host
);
409 sc
= sdhci_priv(host
);
414 sc
->ext_cd_gpio
= -1; /* invalid gpio number */
416 platform_set_drvdata(pdev
, host
);
418 sc
->clk_io
= clk_get(dev
, "hsmmc");
419 if (IS_ERR(sc
->clk_io
)) {
420 dev_err(dev
, "failed to get io clock\n");
421 ret
= PTR_ERR(sc
->clk_io
);
425 /* enable the local io clock and keep it running for the moment. */
426 clk_enable(sc
->clk_io
);
428 for (clks
= 0, ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
430 char *name
= pdata
->clocks
[ptr
];
435 clk
= clk_get(dev
, name
);
437 dev_err(dev
, "failed to get clock %s\n", name
);
442 sc
->clk_bus
[ptr
] = clk
;
445 * save current clock index to know which clock bus
446 * is used later in overriding functions.
452 dev_info(dev
, "clock source %d: %s (%ld Hz)\n",
453 ptr
, name
, clk_get_rate(clk
));
457 dev_err(dev
, "failed to find any bus clocks\n");
462 sc
->ioarea
= request_mem_region(res
->start
, resource_size(res
),
463 mmc_hostname(host
->mmc
));
465 dev_err(dev
, "failed to reserve register area\n");
470 host
->ioaddr
= ioremap_nocache(res
->start
, resource_size(res
));
472 dev_err(dev
, "failed to map registers\n");
477 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
479 pdata
->cfg_gpio(pdev
, pdata
->max_width
);
481 host
->hw_name
= "samsung-hsmmc";
482 host
->ops
= &sdhci_s3c_ops
;
486 /* Setup quirks for the controller */
487 host
->quirks
|= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
;
488 host
->quirks
|= SDHCI_QUIRK_NO_HISPD_BIT
;
490 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
492 /* we currently see overruns on errors, so disable the SDMA
493 * support as well. */
494 host
->quirks
|= SDHCI_QUIRK_BROKEN_DMA
;
496 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
498 /* It seems we do not get an DATA transfer complete on non-busy
499 * transfers, not sure if this is a problem with this specific
500 * SDHCI block, or a missing configuration that needs to be set. */
501 host
->quirks
|= SDHCI_QUIRK_NO_BUSY_IRQ
;
503 /* This host supports the Auto CMD12 */
504 host
->quirks
|= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
;
506 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
507 host
->quirks
|= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
;
509 if (pdata
->cd_type
== S3C_SDHCI_CD_NONE
||
510 pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
511 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
513 if (pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
514 host
->mmc
->caps
= MMC_CAP_NONREMOVABLE
;
516 if (pdata
->host_caps
)
517 host
->mmc
->caps
|= pdata
->host_caps
;
519 host
->quirks
|= (SDHCI_QUIRK_32BIT_DMA_ADDR
|
520 SDHCI_QUIRK_32BIT_DMA_SIZE
);
522 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
523 host
->quirks
|= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
;
526 * If controller does not have internal clock divider,
527 * we can use overriding functions instead of default.
529 if (pdata
->clk_type
) {
530 sdhci_s3c_ops
.set_clock
= sdhci_cmu_set_clock
;
531 sdhci_s3c_ops
.get_min_clock
= sdhci_cmu_get_min_clock
;
532 sdhci_s3c_ops
.get_max_clock
= sdhci_cmu_get_max_clock
;
535 /* It supports additional host capabilities if needed */
536 if (pdata
->host_caps
)
537 host
->mmc
->caps
|= pdata
->host_caps
;
539 ret
= sdhci_add_host(host
);
541 dev_err(dev
, "sdhci_add_host() failed\n");
545 /* The following two methods of card detection might call
546 sdhci_s3c_notify_change() immediately, so they can be called
547 only after sdhci_add_host(). Setup errors are ignored. */
548 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_init
)
549 pdata
->ext_cd_init(&sdhci_s3c_notify_change
);
550 if (pdata
->cd_type
== S3C_SDHCI_CD_GPIO
&&
551 gpio_is_valid(pdata
->ext_cd_gpio
))
552 sdhci_s3c_setup_card_detect_gpio(sc
);
557 release_resource(sc
->ioarea
);
561 for (ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
562 clk_disable(sc
->clk_bus
[ptr
]);
563 clk_put(sc
->clk_bus
[ptr
]);
567 clk_disable(sc
->clk_io
);
571 sdhci_free_host(host
);
576 static int __devexit
sdhci_s3c_remove(struct platform_device
*pdev
)
578 struct s3c_sdhci_platdata
*pdata
= pdev
->dev
.platform_data
;
579 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
580 struct sdhci_s3c
*sc
= sdhci_priv(host
);
583 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_cleanup
)
584 pdata
->ext_cd_cleanup(&sdhci_s3c_notify_change
);
587 free_irq(sc
->ext_cd_irq
, sc
);
589 if (gpio_is_valid(sc
->ext_cd_gpio
))
590 gpio_free(sc
->ext_cd_gpio
);
592 sdhci_remove_host(host
, 1);
594 for (ptr
= 0; ptr
< 3; ptr
++) {
595 if (sc
->clk_bus
[ptr
]) {
596 clk_disable(sc
->clk_bus
[ptr
]);
597 clk_put(sc
->clk_bus
[ptr
]);
600 clk_disable(sc
->clk_io
);
603 iounmap(host
->ioaddr
);
604 release_resource(sc
->ioarea
);
607 sdhci_free_host(host
);
608 platform_set_drvdata(pdev
, NULL
);
615 static int sdhci_s3c_suspend(struct platform_device
*dev
, pm_message_t pm
)
617 struct sdhci_host
*host
= platform_get_drvdata(dev
);
619 return sdhci_suspend_host(host
, pm
);
622 static int sdhci_s3c_resume(struct platform_device
*dev
)
624 struct sdhci_host
*host
= platform_get_drvdata(dev
);
626 return sdhci_resume_host(host
);
630 #define sdhci_s3c_suspend NULL
631 #define sdhci_s3c_resume NULL
634 static struct platform_driver sdhci_s3c_driver
= {
635 .probe
= sdhci_s3c_probe
,
636 .remove
= __devexit_p(sdhci_s3c_remove
),
637 .suspend
= sdhci_s3c_suspend
,
638 .resume
= sdhci_s3c_resume
,
640 .owner
= THIS_MODULE
,
645 static int __init
sdhci_s3c_init(void)
647 return platform_driver_register(&sdhci_s3c_driver
);
650 static void __exit
sdhci_s3c_exit(void)
652 platform_driver_unregister(&sdhci_s3c_driver
);
655 module_init(sdhci_s3c_init
);
656 module_exit(sdhci_s3c_exit
);
658 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
659 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
660 MODULE_LICENSE("GPL v2");
661 MODULE_ALIAS("platform:s3c-sdhci");