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include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / mtd / nand / cafe_nand.c
blob7c8df837d3b88ab1d73c08e8061eb42c94e38ab3
1 /*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * The data sheet for this device can be found at:
5 * http://wiki.laptop.org/go/Datasheets
6 *
7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
11 #define DEBUG
12
13 #include <linux/device.h>
14 #undef DEBUG
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/rslib.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <asm/io.h>
26
27 #define CAFE_NAND_CTRL1 0x00
28 #define CAFE_NAND_CTRL2 0x04
29 #define CAFE_NAND_CTRL3 0x08
30 #define CAFE_NAND_STATUS 0x0c
31 #define CAFE_NAND_IRQ 0x10
32 #define CAFE_NAND_IRQ_MASK 0x14
33 #define CAFE_NAND_DATA_LEN 0x18
34 #define CAFE_NAND_ADDR1 0x1c
35 #define CAFE_NAND_ADDR2 0x20
36 #define CAFE_NAND_TIMING1 0x24
37 #define CAFE_NAND_TIMING2 0x28
38 #define CAFE_NAND_TIMING3 0x2c
39 #define CAFE_NAND_NONMEM 0x30
40 #define CAFE_NAND_ECC_RESULT 0x3C
41 #define CAFE_NAND_DMA_CTRL 0x40
42 #define CAFE_NAND_DMA_ADDR0 0x44
43 #define CAFE_NAND_DMA_ADDR1 0x48
44 #define CAFE_NAND_ECC_SYN01 0x50
45 #define CAFE_NAND_ECC_SYN23 0x54
46 #define CAFE_NAND_ECC_SYN45 0x58
47 #define CAFE_NAND_ECC_SYN67 0x5c
48 #define CAFE_NAND_READ_DATA 0x1000
49 #define CAFE_NAND_WRITE_DATA 0x2000
50
51 #define CAFE_GLOBAL_CTRL 0x3004
52 #define CAFE_GLOBAL_IRQ 0x3008
53 #define CAFE_GLOBAL_IRQ_MASK 0x300c
54 #define CAFE_NAND_RESET 0x3034
55
56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57 #define CTRL1_CHIPSELECT (1<<19)
58
59 struct cafe_priv {
60 struct nand_chip nand;
61 struct mtd_partition *parts;
62 struct pci_dev *pdev;
63 void __iomem *mmio;
64 struct rs_control *rs;
65 uint32_t ctl1;
66 uint32_t ctl2;
67 int datalen;
68 int nr_data;
69 int data_pos;
70 int page_addr;
71 dma_addr_t dmaaddr;
72 unsigned char *dmabuf;
73 };
74
75 static int usedma = 1;
76 module_param(usedma, int, 0644);
77
78 static int skipbbt = 0;
79 module_param(skipbbt, int, 0644);
80
81 static int debug = 0;
82 module_param(debug, int, 0644);
83
84 static int regdebug = 0;
85 module_param(regdebug, int, 0644);
86
87 static int checkecc = 1;
88 module_param(checkecc, int, 0644);
89
90 static unsigned int numtimings;
91 static int timing[3];
92 module_param_array(timing, int, &numtimings, 0644);
93
94 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
95
96 /* Hrm. Why isn't this already conditional on something in the struct device? */
97 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
98
99 /* Make it easier to switch to PIO if we need to */
100 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
101 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
102
103 static int cafe_device_ready(struct mtd_info *mtd)
104 {
105 struct cafe_priv *cafe = mtd->priv;
106 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
108
109 cafe_writel(cafe, irqs, NAND_IRQ);
110
111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
114
115 return result;
116 }
117
118
119 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
120 {
121 struct cafe_priv *cafe = mtd->priv;
122
123 if (usedma)
124 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
125 else
126 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
127
128 cafe->datalen += len;
129
130 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
131 len, cafe->datalen);
132 }
133
134 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
135 {
136 struct cafe_priv *cafe = mtd->priv;
137
138 if (usedma)
139 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
140 else
141 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
142
143 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
144 len, cafe->datalen);
145 cafe->datalen += len;
146 }
147
148 static uint8_t cafe_read_byte(struct mtd_info *mtd)
149 {
150 struct cafe_priv *cafe = mtd->priv;
151 uint8_t d;
152
153 cafe_read_buf(mtd, &d, 1);
154 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
155
156 return d;
157 }
158
159 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
160 int column, int page_addr)
161 {
162 struct cafe_priv *cafe = mtd->priv;
163 int adrbytes = 0;
164 uint32_t ctl1;
165 uint32_t doneint = 0x80000000;
166
167 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
168 command, column, page_addr);
169
170 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
171 /* Second half of a command we already calculated */
172 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
173 ctl1 = cafe->ctl1;
174 cafe->ctl2 &= ~(1<<30);
175 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
176 cafe->ctl1, cafe->nr_data);
177 goto do_command;
178 }
179 /* Reset ECC engine */
180 cafe_writel(cafe, 0, NAND_CTRL2);
181
182 /* Emulate NAND_CMD_READOOB on large-page chips */
183 if (mtd->writesize > 512 &&
184 command == NAND_CMD_READOOB) {
185 column += mtd->writesize;
186 command = NAND_CMD_READ0;
187 }
188
189 /* FIXME: Do we need to send read command before sending data
190 for small-page chips, to position the buffer correctly? */
191
192 if (column != -1) {
193 cafe_writel(cafe, column, NAND_ADDR1);
194 adrbytes = 2;
195 if (page_addr != -1)
196 goto write_adr2;
197 } else if (page_addr != -1) {
198 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
199 page_addr >>= 16;
200 write_adr2:
201 cafe_writel(cafe, page_addr, NAND_ADDR2);
202 adrbytes += 2;
203 if (mtd->size > mtd->writesize << 16)
204 adrbytes++;
205 }
206
207 cafe->data_pos = cafe->datalen = 0;
208
209 /* Set command valid bit, mask in the chip select bit */
210 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
211
212 /* Set RD or WR bits as appropriate */
213 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
214 ctl1 |= (1<<26); /* rd */
215 /* Always 5 bytes, for now */
216 cafe->datalen = 4;
217 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
218 adrbytes = 1;
219 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
220 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
221 ctl1 |= 1<<26; /* rd */
222 /* For now, assume just read to end of page */
223 cafe->datalen = mtd->writesize + mtd->oobsize - column;
224 } else if (command == NAND_CMD_SEQIN)
225 ctl1 |= 1<<25; /* wr */
226
227 /* Set number of address bytes */
228 if (adrbytes)
229 ctl1 |= ((adrbytes-1)|8) << 27;
230
231 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
232 /* Ignore the first command of a pair; the hardware
233 deals with them both at once, later */
234 cafe->ctl1 = ctl1;
235 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
236 cafe->ctl1, cafe->datalen);
237 return;
238 }
239 /* RNDOUT and READ0 commands need a following byte */
240 if (command == NAND_CMD_RNDOUT)
241 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
242 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
244
245 do_command:
246 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
247 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
248
249 /* NB: The datasheet lies -- we really should be subtracting 1 here */
250 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
251 cafe_writel(cafe, 0x90000000, NAND_IRQ);
252 if (usedma && (ctl1 & (3<<25))) {
253 uint32_t dmactl = 0xc0000000 + cafe->datalen;
254 /* If WR or RD bits set, set up DMA */
255 if (ctl1 & (1<<26)) {
256 /* It's a read */
257 dmactl |= (1<<29);
258 /* ... so it's done when the DMA is done, not just
259 the command. */
260 doneint = 0x10000000;
261 }
262 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
263 }
264 cafe->datalen = 0;
265
266 if (unlikely(regdebug)) {
267 int i;
268 printk("About to write command %08x to register 0\n", ctl1);
269 for (i=4; i< 0x5c; i+=4)
270 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
271 }
272
273 cafe_writel(cafe, ctl1, NAND_CTRL1);
274 /* Apply this short delay always to ensure that we do wait tWB in
275 * any case on any machine. */
276 ndelay(100);
277
278 if (1) {
279 int c;
280 uint32_t irqs;
281
282 for (c = 500000; c != 0; c--) {
283 irqs = cafe_readl(cafe, NAND_IRQ);
284 if (irqs & doneint)
285 break;
286 udelay(1);
287 if (!(c % 100000))
288 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
289 cpu_relax();
290 }
291 cafe_writel(cafe, doneint, NAND_IRQ);
292 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
293 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
294 }
295
296 WARN_ON(cafe->ctl2 & (1<<30));
297
298 switch (command) {
299
300 case NAND_CMD_CACHEDPROG:
301 case NAND_CMD_PAGEPROG:
302 case NAND_CMD_ERASE1:
303 case NAND_CMD_ERASE2:
304 case NAND_CMD_SEQIN:
305 case NAND_CMD_RNDIN:
306 case NAND_CMD_STATUS:
307 case NAND_CMD_DEPLETE1:
308 case NAND_CMD_RNDOUT:
309 case NAND_CMD_STATUS_ERROR:
310 case NAND_CMD_STATUS_ERROR0:
311 case NAND_CMD_STATUS_ERROR1:
312 case NAND_CMD_STATUS_ERROR2:
313 case NAND_CMD_STATUS_ERROR3:
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
315 return;
316 }
317 nand_wait_ready(mtd);
318 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
319 }
320
321 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
322 {
323 struct cafe_priv *cafe = mtd->priv;
324
325 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
326
327 /* Mask the appropriate bit into the stored value of ctl1
328 which will be used by cafe_nand_cmdfunc() */
329 if (chipnr)
330 cafe->ctl1 |= CTRL1_CHIPSELECT;
331 else
332 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
333 }
334
335 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
336 {
337 struct mtd_info *mtd = id;
338 struct cafe_priv *cafe = mtd->priv;
339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
341 if (!irqs)
342 return IRQ_NONE;
343
344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
345 return IRQ_HANDLED;
346 }
347
348 static void cafe_nand_bug(struct mtd_info *mtd)
349 {
350 BUG();
351 }
352
353 static int cafe_nand_write_oob(struct mtd_info *mtd,
354 struct nand_chip *chip, int page)
355 {
356 int status = 0;
357
358 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
359 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
360 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
361 status = chip->waitfunc(mtd, chip);
362
363 return status & NAND_STATUS_FAIL ? -EIO : 0;
364 }
365
366 /* Don't use -- use nand_read_oob_std for now */
367 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
368 int page, int sndcmd)
369 {
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
371 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
372 return 1;
373 }
374 /**
375 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
376 * @mtd: mtd info structure
377 * @chip: nand chip info structure
378 * @buf: buffer to store read data
379 *
380 * The hw generator calculates the error syndrome automatically. Therefor
381 * we need a special oob layout and handling.
382 */
383 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
384 uint8_t *buf, int page)
385 {
386 struct cafe_priv *cafe = mtd->priv;
387
388 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
389 cafe_readl(cafe, NAND_ECC_RESULT),
390 cafe_readl(cafe, NAND_ECC_SYN01));
391
392 chip->read_buf(mtd, buf, mtd->writesize);
393 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
394
395 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
396 unsigned short syn[8], pat[4];
397 int pos[4];
398 u8 *oob = chip->oob_poi;
399 int i, n;
400
401 for (i=0; i<8; i+=2) {
402 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
403 syn[i] = cafe->rs->index_of[tmp & 0xfff];
404 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
405 }
406
407 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
408 pat);
409
410 for (i = 0; i < n; i++) {
411 int p = pos[i];
412
413 /* The 12-bit symbols are mapped to bytes here */
414
415 if (p > 1374) {
416 /* out of range */
417 n = -1374;
418 } else if (p == 0) {
419 /* high four bits do not correspond to data */
420 if (pat[i] > 0xff)
421 n = -2048;
422 else
423 buf[0] ^= pat[i];
424 } else if (p == 1365) {
425 buf[2047] ^= pat[i] >> 4;
426 oob[0] ^= pat[i] << 4;
427 } else if (p > 1365) {
428 if ((p & 1) == 1) {
429 oob[3*p/2 - 2048] ^= pat[i] >> 4;
430 oob[3*p/2 - 2047] ^= pat[i] << 4;
431 } else {
432 oob[3*p/2 - 2049] ^= pat[i] >> 8;
433 oob[3*p/2 - 2048] ^= pat[i];
434 }
435 } else if ((p & 1) == 1) {
436 buf[3*p/2] ^= pat[i] >> 4;
437 buf[3*p/2 + 1] ^= pat[i] << 4;
438 } else {
439 buf[3*p/2 - 1] ^= pat[i] >> 8;
440 buf[3*p/2] ^= pat[i];
441 }
442 }
443
444 if (n < 0) {
445 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
446 cafe_readl(cafe, NAND_ADDR2) * 2048);
447 for (i = 0; i < 0x5c; i += 4)
448 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
449 mtd->ecc_stats.failed++;
450 } else {
451 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
452 mtd->ecc_stats.corrected += n;
453 }
454 }
455
456 return 0;
457 }
458
459 static struct nand_ecclayout cafe_oobinfo_2048 = {
460 .eccbytes = 14,
461 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
462 .oobfree = {{14, 50}}
463 };
464
465 /* Ick. The BBT code really ought to be able to work this bit out
466 for itself from the above, at least for the 2KiB case */
467 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
468 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
469
470 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
471 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
472
473
474 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
475 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
476 | NAND_BBT_2BIT | NAND_BBT_VERSION,
477 .offs = 14,
478 .len = 4,
479 .veroffs = 18,
480 .maxblocks = 4,
481 .pattern = cafe_bbt_pattern_2048
482 };
483
484 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
485 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
486 | NAND_BBT_2BIT | NAND_BBT_VERSION,
487 .offs = 14,
488 .len = 4,
489 .veroffs = 18,
490 .maxblocks = 4,
491 .pattern = cafe_mirror_pattern_2048
492 };
493
494 static struct nand_ecclayout cafe_oobinfo_512 = {
495 .eccbytes = 14,
496 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
497 .oobfree = {{14, 2}}
498 };
499
500 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
501 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
502 | NAND_BBT_2BIT | NAND_BBT_VERSION,
503 .offs = 14,
504 .len = 1,
505 .veroffs = 15,
506 .maxblocks = 4,
507 .pattern = cafe_bbt_pattern_512
508 };
509
510 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
511 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
512 | NAND_BBT_2BIT | NAND_BBT_VERSION,
513 .offs = 14,
514 .len = 1,
515 .veroffs = 15,
516 .maxblocks = 4,
517 .pattern = cafe_mirror_pattern_512
518 };
519
520
521 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
522 struct nand_chip *chip, const uint8_t *buf)
523 {
524 struct cafe_priv *cafe = mtd->priv;
525
526 chip->write_buf(mtd, buf, mtd->writesize);
527 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
528
529 /* Set up ECC autogeneration */
530 cafe->ctl2 |= (1<<30);
531 }
532
533 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
534 const uint8_t *buf, int page, int cached, int raw)
535 {
536 int status;
537
538 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
539
540 if (unlikely(raw))
541 chip->ecc.write_page_raw(mtd, chip, buf);
542 else
543 chip->ecc.write_page(mtd, chip, buf);
544
545 /*
546 * Cached progamming disabled for now, Not sure if its worth the
547 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
548 */
549 cached = 0;
550
551 if (!cached || !(chip->options & NAND_CACHEPRG)) {
552
553 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
554 status = chip->waitfunc(mtd, chip);
555 /*
556 * See if operation failed and additional status checks are
557 * available
558 */
559 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
560 status = chip->errstat(mtd, chip, FL_WRITING, status,
561 page);
562
563 if (status & NAND_STATUS_FAIL)
564 return -EIO;
565 } else {
566 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
567 status = chip->waitfunc(mtd, chip);
568 }
569
570 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
571 /* Send command to read back the data */
572 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
573
574 if (chip->verify_buf(mtd, buf, mtd->writesize))
575 return -EIO;
576 #endif
577 return 0;
578 }
579
580 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
581 {
582 return 0;
583 }
584
585 /* F_2[X]/(X**6+X+1) */
586 static unsigned short __devinit gf64_mul(u8 a, u8 b)
587 {
588 u8 c;
589 unsigned int i;
590
591 c = 0;
592 for (i = 0; i < 6; i++) {
593 if (a & 1)
594 c ^= b;
595 a >>= 1;
596 b <<= 1;
597 if ((b & 0x40) != 0)
598 b ^= 0x43;
599 }
600
601 return c;
602 }
603
604 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
605 static u16 __devinit gf4096_mul(u16 a, u16 b)
606 {
607 u8 ah, al, bh, bl, ch, cl;
608
609 ah = a >> 6;
610 al = a & 0x3f;
611 bh = b >> 6;
612 bl = b & 0x3f;
613
614 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
615 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
616
617 return (ch << 6) ^ cl;
618 }
619
620 static int __devinit cafe_mul(int x)
621 {
622 if (x == 0)
623 return 1;
624 return gf4096_mul(x, 0xe01);
625 }
626
627 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
628 const struct pci_device_id *ent)
629 {
630 struct mtd_info *mtd;
631 struct cafe_priv *cafe;
632 uint32_t ctrl;
633 int err = 0;
634 struct mtd_partition *parts;
635 int nr_parts;
636
637 /* Very old versions shared the same PCI ident for all three
638 functions on the chip. Verify the class too... */
639 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
640 return -ENODEV;
641
642 err = pci_enable_device(pdev);
643 if (err)
644 return err;
645
646 pci_set_master(pdev);
647
648 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
649 if (!mtd) {
650 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
651 return -ENOMEM;
652 }
653 cafe = (void *)(&mtd[1]);
654
655 mtd->dev.parent = &pdev->dev;
656 mtd->priv = cafe;
657 mtd->owner = THIS_MODULE;
658
659 cafe->pdev = pdev;
660 cafe->mmio = pci_iomap(pdev, 0, 0);
661 if (!cafe->mmio) {
662 dev_warn(&pdev->dev, "failed to iomap\n");
663 err = -ENOMEM;
664 goto out_free_mtd;
665 }
666 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
667 &cafe->dmaaddr, GFP_KERNEL);
668 if (!cafe->dmabuf) {
669 err = -ENOMEM;
670 goto out_ior;
671 }
672 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
673
674 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
675 if (!cafe->rs) {
676 err = -ENOMEM;
677 goto out_ior;
678 }
679
680 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
681 cafe->nand.dev_ready = cafe_device_ready;
682 cafe->nand.read_byte = cafe_read_byte;
683 cafe->nand.read_buf = cafe_read_buf;
684 cafe->nand.write_buf = cafe_write_buf;
685 cafe->nand.select_chip = cafe_select_chip;
686
687 cafe->nand.chip_delay = 0;
688
689 /* Enable the following for a flash based bad block table */
690 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
691
692 if (skipbbt) {
693 cafe->nand.options |= NAND_SKIP_BBTSCAN;
694 cafe->nand.block_bad = cafe_nand_block_bad;
695 }
696
697 if (numtimings && numtimings != 3) {
698 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
699 }
700
701 if (numtimings == 3) {
702 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
703 timing[0], timing[1], timing[2]);
704 } else {
705 timing[0] = cafe_readl(cafe, NAND_TIMING1);
706 timing[1] = cafe_readl(cafe, NAND_TIMING2);
707 timing[2] = cafe_readl(cafe, NAND_TIMING3);
708
709 if (timing[0] | timing[1] | timing[2]) {
710 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
711 timing[0], timing[1], timing[2]);
712 } else {
713 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
714 timing[0] = timing[1] = timing[2] = 0xffffffff;
715 }
716 }
717
718 /* Start off by resetting the NAND controller completely */
719 cafe_writel(cafe, 1, NAND_RESET);
720 cafe_writel(cafe, 0, NAND_RESET);
721
722 cafe_writel(cafe, timing[0], NAND_TIMING1);
723 cafe_writel(cafe, timing[1], NAND_TIMING2);
724 cafe_writel(cafe, timing[2], NAND_TIMING3);
725
726 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
727 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
728 "CAFE NAND", mtd);
729 if (err) {
730 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
731 goto out_free_dma;
732 }
733
734 /* Disable master reset, enable NAND clock */
735 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
736 ctrl &= 0xffffeff0;
737 ctrl |= 0x00007000;
738 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
739 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
740 cafe_writel(cafe, 0, NAND_DMA_CTRL);
741
742 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
743 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
744
745 /* Set up DMA address */
746 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
747 if (sizeof(cafe->dmaaddr) > 4)
748 /* Shift in two parts to shut the compiler up */
749 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
750 else
751 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
752
753 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
754 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
755
756 /* Enable NAND IRQ in global IRQ mask register */
757 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
758 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
759 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
760
761 /* Scan to find existence of the device */
762 if (nand_scan_ident(mtd, 2, NULL)) {
763 err = -ENXIO;
764 goto out_irq;
765 }
766
767 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
768 if (mtd->writesize == 2048)
769 cafe->ctl2 |= 1<<29; /* 2KiB page size */
770
771 /* Set up ECC according to the type of chip we found */
772 if (mtd->writesize == 2048) {
773 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
774 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
775 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
776 } else if (mtd->writesize == 512) {
777 cafe->nand.ecc.layout = &cafe_oobinfo_512;
778 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
779 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
780 } else {
781 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
782 mtd->writesize);
783 goto out_irq;
784 }
785 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
786 cafe->nand.ecc.size = mtd->writesize;
787 cafe->nand.ecc.bytes = 14;
788 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
789 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
790 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
791 cafe->nand.write_page = cafe_nand_write_page;
792 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
793 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
794 cafe->nand.ecc.read_page = cafe_nand_read_page;
795 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
796
797 err = nand_scan_tail(mtd);
798 if (err)
799 goto out_irq;
800
801 pci_set_drvdata(pdev, mtd);
802
803 /* We register the whole device first, separate from the partitions */
804 mtd_device_register(mtd, NULL, 0);
805
806 #ifdef CONFIG_MTD_CMDLINE_PARTS
807 mtd->name = "cafe_nand";
808 #endif
809 nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
810 if (nr_parts > 0) {
811 cafe->parts = parts;
812 dev_info(&cafe->pdev->dev, "%d partitions found\n", nr_parts);
813 mtd_device_register(mtd, parts, nr_parts);
814 }
815 goto out;
816
817 out_irq:
818 /* Disable NAND IRQ in global IRQ mask register */
819 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
820 free_irq(pdev->irq, mtd);
821 out_free_dma:
822 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
823 out_ior:
824 pci_iounmap(pdev, cafe->mmio);
825 out_free_mtd:
826 kfree(mtd);
827 out:
828 return err;
829 }
830
831 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
832 {
833 struct mtd_info *mtd = pci_get_drvdata(pdev);
834 struct cafe_priv *cafe = mtd->priv;
835
836 /* Disable NAND IRQ in global IRQ mask register */
837 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
838 free_irq(pdev->irq, mtd);
839 nand_release(mtd);
840 free_rs(cafe->rs);
841 pci_iounmap(pdev, cafe->mmio);
842 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
843 kfree(mtd);
844 }
845
846 static const struct pci_device_id cafe_nand_tbl[] = {
847 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
848 PCI_ANY_ID, PCI_ANY_ID },
849 { }
850 };
851
852 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
853
854 static int cafe_nand_resume(struct pci_dev *pdev)
855 {
856 uint32_t ctrl;
857 struct mtd_info *mtd = pci_get_drvdata(pdev);
858 struct cafe_priv *cafe = mtd->priv;
859
860 /* Start off by resetting the NAND controller completely */
861 cafe_writel(cafe, 1, NAND_RESET);
862 cafe_writel(cafe, 0, NAND_RESET);
863 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
864
865 /* Restore timing configuration */
866 cafe_writel(cafe, timing[0], NAND_TIMING1);
867 cafe_writel(cafe, timing[1], NAND_TIMING2);
868 cafe_writel(cafe, timing[2], NAND_TIMING3);
869
870 /* Disable master reset, enable NAND clock */
871 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
872 ctrl &= 0xffffeff0;
873 ctrl |= 0x00007000;
874 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
875 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
876 cafe_writel(cafe, 0, NAND_DMA_CTRL);
877 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
878 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
879
880 /* Set up DMA address */
881 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
882 if (sizeof(cafe->dmaaddr) > 4)
883 /* Shift in two parts to shut the compiler up */
884 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
885 else
886 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
887
888 /* Enable NAND IRQ in global IRQ mask register */
889 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
890 return 0;
891 }
892
893 static struct pci_driver cafe_nand_pci_driver = {
894 .name = "CAFÉ NAND",
895 .id_table = cafe_nand_tbl,
896 .probe = cafe_nand_probe,
897 .remove = __devexit_p(cafe_nand_remove),
898 .resume = cafe_nand_resume,
899 };
900
901 static int __init cafe_nand_init(void)
902 {
903 return pci_register_driver(&cafe_nand_pci_driver);
904 }
905
906 static void __exit cafe_nand_exit(void)
907 {
908 pci_unregister_driver(&cafe_nand_pci_driver);
909 }
910 module_init(cafe_nand_init);
911 module_exit(cafe_nand_exit);
912
913 MODULE_LICENSE("GPL");
914 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
915 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
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