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include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / drivers / net / bnx2x / bnx2x_main.c
blobf74582a22c68a803985437989e6c0dd53652201a
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/ipv6.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52 #include <linux/stringify.h>
53 #include <linux/vmalloc.h>
54
55 #include "bnx2x.h"
56 #include "bnx2x_init.h"
57 #include "bnx2x_init_ops.h"
58 #include "bnx2x_cmn.h"
59 #include "bnx2x_dcb.h"
60 #include "bnx2x_sp.h"
61
62 #include <linux/firmware.h>
63 #include "bnx2x_fw_file_hdr.h"
64 /* FW files */
65 #define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
70 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
72 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
73
74 /* Time in jiffies before concluding the transmitter is hung */
75 #define TX_TIMEOUT (5*HZ)
76
77 static char version[] __devinitdata =
78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
81 MODULE_AUTHOR("Eliezer Tamir");
82 MODULE_DESCRIPTION("Broadcom NetXtreme II "
83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
86 MODULE_LICENSE("GPL");
87 MODULE_VERSION(DRV_MODULE_VERSION);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1);
89 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
90 MODULE_FIRMWARE(FW_FILE_NAME_E2);
91
92 static int multi_mode = 1;
93 module_param(multi_mode, int, 0);
94 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
97 int num_queues;
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
101
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
108 static int int_mode;
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
111 "(1 INT#x; 2 MSI)");
112
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
117 static int poll;
118 module_param(poll, int, 0);
119 MODULE_PARM_DESC(poll, " Use polling (for debug)");
120
121 static int mrrs = -1;
122 module_param(mrrs, int, 0);
123 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
125 static int debug;
126 module_param(debug, int, 0);
127 MODULE_PARM_DESC(debug, " Default debug msglevel");
128
129
130
131 struct workqueue_struct *bnx2x_wq;
132
133 enum bnx2x_board_type {
134 BCM57710 = 0,
135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
145 };
146
147 /* indexed by board_type, above */
148 static struct {
149 char *name;
150 } board_info[] __devinitdata = {
151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
163 };
164
165 #ifndef PCI_DEVICE_ID_NX2_57710
166 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167 #endif
168 #ifndef PCI_DEVICE_ID_NX2_57711
169 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170 #endif
171 #ifndef PCI_DEVICE_ID_NX2_57711E
172 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57712
175 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57712_MF
178 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57800
181 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57800_MF
184 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57810
187 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57810_MF
190 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57840
193 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57840_MF
196 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197 #endif
198 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
210 { 0 }
211 };
212
213 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215 /****************************************************************************
216 * General service functions
217 ****************************************************************************/
218
219 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221 {
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224 }
225
226 static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228 {
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233 }
234
235 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
237 {
238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
246 }
247
248 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250 {
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259 }
260
261 static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264 {
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270 }
271
272 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274 {
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277 }
278
279 /* used only at init
280 * locking is done by mcp
281 */
282 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
283 {
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288 }
289
290 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291 {
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300 }
301
302 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306 #define DMAE_DP_DST_NONE "dst_addr [none]"
307
308 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
310 {
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370 }
371
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
374 {
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386 }
387
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
389 {
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392 }
393
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395 {
396 return opcode & ~DMAE_CMD_SRC_RESET;
397 }
398
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401 {
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
406
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
413
414 #ifdef __BIG_ENDIAN
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
416 #else
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
418 #endif
419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422 }
423
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
427 {
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438 }
439
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
443 {
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
451
452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
457 spin_lock_bh(&bp->dmae_lock);
458
459 /* reset completion */
460 *wb_comp = 0;
461
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
464
465 /* wait for completion */
466 udelay(5);
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
470 if (!cnt) {
471 BNX2X_ERR("DMAE timeout!\n");
472 rc = DMAE_TIMEOUT;
473 goto unlock;
474 }
475 cnt--;
476 udelay(50);
477 }
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
486
487 unlock:
488 spin_unlock_bh(&bp->dmae_lock);
489 return rc;
490 }
491
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494 {
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
520 }
521
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
523 {
524 struct dmae_command dmae;
525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
539
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
546
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
548
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
551 }
552
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
555 {
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
557 int offset = 0;
558
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567 }
568
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571 {
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
577 }
578
579 #ifdef USE_WB_RD
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581 {
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587 }
588 #endif
589
590 static int bnx2x_mc_assert(struct bnx2x *bp)
591 {
592 char last_idx;
593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 return rc;
709 }
710
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
712 {
713 u32 addr, val;
714 u32 mark, offset;
715 __be32 data[9];
716 int word;
717 u32 trace_shmem_base;
718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
730
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
740
741 printk("%s", lvl);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
745 data[8] = 0x0;
746 pr_cont("%s", (char *)data);
747 }
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
751 data[8] = 0x0;
752 pr_cont("%s", (char *)data);
753 }
754 printk("%s" "end of fw dump\n", lvl);
755 }
756
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
758 {
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
760 }
761
762 void bnx2x_panic_dump(struct bnx2x *bp)
763 {
764 int i;
765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
770 u8 cos;
771 #endif
772
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
776 BNX2X_ERR("begin crash dump -----------------\n");
777
778 /* Indices */
779 /* Common */
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
801 "pf_id(0x%x) vnic_id(0x%x) "
802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
811
812
813 for_each_eth_queue(bp, i) {
814 struct bnx2x_fastpath *fp = &bp->fp[i];
815 int loop;
816 struct hc_status_block_data_e2 sb_data_e2;
817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
822 struct hc_index_data *hc_index_p =
823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
826 u8 data_size, cos;
827 u32 *sb_data_p;
828 struct bnx2x_fp_txdata txdata;
829
830 /* Rx */
831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
832 " rx_comp_prod(0x%x)"
833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
834 i, fp->rx_bd_prod, fp->rx_bd_cons,
835 fp->rx_comp_prod,
836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
838 " fp_hc_idx(0x%x)\n",
839 fp->rx_sge_prod, fp->last_max_sge,
840 le16_to_cpu(fp->fp_hc_idx));
841
842 /* Tx */
843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
854
855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
857
858 /* host sb data */
859
860 #ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863 #endif
864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
879 data_size /= sizeof(u32);
880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
899 } else {
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
909 }
910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
931 }
932
933 #ifdef BNX2X_STOP_ON_ERROR
934 /* Rings */
935 /* Rx */
936 for_each_rx_queue(bp, i) {
937 struct bnx2x_fastpath *fp = &bp->fp[i];
938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
941 for (j = start; j != end; j = RX_BD(j + 1)) {
942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
947 }
948
949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
951 for (j = start; j != end; j = RX_SGE(j + 1)) {
952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
957 }
958
959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
966 }
967 }
968
969 /* Tx */
970 for_each_tx_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
986
987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
991
992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
997 }
998 }
999 #endif
1000 bnx2x_fw_dump(bp);
1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
1003 }
1004
1005 /*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012 #define FLR_WAIT_INTERAVAL 50 /* usec */
1013 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015 struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020 };
1021
1022 struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026 };
1027
1028 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031 {
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061 }
1062
1063 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066 {
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093 }
1094
1095 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097 {
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105 }
1106
1107 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109 {
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116 }
1117
1118 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119 {
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128 }
1129
1130 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131 {
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193 }
1194
1195 #define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198 #define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201 #define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207 {
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235 }
1236
1237 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238 {
1239 int pos;
1240 u16 status;
1241
1242 pos = pci_pcie_cap(dev);
1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248 }
1249
1250 /* PF FLR specific routines
1251 */
1252 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253 {
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297 }
1298
1299 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300 {
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327 }
1328
1329 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330 {
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370 }
1371
1372 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1373 {
1374 int port = BP_PORT(bp);
1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1379
1380 if (msix) {
1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1395
1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
1399
1400 REG_WR(bp, addr, val);
1401
1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
1404 }
1405
1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1411
1412 REG_WR(bp, addr, val);
1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
1418
1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */
1421 if (IS_MF(bp)) {
1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1423 if (bp->port.pmf)
1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
1435 }
1436
1437 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438 {
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486 }
1487
1488 void bnx2x_int_enable(struct bnx2x *bp)
1489 {
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494 }
1495
1496 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1497 {
1498 int port = BP_PORT(bp);
1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
1526 /* flush all outstanding writes */
1527 mmiowb();
1528
1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532 }
1533
1534 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535 {
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550 }
1551
1552 void bnx2x_int_disable(struct bnx2x *bp)
1553 {
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558 }
1559
1560 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1561 {
1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1563 int i, offset;
1564
1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
1573 #ifdef BCM_CNIC
1574 offset++;
1575 #endif
1576 for_each_eth_queue(bp, i)
1577 synchronize_irq(bp->msix_table[offset++].vector);
1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1582 cancel_delayed_work(&bp->sp_task);
1583 cancel_delayed_work(&bp->period_task);
1584 flush_workqueue(bnx2x_wq);
1585 }
1586
1587 /* fast path */
1588
1589 /*
1590 * General service functions
1591 */
1592
1593 /* Return true if succeeded to acquire the lock */
1594 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595 {
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1608 return false;
1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625 }
1626
1627 /**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636 {
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641 }
1642
1643 /**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651 {
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653 }
1654
1655 #ifdef BCM_CNIC
1656 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1657 #endif
1658
1659 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1660 {
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1666
1667 DP(BNX2X_MSG_SP,
1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1669 fp->index, cid, command, bp->state,
1670 rr_cqe->ramrod_cqe.ramrod_type);
1671
1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
1677
1678 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1679 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1680 drv_cmd = BNX2X_Q_CMD_SETUP;
1681 break;
1682
1683 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1684 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1685 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1686 break;
1687
1688 case (RAMROD_CMD_ID_ETH_HALT):
1689 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1690 drv_cmd = BNX2X_Q_CMD_HALT;
1691 break;
1692
1693 case (RAMROD_CMD_ID_ETH_TERMINATE):
1694 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1695 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1696 break;
1697
1698 case (RAMROD_CMD_ID_ETH_EMPTY):
1699 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1700 drv_cmd = BNX2X_Q_CMD_EMPTY;
1701 break;
1702
1703 default:
1704 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1705 command, fp->index);
1706 return;
1707 }
1708
1709 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1710 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1711 /* q_obj->complete_cmd() failure means that this was
1712 * an unexpected completion.
1713 *
1714 * In this case we don't want to increase the bp->spq_left
1715 * because apparently we haven't sent this command the first
1716 * place.
1717 */
1718 #ifdef BNX2X_STOP_ON_ERROR
1719 bnx2x_panic();
1720 #else
1721 return;
1722 #endif
1723
1724 smp_mb__before_atomic_inc();
1725 atomic_inc(&bp->cq_spq_left);
1726 /* push the change in bp->spq_left and towards the memory */
1727 smp_mb__after_atomic_inc();
1728
1729 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1730
1731 return;
1732 }
1733
1734 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1735 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1736 {
1737 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1738
1739 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 start);
1741 }
1742
1743 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1744 {
1745 struct bnx2x *bp = netdev_priv(dev_instance);
1746 u16 status = bnx2x_ack_int(bp);
1747 u16 mask;
1748 int i;
1749 u8 cos;
1750
1751 /* Return here if interrupt is shared and it's not for us */
1752 if (unlikely(status == 0)) {
1753 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1754 return IRQ_NONE;
1755 }
1756 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1757
1758 #ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic))
1760 return IRQ_HANDLED;
1761 #endif
1762
1763 for_each_eth_queue(bp, i) {
1764 struct bnx2x_fastpath *fp = &bp->fp[i];
1765
1766 mask = 0x2 << (fp->index + CNIC_PRESENT);
1767 if (status & mask) {
1768 /* Handle Rx or Tx according to SB id */
1769 prefetch(fp->rx_cons_sb);
1770 for_each_cos_in_tx_queue(fp, cos)
1771 prefetch(fp->txdata[cos].tx_cons_sb);
1772 prefetch(&fp->sb_running_index[SM_RX_ID]);
1773 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1774 status &= ~mask;
1775 }
1776 }
1777
1778 #ifdef BCM_CNIC
1779 mask = 0x2;
1780 if (status & (mask | 0x1)) {
1781 struct cnic_ops *c_ops = NULL;
1782
1783 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1784 rcu_read_lock();
1785 c_ops = rcu_dereference(bp->cnic_ops);
1786 if (c_ops)
1787 c_ops->cnic_handler(bp->cnic_data, NULL);
1788 rcu_read_unlock();
1789 }
1790
1791 status &= ~mask;
1792 }
1793 #endif
1794
1795 if (unlikely(status & 0x1)) {
1796 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1797
1798 status &= ~0x1;
1799 if (!status)
1800 return IRQ_HANDLED;
1801 }
1802
1803 if (unlikely(status))
1804 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1805 status);
1806
1807 return IRQ_HANDLED;
1808 }
1809
1810 /* Link */
1811
1812 /*
1813 * General service functions
1814 */
1815
1816 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1817 {
1818 u32 lock_status;
1819 u32 resource_bit = (1 << resource);
1820 int func = BP_FUNC(bp);
1821 u32 hw_lock_control_reg;
1822 int cnt;
1823
1824 /* Validating that the resource is within range */
1825 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1826 DP(NETIF_MSG_HW,
1827 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1828 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1829 return -EINVAL;
1830 }
1831
1832 if (func <= 5) {
1833 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1834 } else {
1835 hw_lock_control_reg =
1836 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1837 }
1838
1839 /* Validating that the resource is not already taken */
1840 lock_status = REG_RD(bp, hw_lock_control_reg);
1841 if (lock_status & resource_bit) {
1842 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1843 lock_status, resource_bit);
1844 return -EEXIST;
1845 }
1846
1847 /* Try for 5 second every 5ms */
1848 for (cnt = 0; cnt < 1000; cnt++) {
1849 /* Try to acquire the lock */
1850 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1851 lock_status = REG_RD(bp, hw_lock_control_reg);
1852 if (lock_status & resource_bit)
1853 return 0;
1854
1855 msleep(5);
1856 }
1857 DP(NETIF_MSG_HW, "Timeout\n");
1858 return -EAGAIN;
1859 }
1860
1861 int bnx2x_release_leader_lock(struct bnx2x *bp)
1862 {
1863 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1864 }
1865
1866 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1867 {
1868 u32 lock_status;
1869 u32 resource_bit = (1 << resource);
1870 int func = BP_FUNC(bp);
1871 u32 hw_lock_control_reg;
1872
1873 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1874
1875 /* Validating that the resource is within range */
1876 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1877 DP(NETIF_MSG_HW,
1878 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1879 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1880 return -EINVAL;
1881 }
1882
1883 if (func <= 5) {
1884 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1885 } else {
1886 hw_lock_control_reg =
1887 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1888 }
1889
1890 /* Validating that the resource is currently taken */
1891 lock_status = REG_RD(bp, hw_lock_control_reg);
1892 if (!(lock_status & resource_bit)) {
1893 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1894 lock_status, resource_bit);
1895 return -EFAULT;
1896 }
1897
1898 REG_WR(bp, hw_lock_control_reg, resource_bit);
1899 return 0;
1900 }
1901
1902
1903 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1904 {
1905 /* The GPIO should be swapped if swap register is set and active */
1906 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1907 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1908 int gpio_shift = gpio_num +
1909 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1910 u32 gpio_mask = (1 << gpio_shift);
1911 u32 gpio_reg;
1912 int value;
1913
1914 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1915 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 return -EINVAL;
1917 }
1918
1919 /* read GPIO value */
1920 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1921
1922 /* get the requested pin value */
1923 if ((gpio_reg & gpio_mask) == gpio_mask)
1924 value = 1;
1925 else
1926 value = 0;
1927
1928 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1929
1930 return value;
1931 }
1932
1933 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1934 {
1935 /* The GPIO should be swapped if swap register is set and active */
1936 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1937 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1938 int gpio_shift = gpio_num +
1939 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1940 u32 gpio_mask = (1 << gpio_shift);
1941 u32 gpio_reg;
1942
1943 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1944 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 return -EINVAL;
1946 }
1947
1948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1949 /* read GPIO and mask except the float bits */
1950 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1951
1952 switch (mode) {
1953 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1954 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1955 gpio_num, gpio_shift);
1956 /* clear FLOAT and set CLR */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1959 break;
1960
1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set SET */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1967 break;
1968
1969 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1971 gpio_num, gpio_shift);
1972 /* set FLOAT */
1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 break;
1975
1976 default:
1977 break;
1978 }
1979
1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1981 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1982
1983 return 0;
1984 }
1985
1986 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1987 {
1988 u32 gpio_reg = 0;
1989 int rc = 0;
1990
1991 /* Any port swapping should be handled by caller. */
1992
1993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 /* read GPIO and mask except the float bits */
1995 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1997 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1998 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1999
2000 switch (mode) {
2001 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2003 /* set CLR */
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2005 break;
2006
2007 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2009 /* set SET */
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2011 break;
2012
2013 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2015 /* set FLOAT */
2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 break;
2018
2019 default:
2020 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2021 rc = -EINVAL;
2022 break;
2023 }
2024
2025 if (rc == 0)
2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2027
2028 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2029
2030 return rc;
2031 }
2032
2033 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2034 {
2035 /* The GPIO should be swapped if swap register is set and active */
2036 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2037 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2038 int gpio_shift = gpio_num +
2039 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2040 u32 gpio_mask = (1 << gpio_shift);
2041 u32 gpio_reg;
2042
2043 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2044 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 return -EINVAL;
2046 }
2047
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2049 /* read GPIO int */
2050 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2051
2052 switch (mode) {
2053 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2054 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2055 "output low\n", gpio_num, gpio_shift);
2056 /* clear SET and set CLR */
2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2059 break;
2060
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2062 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2063 "output high\n", gpio_num, gpio_shift);
2064 /* clear CLR and set SET */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return 0;
2077 }
2078
2079 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2080 {
2081 u32 spio_mask = (1 << spio_num);
2082 u32 spio_reg;
2083
2084 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2085 (spio_num > MISC_REGISTERS_SPIO_7)) {
2086 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 return -EINVAL;
2088 }
2089
2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2091 /* read SPIO and mask except the float bits */
2092 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2093
2094 switch (mode) {
2095 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2096 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2097 /* clear FLOAT and set CLR */
2098 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2100 break;
2101
2102 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2103 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2104 /* clear FLOAT and set SET */
2105 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2107 break;
2108
2109 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2110 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2111 /* set FLOAT */
2112 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2113 break;
2114
2115 default:
2116 break;
2117 }
2118
2119 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2121
2122 return 0;
2123 }
2124
2125 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2126 {
2127 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2128 switch (bp->link_vars.ieee_fc &
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2130 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2131 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2132 ADVERTISED_Pause);
2133 break;
2134
2135 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2136 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2137 ADVERTISED_Pause);
2138 break;
2139
2140 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2141 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2142 break;
2143
2144 default:
2145 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2146 ADVERTISED_Pause);
2147 break;
2148 }
2149 }
2150
2151 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2152 {
2153 if (!BP_NOMCP(bp)) {
2154 u8 rc;
2155 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2156 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2157 /*
2158 * Initialize link parameters structure variables
2159 * It is recommended to turn off RX FC for jumbo frames
2160 * for better performance
2161 */
2162 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2164 else
2165 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2166
2167 bnx2x_acquire_phy_lock(bp);
2168
2169 if (load_mode == LOAD_DIAG) {
2170 struct link_params *lp = &bp->link_params;
2171 lp->loopback_mode = LOOPBACK_XGXS;
2172 /* do PHY loopback at 10G speed, if possible */
2173 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2174 if (lp->speed_cap_mask[cfx_idx] &
2175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2176 lp->req_line_speed[cfx_idx] =
2177 SPEED_10000;
2178 else
2179 lp->req_line_speed[cfx_idx] =
2180 SPEED_1000;
2181 }
2182 }
2183
2184 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2185
2186 bnx2x_release_phy_lock(bp);
2187
2188 bnx2x_calc_fc_adv(bp);
2189
2190 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2191 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2192 bnx2x_link_report(bp);
2193 } else
2194 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2195 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2196 return rc;
2197 }
2198 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2199 return -EINVAL;
2200 }
2201
2202 void bnx2x_link_set(struct bnx2x *bp)
2203 {
2204 if (!BP_NOMCP(bp)) {
2205 bnx2x_acquire_phy_lock(bp);
2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2207 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2208 bnx2x_release_phy_lock(bp);
2209
2210 bnx2x_calc_fc_adv(bp);
2211 } else
2212 BNX2X_ERR("Bootcode is missing - can not set link\n");
2213 }
2214
2215 static void bnx2x__link_reset(struct bnx2x *bp)
2216 {
2217 if (!BP_NOMCP(bp)) {
2218 bnx2x_acquire_phy_lock(bp);
2219 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2220 bnx2x_release_phy_lock(bp);
2221 } else
2222 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2223 }
2224
2225 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2226 {
2227 u8 rc = 0;
2228
2229 if (!BP_NOMCP(bp)) {
2230 bnx2x_acquire_phy_lock(bp);
2231 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2232 is_serdes);
2233 bnx2x_release_phy_lock(bp);
2234 } else
2235 BNX2X_ERR("Bootcode is missing - can not test link\n");
2236
2237 return rc;
2238 }
2239
2240 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2241 {
2242 u32 r_param = bp->link_vars.line_speed / 8;
2243 u32 fair_periodic_timeout_usec;
2244 u32 t_fair;
2245
2246 memset(&(bp->cmng.rs_vars), 0,
2247 sizeof(struct rate_shaping_vars_per_port));
2248 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2249
2250 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2251 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2252
2253 /* this is the threshold below which no timer arming will occur
2254 1.25 coefficient is for the threshold to be a little bigger
2255 than the real time, to compensate for timer in-accuracy */
2256 bp->cmng.rs_vars.rs_threshold =
2257 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2258
2259 /* resolution of fairness timer */
2260 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2261 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2262 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2263
2264 /* this is the threshold below which we won't arm the timer anymore */
2265 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2266
2267 /* we multiply by 1e3/8 to get bytes/msec.
2268 We don't want the credits to pass a credit
2269 of the t_fair*FAIR_MEM (algorithm resolution) */
2270 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2271 /* since each tick is 4 usec */
2272 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2273 }
2274
2275 /* Calculates the sum of vn_min_rates.
2276 It's needed for further normalizing of the min_rates.
2277 Returns:
2278 sum of vn_min_rates.
2279 or
2280 0 - if all the min_rates are 0.
2281 In the later case fainess algorithm should be deactivated.
2282 If not all min_rates are zero then those that are zeroes will be set to 1.
2283 */
2284 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2285 {
2286 int all_zero = 1;
2287 int vn;
2288
2289 bp->vn_weight_sum = 0;
2290 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2291 u32 vn_cfg = bp->mf_config[vn];
2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2294
2295 /* Skip hidden vns */
2296 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2297 continue;
2298
2299 /* If min rate is zero - set it to 1 */
2300 if (!vn_min_rate)
2301 vn_min_rate = DEF_MIN_RATE;
2302 else
2303 all_zero = 0;
2304
2305 bp->vn_weight_sum += vn_min_rate;
2306 }
2307
2308 /* if ETS or all min rates are zeros - disable fairness */
2309 if (BNX2X_IS_ETS_ENABLED(bp)) {
2310 bp->cmng.flags.cmng_enables &=
2311 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2312 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2313 } else if (all_zero) {
2314 bp->cmng.flags.cmng_enables &=
2315 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2316 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2317 " fairness will be disabled\n");
2318 } else
2319 bp->cmng.flags.cmng_enables |=
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2321 }
2322
2323 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2324 {
2325 struct rate_shaping_vars_per_vn m_rs_vn;
2326 struct fairness_vars_per_vn m_fair_vn;
2327 u32 vn_cfg = bp->mf_config[vn];
2328 int func = 2*vn + BP_PORT(bp);
2329 u16 vn_min_rate, vn_max_rate;
2330 int i;
2331
2332 /* If function is hidden - set min and max to zeroes */
2333 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2334 vn_min_rate = 0;
2335 vn_max_rate = 0;
2336
2337 } else {
2338 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2339
2340 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2341 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2342 /* If fairness is enabled (not all min rates are zeroes) and
2343 if current min rate is zero - set it to 1.
2344 This is a requirement of the algorithm. */
2345 if (bp->vn_weight_sum && (vn_min_rate == 0))
2346 vn_min_rate = DEF_MIN_RATE;
2347
2348 if (IS_MF_SI(bp))
2349 /* maxCfg in percents of linkspeed */
2350 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2351 else
2352 /* maxCfg is absolute in 100Mb units */
2353 vn_max_rate = maxCfg * 100;
2354 }
2355
2356 DP(NETIF_MSG_IFUP,
2357 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2358 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2359
2360 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2361 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2362
2363 /* global vn counter - maximal Mbps for this vn */
2364 m_rs_vn.vn_counter.rate = vn_max_rate;
2365
2366 /* quota - number of bytes transmitted in this period */
2367 m_rs_vn.vn_counter.quota =
2368 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2369
2370 if (bp->vn_weight_sum) {
2371 /* credit for each period of the fairness algorithm:
2372 number of bytes in T_FAIR (the vn share the port rate).
2373 vn_weight_sum should not be larger than 10000, thus
2374 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2375 than zero */
2376 m_fair_vn.vn_credit_delta =
2377 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2378 (8 * bp->vn_weight_sum))),
2379 (bp->cmng.fair_vars.fair_threshold +
2380 MIN_ABOVE_THRESH));
2381 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2382 m_fair_vn.vn_credit_delta);
2383 }
2384
2385 /* Store it to internal memory */
2386 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2387 REG_WR(bp, BAR_XSTRORM_INTMEM +
2388 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2389 ((u32 *)(&m_rs_vn))[i]);
2390
2391 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2392 REG_WR(bp, BAR_XSTRORM_INTMEM +
2393 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2394 ((u32 *)(&m_fair_vn))[i]);
2395 }
2396
2397 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2398 {
2399 if (CHIP_REV_IS_SLOW(bp))
2400 return CMNG_FNS_NONE;
2401 if (IS_MF(bp))
2402 return CMNG_FNS_MINMAX;
2403
2404 return CMNG_FNS_NONE;
2405 }
2406
2407 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2408 {
2409 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2410
2411 if (BP_NOMCP(bp))
2412 return; /* what should be the default bvalue in this case */
2413
2414 /* For 2 port configuration the absolute function number formula
2415 * is:
2416 * abs_func = 2 * vn + BP_PORT + BP_PATH
2417 *
2418 * and there are 4 functions per port
2419 *
2420 * For 4 port configuration it is
2421 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2422 *
2423 * and there are 2 functions per port
2424 */
2425 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2426 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2427
2428 if (func >= E1H_FUNC_MAX)
2429 break;
2430
2431 bp->mf_config[vn] =
2432 MF_CFG_RD(bp, func_mf_config[func].config);
2433 }
2434 }
2435
2436 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2437 {
2438
2439 if (cmng_type == CMNG_FNS_MINMAX) {
2440 int vn;
2441
2442 /* clear cmng_enables */
2443 bp->cmng.flags.cmng_enables = 0;
2444
2445 /* read mf conf from shmem */
2446 if (read_cfg)
2447 bnx2x_read_mf_cfg(bp);
2448
2449 /* Init rate shaping and fairness contexts */
2450 bnx2x_init_port_minmax(bp);
2451
2452 /* vn_weight_sum and enable fairness if not 0 */
2453 bnx2x_calc_vn_weight_sum(bp);
2454
2455 /* calculate and set min-max rate for each vn */
2456 if (bp->port.pmf)
2457 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2458 bnx2x_init_vn_minmax(bp, vn);
2459
2460 /* always enable rate shaping and fairness */
2461 bp->cmng.flags.cmng_enables |=
2462 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2463 if (!bp->vn_weight_sum)
2464 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2465 " fairness will be disabled\n");
2466 return;
2467 }
2468
2469 /* rate shaping and fairness are disabled */
2470 DP(NETIF_MSG_IFUP,
2471 "rate shaping and fairness are disabled\n");
2472 }
2473
2474 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2475 {
2476 int port = BP_PORT(bp);
2477 int func;
2478 int vn;
2479
2480 /* Set the attention towards other drivers on the same port */
2481 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2482 if (vn == BP_E1HVN(bp))
2483 continue;
2484
2485 func = ((vn << 1) | port);
2486 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2487 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2488 }
2489 }
2490
2491 /* This function is called upon link interrupt */
2492 static void bnx2x_link_attn(struct bnx2x *bp)
2493 {
2494 /* Make sure that we are synced with the current statistics */
2495 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2496
2497 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2498
2499 if (bp->link_vars.link_up) {
2500
2501 /* dropless flow control */
2502 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2503 int port = BP_PORT(bp);
2504 u32 pause_enabled = 0;
2505
2506 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2507 pause_enabled = 1;
2508
2509 REG_WR(bp, BAR_USTRORM_INTMEM +
2510 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2511 pause_enabled);
2512 }
2513
2514 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2515 struct host_port_stats *pstats;
2516
2517 pstats = bnx2x_sp(bp, port_stats);
2518 /* reset old mac stats */
2519 memset(&(pstats->mac_stx[0]), 0,
2520 sizeof(struct mac_stx));
2521 }
2522 if (bp->state == BNX2X_STATE_OPEN)
2523 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2524 }
2525
2526 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2527 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2528
2529 if (cmng_fns != CMNG_FNS_NONE) {
2530 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2531 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2532 } else
2533 /* rate shaping and fairness are disabled */
2534 DP(NETIF_MSG_IFUP,
2535 "single function mode without fairness\n");
2536 }
2537
2538 __bnx2x_link_report(bp);
2539
2540 if (IS_MF(bp))
2541 bnx2x_link_sync_notify(bp);
2542 }
2543
2544 void bnx2x__link_status_update(struct bnx2x *bp)
2545 {
2546 if (bp->state != BNX2X_STATE_OPEN)
2547 return;
2548
2549 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2550
2551 if (bp->link_vars.link_up)
2552 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2553 else
2554 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2555
2556 /* indicate link status */
2557 bnx2x_link_report(bp);
2558 }
2559
2560 static void bnx2x_pmf_update(struct bnx2x *bp)
2561 {
2562 int port = BP_PORT(bp);
2563 u32 val;
2564
2565 bp->port.pmf = 1;
2566 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2567
2568 /*
2569 * We need the mb() to ensure the ordering between the writing to
2570 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2571 */
2572 smp_mb();
2573
2574 /* queue a periodic task */
2575 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2576
2577 bnx2x_dcbx_pmf_update(bp);
2578
2579 /* enable nig attention */
2580 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2581 if (bp->common.int_block == INT_BLOCK_HC) {
2582 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2583 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2584 } else if (!CHIP_IS_E1x(bp)) {
2585 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2586 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2587 }
2588
2589 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2590 }
2591
2592 /* end of Link */
2593
2594 /* slow path */
2595
2596 /*
2597 * General service functions
2598 */
2599
2600 /* send the MCP a request, block until there is a reply */
2601 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2602 {
2603 int mb_idx = BP_FW_MB_IDX(bp);
2604 u32 seq;
2605 u32 rc = 0;
2606 u32 cnt = 1;
2607 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2608
2609 mutex_lock(&bp->fw_mb_mutex);
2610 seq = ++bp->fw_seq;
2611 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2612 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2613
2614 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2615 (command | seq), param);
2616
2617 do {
2618 /* let the FW do it's magic ... */
2619 msleep(delay);
2620
2621 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2622
2623 /* Give the FW up to 5 second (500*10ms) */
2624 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2625
2626 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2627 cnt*delay, rc, seq);
2628
2629 /* is this a reply to our command? */
2630 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2631 rc &= FW_MSG_CODE_MASK;
2632 else {
2633 /* FW BUG! */
2634 BNX2X_ERR("FW failed to respond!\n");
2635 bnx2x_fw_dump(bp);
2636 rc = 0;
2637 }
2638 mutex_unlock(&bp->fw_mb_mutex);
2639
2640 return rc;
2641 }
2642
2643 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2644 {
2645 #ifdef BCM_CNIC
2646 /* Statistics are not supported for CNIC Clients at the moment */
2647 if (IS_FCOE_FP(fp))
2648 return false;
2649 #endif
2650 return true;
2651 }
2652
2653 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2654 {
2655 if (CHIP_IS_E1x(bp)) {
2656 struct tstorm_eth_function_common_config tcfg = {0};
2657
2658 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2659 }
2660
2661 /* Enable the function in the FW */
2662 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2663 storm_memset_func_en(bp, p->func_id, 1);
2664
2665 /* spq */
2666 if (p->func_flgs & FUNC_FLG_SPQ) {
2667 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2668 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2669 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2670 }
2671 }
2672
2673 /**
2674 * bnx2x_get_tx_only_flags - Return common flags
2675 *
2676 * @bp device handle
2677 * @fp queue handle
2678 * @zero_stats TRUE if statistics zeroing is needed
2679 *
2680 * Return the flags that are common for the Tx-only and not normal connections.
2681 */
2682 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2683 struct bnx2x_fastpath *fp,
2684 bool zero_stats)
2685 {
2686 unsigned long flags = 0;
2687
2688 /* PF driver will always initialize the Queue to an ACTIVE state */
2689 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2690
2691 /* tx only connections collect statistics (on the same index as the
2692 * parent connection). The statistics are zeroed when the parent
2693 * connection is initialized.
2694 */
2695 if (stat_counter_valid(bp, fp)) {
2696 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2697 if (zero_stats)
2698 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2699 }
2700
2701 return flags;
2702 }
2703
2704 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2705 struct bnx2x_fastpath *fp,
2706 bool leading)
2707 {
2708 unsigned long flags = 0;
2709
2710 /* calculate other queue flags */
2711 if (IS_MF_SD(bp))
2712 __set_bit(BNX2X_Q_FLG_OV, &flags);
2713
2714 if (IS_FCOE_FP(fp))
2715 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2716
2717 if (!fp->disable_tpa) {
2718 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2719 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2720 }
2721
2722 if (leading) {
2723 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2724 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2725 }
2726
2727 /* Always set HW VLAN stripping */
2728 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2729
2730
2731 return flags | bnx2x_get_common_flags(bp, fp, true);
2732 }
2733
2734 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2735 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2736 u8 cos)
2737 {
2738 gen_init->stat_id = bnx2x_stats_id(fp);
2739 gen_init->spcl_id = fp->cl_id;
2740
2741 /* Always use mini-jumbo MTU for FCoE L2 ring */
2742 if (IS_FCOE_FP(fp))
2743 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2744 else
2745 gen_init->mtu = bp->dev->mtu;
2746
2747 gen_init->cos = cos;
2748 }
2749
2750 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2751 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2752 struct bnx2x_rxq_setup_params *rxq_init)
2753 {
2754 u8 max_sge = 0;
2755 u16 sge_sz = 0;
2756 u16 tpa_agg_size = 0;
2757
2758 if (!fp->disable_tpa) {
2759 pause->sge_th_hi = 250;
2760 pause->sge_th_lo = 150;
2761 tpa_agg_size = min_t(u32,
2762 (min_t(u32, 8, MAX_SKB_FRAGS) *
2763 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2764 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2765 SGE_PAGE_SHIFT;
2766 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2767 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2768 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2769 0xffff);
2770 }
2771
2772 /* pause - not for e1 */
2773 if (!CHIP_IS_E1(bp)) {
2774 pause->bd_th_hi = 350;
2775 pause->bd_th_lo = 250;
2776 pause->rcq_th_hi = 350;
2777 pause->rcq_th_lo = 250;
2778
2779 pause->pri_map = 1;
2780 }
2781
2782 /* rxq setup */
2783 rxq_init->dscr_map = fp->rx_desc_mapping;
2784 rxq_init->sge_map = fp->rx_sge_mapping;
2785 rxq_init->rcq_map = fp->rx_comp_mapping;
2786 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2787
2788 /* This should be a maximum number of data bytes that may be
2789 * placed on the BD (not including paddings).
2790 */
2791 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2792 IP_HEADER_ALIGNMENT_PADDING;
2793
2794 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2795 rxq_init->tpa_agg_sz = tpa_agg_size;
2796 rxq_init->sge_buf_sz = sge_sz;
2797 rxq_init->max_sges_pkt = max_sge;
2798 rxq_init->rss_engine_id = BP_FUNC(bp);
2799
2800 /* Maximum number or simultaneous TPA aggregation for this Queue.
2801 *
2802 * For PF Clients it should be the maximum avaliable number.
2803 * VF driver(s) may want to define it to a smaller value.
2804 */
2805 rxq_init->max_tpa_queues =
2806 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2807 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2808
2809 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2810 rxq_init->fw_sb_id = fp->fw_sb_id;
2811
2812 if (IS_FCOE_FP(fp))
2813 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2814 else
2815 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2816 }
2817
2818 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2819 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2820 u8 cos)
2821 {
2822 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2823 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2824 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2825 txq_init->fw_sb_id = fp->fw_sb_id;
2826
2827 /*
2828 * set the tss leading client id for TX classfication ==
2829 * leading RSS client id
2830 */
2831 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2832
2833 if (IS_FCOE_FP(fp)) {
2834 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2835 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2836 }
2837 }
2838
2839 static void bnx2x_pf_init(struct bnx2x *bp)
2840 {
2841 struct bnx2x_func_init_params func_init = {0};
2842 struct event_ring_data eq_data = { {0} };
2843 u16 flags;
2844
2845 if (!CHIP_IS_E1x(bp)) {
2846 /* reset IGU PF statistics: MSIX + ATTN */
2847 /* PF */
2848 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2849 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2850 (CHIP_MODE_IS_4_PORT(bp) ?
2851 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2852 /* ATTN */
2853 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2854 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2855 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2856 (CHIP_MODE_IS_4_PORT(bp) ?
2857 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2858 }
2859
2860 /* function setup flags */
2861 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2862
2863 /* This flag is relevant for E1x only.
2864 * E2 doesn't have a TPA configuration in a function level.
2865 */
2866 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2867
2868 func_init.func_flgs = flags;
2869 func_init.pf_id = BP_FUNC(bp);
2870 func_init.func_id = BP_FUNC(bp);
2871 func_init.spq_map = bp->spq_mapping;
2872 func_init.spq_prod = bp->spq_prod_idx;
2873
2874 bnx2x_func_init(bp, &func_init);
2875
2876 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2877
2878 /*
2879 * Congestion management values depend on the link rate
2880 * There is no active link so initial link rate is set to 10 Gbps.
2881 * When the link comes up The congestion management values are
2882 * re-calculated according to the actual link rate.
2883 */
2884 bp->link_vars.line_speed = SPEED_10000;
2885 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2886
2887 /* Only the PMF sets the HW */
2888 if (bp->port.pmf)
2889 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2890
2891 /* init Event Queue */
2892 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2893 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2894 eq_data.producer = bp->eq_prod;
2895 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2896 eq_data.sb_id = DEF_SB_ID;
2897 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2898 }
2899
2900
2901 static void bnx2x_e1h_disable(struct bnx2x *bp)
2902 {
2903 int port = BP_PORT(bp);
2904
2905 bnx2x_tx_disable(bp);
2906
2907 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2908 }
2909
2910 static void bnx2x_e1h_enable(struct bnx2x *bp)
2911 {
2912 int port = BP_PORT(bp);
2913
2914 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2915
2916 /* Tx queue should be only reenabled */
2917 netif_tx_wake_all_queues(bp->dev);
2918
2919 /*
2920 * Should not call netif_carrier_on since it will be called if the link
2921 * is up when checking for link state
2922 */
2923 }
2924
2925 /* called due to MCP event (on pmf):
2926 * reread new bandwidth configuration
2927 * configure FW
2928 * notify others function about the change
2929 */
2930 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2931 {
2932 if (bp->link_vars.link_up) {
2933 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2934 bnx2x_link_sync_notify(bp);
2935 }
2936 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2937 }
2938
2939 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2940 {
2941 bnx2x_config_mf_bw(bp);
2942 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2943 }
2944
2945 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2946 {
2947 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2948
2949 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2950
2951 /*
2952 * This is the only place besides the function initialization
2953 * where the bp->flags can change so it is done without any
2954 * locks
2955 */
2956 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2957 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2958 bp->flags |= MF_FUNC_DIS;
2959
2960 bnx2x_e1h_disable(bp);
2961 } else {
2962 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2963 bp->flags &= ~MF_FUNC_DIS;
2964
2965 bnx2x_e1h_enable(bp);
2966 }
2967 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2968 }
2969 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2970 bnx2x_config_mf_bw(bp);
2971 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2972 }
2973
2974 /* Report results to MCP */
2975 if (dcc_event)
2976 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2977 else
2978 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2979 }
2980
2981 /* must be called under the spq lock */
2982 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2983 {
2984 struct eth_spe *next_spe = bp->spq_prod_bd;
2985
2986 if (bp->spq_prod_bd == bp->spq_last_bd) {
2987 bp->spq_prod_bd = bp->spq;
2988 bp->spq_prod_idx = 0;
2989 DP(NETIF_MSG_TIMER, "end of spq\n");
2990 } else {
2991 bp->spq_prod_bd++;
2992 bp->spq_prod_idx++;
2993 }
2994 return next_spe;
2995 }
2996
2997 /* must be called under the spq lock */
2998 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2999 {
3000 int func = BP_FUNC(bp);
3001
3002 /*
3003 * Make sure that BD data is updated before writing the producer:
3004 * BD data is written to the memory, the producer is read from the
3005 * memory, thus we need a full memory barrier to ensure the ordering.
3006 */
3007 mb();
3008
3009 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3010 bp->spq_prod_idx);
3011 mmiowb();
3012 }
3013
3014 /**
3015 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3016 *
3017 * @cmd: command to check
3018 * @cmd_type: command type
3019 */
3020 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3021 {
3022 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3023 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3024 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3025 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3026 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3027 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3028 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3029 return true;
3030 else
3031 return false;
3032
3033 }
3034
3035
3036 /**
3037 * bnx2x_sp_post - place a single command on an SP ring
3038 *
3039 * @bp: driver handle
3040 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3041 * @cid: SW CID the command is related to
3042 * @data_hi: command private data address (high 32 bits)
3043 * @data_lo: command private data address (low 32 bits)
3044 * @cmd_type: command type (e.g. NONE, ETH)
3045 *
3046 * SP data is handled as if it's always an address pair, thus data fields are
3047 * not swapped to little endian in upper functions. Instead this function swaps
3048 * data as if it's two u32 fields.
3049 */
3050 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3051 u32 data_hi, u32 data_lo, int cmd_type)
3052 {
3053 struct eth_spe *spe;
3054 u16 type;
3055 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3056
3057 #ifdef BNX2X_STOP_ON_ERROR
3058 if (unlikely(bp->panic))
3059 return -EIO;
3060 #endif
3061
3062 spin_lock_bh(&bp->spq_lock);
3063
3064 if (common) {
3065 if (!atomic_read(&bp->eq_spq_left)) {
3066 BNX2X_ERR("BUG! EQ ring full!\n");
3067 spin_unlock_bh(&bp->spq_lock);
3068 bnx2x_panic();
3069 return -EBUSY;
3070 }
3071 } else if (!atomic_read(&bp->cq_spq_left)) {
3072 BNX2X_ERR("BUG! SPQ ring full!\n");
3073 spin_unlock_bh(&bp->spq_lock);
3074 bnx2x_panic();
3075 return -EBUSY;
3076 }
3077
3078 spe = bnx2x_sp_get_next(bp);
3079
3080 /* CID needs port number to be encoded int it */
3081 spe->hdr.conn_and_cmd_data =
3082 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3083 HW_CID(bp, cid));
3084
3085 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3086
3087 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3088 SPE_HDR_FUNCTION_ID);
3089
3090 spe->hdr.type = cpu_to_le16(type);
3091
3092 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3093 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3094
3095 /*
3096 * It's ok if the actual decrement is issued towards the memory
3097 * somewhere between the spin_lock and spin_unlock. Thus no
3098 * more explict memory barrier is needed.
3099 */
3100 if (common)
3101 atomic_dec(&bp->eq_spq_left);
3102 else
3103 atomic_dec(&bp->cq_spq_left);
3104
3105
3106 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3107 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3108 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3109 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3110 (u32)(U64_LO(bp->spq_mapping) +
3111 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3112 HW_CID(bp, cid), data_hi, data_lo, type,
3113 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3114
3115 bnx2x_sp_prod_update(bp);
3116 spin_unlock_bh(&bp->spq_lock);
3117 return 0;
3118 }
3119
3120 /* acquire split MCP access lock register */
3121 static int bnx2x_acquire_alr(struct bnx2x *bp)
3122 {
3123 u32 j, val;
3124 int rc = 0;
3125
3126 might_sleep();
3127 for (j = 0; j < 1000; j++) {
3128 val = (1UL << 31);
3129 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3130 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3131 if (val & (1L << 31))
3132 break;
3133
3134 msleep(5);
3135 }
3136 if (!(val & (1L << 31))) {
3137 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3138 rc = -EBUSY;
3139 }
3140
3141 return rc;
3142 }
3143
3144 /* release split MCP access lock register */
3145 static void bnx2x_release_alr(struct bnx2x *bp)
3146 {
3147 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3148 }
3149
3150 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3151 #define BNX2X_DEF_SB_IDX 0x0002
3152
3153 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3154 {
3155 struct host_sp_status_block *def_sb = bp->def_status_blk;
3156 u16 rc = 0;
3157
3158 barrier(); /* status block is written to by the chip */
3159 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3160 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3161 rc |= BNX2X_DEF_SB_ATT_IDX;
3162 }
3163
3164 if (bp->def_idx != def_sb->sp_sb.running_index) {
3165 bp->def_idx = def_sb->sp_sb.running_index;
3166 rc |= BNX2X_DEF_SB_IDX;
3167 }
3168
3169 /* Do not reorder: indecies reading should complete before handling */
3170 barrier();
3171 return rc;
3172 }
3173
3174 /*
3175 * slow path service functions
3176 */
3177
3178 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3179 {
3180 int port = BP_PORT(bp);
3181 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3182 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3183 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3184 NIG_REG_MASK_INTERRUPT_PORT0;
3185 u32 aeu_mask;
3186 u32 nig_mask = 0;
3187 u32 reg_addr;
3188
3189 if (bp->attn_state & asserted)
3190 BNX2X_ERR("IGU ERROR\n");
3191
3192 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3193 aeu_mask = REG_RD(bp, aeu_addr);
3194
3195 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3196 aeu_mask, asserted);
3197 aeu_mask &= ~(asserted & 0x3ff);
3198 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3199
3200 REG_WR(bp, aeu_addr, aeu_mask);
3201 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3202
3203 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3204 bp->attn_state |= asserted;
3205 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3206
3207 if (asserted & ATTN_HARD_WIRED_MASK) {
3208 if (asserted & ATTN_NIG_FOR_FUNC) {
3209
3210 bnx2x_acquire_phy_lock(bp);
3211
3212 /* save nig interrupt mask */
3213 nig_mask = REG_RD(bp, nig_int_mask_addr);
3214
3215 /* If nig_mask is not set, no need to call the update
3216 * function.
3217 */
3218 if (nig_mask) {
3219 REG_WR(bp, nig_int_mask_addr, 0);
3220
3221 bnx2x_link_attn(bp);
3222 }
3223
3224 /* handle unicore attn? */
3225 }
3226 if (asserted & ATTN_SW_TIMER_4_FUNC)
3227 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3228
3229 if (asserted & GPIO_2_FUNC)
3230 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3231
3232 if (asserted & GPIO_3_FUNC)
3233 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3234
3235 if (asserted & GPIO_4_FUNC)
3236 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3237
3238 if (port == 0) {
3239 if (asserted & ATTN_GENERAL_ATTN_1) {
3240 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3241 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3242 }
3243 if (asserted & ATTN_GENERAL_ATTN_2) {
3244 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3245 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3246 }
3247 if (asserted & ATTN_GENERAL_ATTN_3) {
3248 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3249 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3250 }
3251 } else {
3252 if (asserted & ATTN_GENERAL_ATTN_4) {
3253 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3254 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3255 }
3256 if (asserted & ATTN_GENERAL_ATTN_5) {
3257 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3258 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3259 }
3260 if (asserted & ATTN_GENERAL_ATTN_6) {
3261 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3262 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3263 }
3264 }
3265
3266 } /* if hardwired */
3267
3268 if (bp->common.int_block == INT_BLOCK_HC)
3269 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3270 COMMAND_REG_ATTN_BITS_SET);
3271 else
3272 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3273
3274 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3275 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3276 REG_WR(bp, reg_addr, asserted);
3277
3278 /* now set back the mask */
3279 if (asserted & ATTN_NIG_FOR_FUNC) {
3280 REG_WR(bp, nig_int_mask_addr, nig_mask);
3281 bnx2x_release_phy_lock(bp);
3282 }
3283 }
3284
3285 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3286 {
3287 int port = BP_PORT(bp);
3288 u32 ext_phy_config;
3289 /* mark the failure */
3290 ext_phy_config =
3291 SHMEM_RD(bp,
3292 dev_info.port_hw_config[port].external_phy_config);
3293
3294 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3295 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3296 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3297 ext_phy_config);
3298
3299 /* log the failure */
3300 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3301 " the driver to shutdown the card to prevent permanent"
3302 " damage. Please contact OEM Support for assistance\n");
3303 }
3304
3305 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3306 {
3307 int port = BP_PORT(bp);
3308 int reg_offset;
3309 u32 val;
3310
3311 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3312 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3313
3314 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3315
3316 val = REG_RD(bp, reg_offset);
3317 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3318 REG_WR(bp, reg_offset, val);
3319
3320 BNX2X_ERR("SPIO5 hw attention\n");
3321
3322 /* Fan failure attention */
3323 bnx2x_hw_reset_phy(&bp->link_params);
3324 bnx2x_fan_failure(bp);
3325 }
3326
3327 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3328 bnx2x_acquire_phy_lock(bp);
3329 bnx2x_handle_module_detect_int(&bp->link_params);
3330 bnx2x_release_phy_lock(bp);
3331 }
3332
3333 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3334
3335 val = REG_RD(bp, reg_offset);
3336 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3337 REG_WR(bp, reg_offset, val);
3338
3339 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3340 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3341 bnx2x_panic();
3342 }
3343 }
3344
3345 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3346 {
3347 u32 val;
3348
3349 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3350
3351 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3352 BNX2X_ERR("DB hw attention 0x%x\n", val);
3353 /* DORQ discard attention */
3354 if (val & 0x2)
3355 BNX2X_ERR("FATAL error from DORQ\n");
3356 }
3357
3358 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3359
3360 int port = BP_PORT(bp);
3361 int reg_offset;
3362
3363 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3364 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3365
3366 val = REG_RD(bp, reg_offset);
3367 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3368 REG_WR(bp, reg_offset, val);
3369
3370 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3371 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3372 bnx2x_panic();
3373 }
3374 }
3375
3376 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3377 {
3378 u32 val;
3379
3380 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3381
3382 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3383 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3384 /* CFC error attention */
3385 if (val & 0x2)
3386 BNX2X_ERR("FATAL error from CFC\n");
3387 }
3388
3389 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3390 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3391 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3392 /* RQ_USDMDP_FIFO_OVERFLOW */
3393 if (val & 0x18000)
3394 BNX2X_ERR("FATAL error from PXP\n");
3395
3396 if (!CHIP_IS_E1x(bp)) {
3397 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3398 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3399 }
3400 }
3401
3402 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3403
3404 int port = BP_PORT(bp);
3405 int reg_offset;
3406
3407 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3408 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3409
3410 val = REG_RD(bp, reg_offset);
3411 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3412 REG_WR(bp, reg_offset, val);
3413
3414 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3415 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3416 bnx2x_panic();
3417 }
3418 }
3419
3420 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3421 {
3422 u32 val;
3423
3424 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3425
3426 if (attn & BNX2X_PMF_LINK_ASSERT) {
3427 int func = BP_FUNC(bp);
3428
3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3430 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3431 func_mf_config[BP_ABS_FUNC(bp)].config);
3432 val = SHMEM_RD(bp,
3433 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3434 if (val & DRV_STATUS_DCC_EVENT_MASK)
3435 bnx2x_dcc_event(bp,
3436 (val & DRV_STATUS_DCC_EVENT_MASK));
3437
3438 if (val & DRV_STATUS_SET_MF_BW)
3439 bnx2x_set_mf_bw(bp);
3440
3441 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3442 bnx2x_pmf_update(bp);
3443
3444 if (bp->port.pmf &&
3445 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3446 bp->dcbx_enabled > 0)
3447 /* start dcbx state machine */
3448 bnx2x_dcbx_set_params(bp,
3449 BNX2X_DCBX_STATE_NEG_RECEIVED);
3450 if (bp->link_vars.periodic_flags &
3451 PERIODIC_FLAGS_LINK_EVENT) {
3452 /* sync with link */
3453 bnx2x_acquire_phy_lock(bp);
3454 bp->link_vars.periodic_flags &=
3455 ~PERIODIC_FLAGS_LINK_EVENT;
3456 bnx2x_release_phy_lock(bp);
3457 if (IS_MF(bp))
3458 bnx2x_link_sync_notify(bp);
3459 bnx2x_link_report(bp);
3460 }
3461 /* Always call it here: bnx2x_link_report() will
3462 * prevent the link indication duplication.
3463 */
3464 bnx2x__link_status_update(bp);
3465 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3466
3467 BNX2X_ERR("MC assert!\n");
3468 bnx2x_mc_assert(bp);
3469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3470 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3472 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3473 bnx2x_panic();
3474
3475 } else if (attn & BNX2X_MCP_ASSERT) {
3476
3477 BNX2X_ERR("MCP assert!\n");
3478 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3479 bnx2x_fw_dump(bp);
3480
3481 } else
3482 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3483 }
3484
3485 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3486 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3487 if (attn & BNX2X_GRC_TIMEOUT) {
3488 val = CHIP_IS_E1(bp) ? 0 :
3489 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3490 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3491 }
3492 if (attn & BNX2X_GRC_RSV) {
3493 val = CHIP_IS_E1(bp) ? 0 :
3494 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3495 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3496 }
3497 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3498 }
3499 }
3500
3501 /*
3502 * Bits map:
3503 * 0-7 - Engine0 load counter.
3504 * 8-15 - Engine1 load counter.
3505 * 16 - Engine0 RESET_IN_PROGRESS bit.
3506 * 17 - Engine1 RESET_IN_PROGRESS bit.
3507 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3508 * on the engine
3509 * 19 - Engine1 ONE_IS_LOADED.
3510 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3511 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3512 * just the one belonging to its engine).
3513 *
3514 */
3515 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3516
3517 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3518 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3519 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3520 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3521 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3522 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3523 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3524
3525 /*
3526 * Set the GLOBAL_RESET bit.
3527 *
3528 * Should be run under rtnl lock
3529 */
3530 void bnx2x_set_reset_global(struct bnx2x *bp)
3531 {
3532 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3533
3534 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3535 barrier();
3536 mmiowb();
3537 }
3538
3539 /*
3540 * Clear the GLOBAL_RESET bit.
3541 *
3542 * Should be run under rtnl lock
3543 */
3544 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3545 {
3546 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3547
3548 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3549 barrier();
3550 mmiowb();
3551 }
3552
3553 /*
3554 * Checks the GLOBAL_RESET bit.
3555 *
3556 * should be run under rtnl lock
3557 */
3558 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3559 {
3560 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3561
3562 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3563 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3564 }
3565
3566 /*
3567 * Clear RESET_IN_PROGRESS bit for the current engine.
3568 *
3569 * Should be run under rtnl lock
3570 */
3571 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3572 {
3573 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3574 u32 bit = BP_PATH(bp) ?
3575 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3576
3577 /* Clear the bit */
3578 val &= ~bit;
3579 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3580 barrier();
3581 mmiowb();
3582 }
3583
3584 /*
3585 * Set RESET_IN_PROGRESS for the current engine.
3586 *
3587 * should be run under rtnl lock
3588 */
3589 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3590 {
3591 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3592 u32 bit = BP_PATH(bp) ?
3593 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3594
3595 /* Set the bit */
3596 val |= bit;
3597 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3598 barrier();
3599 mmiowb();
3600 }
3601
3602 /*
3603 * Checks the RESET_IN_PROGRESS bit for the given engine.
3604 * should be run under rtnl lock
3605 */
3606 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3607 {
3608 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3609 u32 bit = engine ?
3610 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3611
3612 /* return false if bit is set */
3613 return (val & bit) ? false : true;
3614 }
3615
3616 /*
3617 * Increment the load counter for the current engine.
3618 *
3619 * should be run under rtnl lock
3620 */
3621 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3622 {
3623 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3624 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3625 BNX2X_PATH0_LOAD_CNT_MASK;
3626 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3627 BNX2X_PATH0_LOAD_CNT_SHIFT;
3628
3629 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3630
3631 /* get the current counter value */
3632 val1 = (val & mask) >> shift;
3633
3634 /* increment... */
3635 val1++;
3636
3637 /* clear the old value */
3638 val &= ~mask;
3639
3640 /* set the new one */
3641 val |= ((val1 << shift) & mask);
3642
3643 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3644 barrier();
3645 mmiowb();
3646 }
3647
3648 /**
3649 * bnx2x_dec_load_cnt - decrement the load counter
3650 *
3651 * @bp: driver handle
3652 *
3653 * Should be run under rtnl lock.
3654 * Decrements the load counter for the current engine. Returns
3655 * the new counter value.
3656 */
3657 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3658 {
3659 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3660 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3661 BNX2X_PATH0_LOAD_CNT_MASK;
3662 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3663 BNX2X_PATH0_LOAD_CNT_SHIFT;
3664
3665 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3666
3667 /* get the current counter value */
3668 val1 = (val & mask) >> shift;
3669
3670 /* decrement... */
3671 val1--;
3672
3673 /* clear the old value */
3674 val &= ~mask;
3675
3676 /* set the new one */
3677 val |= ((val1 << shift) & mask);
3678
3679 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3680 barrier();
3681 mmiowb();
3682
3683 return val1;
3684 }
3685
3686 /*
3687 * Read the load counter for the current engine.
3688 *
3689 * should be run under rtnl lock
3690 */
3691 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3692 {
3693 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3694 BNX2X_PATH0_LOAD_CNT_MASK);
3695 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3696 BNX2X_PATH0_LOAD_CNT_SHIFT);
3697 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3698
3699 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3700
3701 val = (val & mask) >> shift;
3702
3703 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3704
3705 return val;
3706 }
3707
3708 /*
3709 * Reset the load counter for the current engine.
3710 *
3711 * should be run under rtnl lock
3712 */
3713 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3714 {
3715 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3716 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3717 BNX2X_PATH0_LOAD_CNT_MASK);
3718
3719 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3720 }
3721
3722 static inline void _print_next_block(int idx, const char *blk)
3723 {
3724 if (idx)
3725 pr_cont(", ");
3726 pr_cont("%s", blk);
3727 }
3728
3729 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3730 bool print)
3731 {
3732 int i = 0;
3733 u32 cur_bit = 0;
3734 for (i = 0; sig; i++) {
3735 cur_bit = ((u32)0x1 << i);
3736 if (sig & cur_bit) {
3737 switch (cur_bit) {
3738 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3739 if (print)
3740 _print_next_block(par_num++, "BRB");
3741 break;
3742 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3743 if (print)
3744 _print_next_block(par_num++, "PARSER");
3745 break;
3746 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3747 if (print)
3748 _print_next_block(par_num++, "TSDM");
3749 break;
3750 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3751 if (print)
3752 _print_next_block(par_num++,
3753 "SEARCHER");
3754 break;
3755 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3756 if (print)
3757 _print_next_block(par_num++, "TCM");
3758 break;
3759 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3760 if (print)
3761 _print_next_block(par_num++, "TSEMI");
3762 break;
3763 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3764 if (print)
3765 _print_next_block(par_num++, "XPB");
3766 break;
3767 }
3768
3769 /* Clear the bit */
3770 sig &= ~cur_bit;
3771 }
3772 }
3773
3774 return par_num;
3775 }
3776
3777 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3778 bool *global, bool print)
3779 {
3780 int i = 0;
3781 u32 cur_bit = 0;
3782 for (i = 0; sig; i++) {
3783 cur_bit = ((u32)0x1 << i);
3784 if (sig & cur_bit) {
3785 switch (cur_bit) {
3786 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3787 if (print)
3788 _print_next_block(par_num++, "PBF");
3789 break;
3790 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3791 if (print)
3792 _print_next_block(par_num++, "QM");
3793 break;
3794 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3795 if (print)
3796 _print_next_block(par_num++, "TM");
3797 break;
3798 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3799 if (print)
3800 _print_next_block(par_num++, "XSDM");
3801 break;
3802 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3803 if (print)
3804 _print_next_block(par_num++, "XCM");
3805 break;
3806 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3807 if (print)
3808 _print_next_block(par_num++, "XSEMI");
3809 break;
3810 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3811 if (print)
3812 _print_next_block(par_num++,
3813 "DOORBELLQ");
3814 break;
3815 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3816 if (print)
3817 _print_next_block(par_num++, "NIG");
3818 break;
3819 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3820 if (print)
3821 _print_next_block(par_num++,
3822 "VAUX PCI CORE");
3823 *global = true;
3824 break;
3825 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3826 if (print)
3827 _print_next_block(par_num++, "DEBUG");
3828 break;
3829 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3830 if (print)
3831 _print_next_block(par_num++, "USDM");
3832 break;
3833 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3834 if (print)
3835 _print_next_block(par_num++, "UCM");
3836 break;
3837 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3838 if (print)
3839 _print_next_block(par_num++, "USEMI");
3840 break;
3841 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3842 if (print)
3843 _print_next_block(par_num++, "UPB");
3844 break;
3845 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3846 if (print)
3847 _print_next_block(par_num++, "CSDM");
3848 break;
3849 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3850 if (print)
3851 _print_next_block(par_num++, "CCM");
3852 break;
3853 }
3854
3855 /* Clear the bit */
3856 sig &= ~cur_bit;
3857 }
3858 }
3859
3860 return par_num;
3861 }
3862
3863 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3864 bool print)
3865 {
3866 int i = 0;
3867 u32 cur_bit = 0;
3868 for (i = 0; sig; i++) {
3869 cur_bit = ((u32)0x1 << i);
3870 if (sig & cur_bit) {
3871 switch (cur_bit) {
3872 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3873 if (print)
3874 _print_next_block(par_num++, "CSEMI");
3875 break;
3876 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3877 if (print)
3878 _print_next_block(par_num++, "PXP");
3879 break;
3880 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3881 if (print)
3882 _print_next_block(par_num++,
3883 "PXPPCICLOCKCLIENT");
3884 break;
3885 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3886 if (print)
3887 _print_next_block(par_num++, "CFC");
3888 break;
3889 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3890 if (print)
3891 _print_next_block(par_num++, "CDU");
3892 break;
3893 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3894 if (print)
3895 _print_next_block(par_num++, "DMAE");
3896 break;
3897 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3898 if (print)
3899 _print_next_block(par_num++, "IGU");
3900 break;
3901 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3902 if (print)
3903 _print_next_block(par_num++, "MISC");
3904 break;
3905 }
3906
3907 /* Clear the bit */
3908 sig &= ~cur_bit;
3909 }
3910 }
3911
3912 return par_num;
3913 }
3914
3915 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3916 bool *global, bool print)
3917 {
3918 int i = 0;
3919 u32 cur_bit = 0;
3920 for (i = 0; sig; i++) {
3921 cur_bit = ((u32)0x1 << i);
3922 if (sig & cur_bit) {
3923 switch (cur_bit) {
3924 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3925 if (print)
3926 _print_next_block(par_num++, "MCP ROM");
3927 *global = true;
3928 break;
3929 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3930 if (print)
3931 _print_next_block(par_num++,
3932 "MCP UMP RX");
3933 *global = true;
3934 break;
3935 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3936 if (print)
3937 _print_next_block(par_num++,
3938 "MCP UMP TX");
3939 *global = true;
3940 break;
3941 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3942 if (print)
3943 _print_next_block(par_num++,
3944 "MCP SCPAD");
3945 *global = true;
3946 break;
3947 }
3948
3949 /* Clear the bit */
3950 sig &= ~cur_bit;
3951 }
3952 }
3953
3954 return par_num;
3955 }
3956
3957 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3958 bool print)
3959 {
3960 int i = 0;
3961 u32 cur_bit = 0;
3962 for (i = 0; sig; i++) {
3963 cur_bit = ((u32)0x1 << i);
3964 if (sig & cur_bit) {
3965 switch (cur_bit) {
3966 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3967 if (print)
3968 _print_next_block(par_num++, "PGLUE_B");
3969 break;
3970 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3971 if (print)
3972 _print_next_block(par_num++, "ATC");
3973 break;
3974 }
3975
3976 /* Clear the bit */
3977 sig &= ~cur_bit;
3978 }
3979 }
3980
3981 return par_num;
3982 }
3983
3984 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3985 u32 *sig)
3986 {
3987 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3988 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3989 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3990 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3991 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3992 int par_num = 0;
3993 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3994 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3995 "[4]:0x%08x\n",
3996 sig[0] & HW_PRTY_ASSERT_SET_0,
3997 sig[1] & HW_PRTY_ASSERT_SET_1,
3998 sig[2] & HW_PRTY_ASSERT_SET_2,
3999 sig[3] & HW_PRTY_ASSERT_SET_3,
4000 sig[4] & HW_PRTY_ASSERT_SET_4);
4001 if (print)
4002 netdev_err(bp->dev,
4003 "Parity errors detected in blocks: ");
4004 par_num = bnx2x_check_blocks_with_parity0(
4005 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4006 par_num = bnx2x_check_blocks_with_parity1(
4007 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4008 par_num = bnx2x_check_blocks_with_parity2(
4009 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4010 par_num = bnx2x_check_blocks_with_parity3(
4011 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4012 par_num = bnx2x_check_blocks_with_parity4(
4013 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4014
4015 if (print)
4016 pr_cont("\n");
4017
4018 return true;
4019 } else
4020 return false;
4021 }
4022
4023 /**
4024 * bnx2x_chk_parity_attn - checks for parity attentions.
4025 *
4026 * @bp: driver handle
4027 * @global: true if there was a global attention
4028 * @print: show parity attention in syslog
4029 */
4030 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4031 {
4032 struct attn_route attn = { {0} };
4033 int port = BP_PORT(bp);
4034
4035 attn.sig[0] = REG_RD(bp,
4036 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4037 port*4);
4038 attn.sig[1] = REG_RD(bp,
4039 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4040 port*4);
4041 attn.sig[2] = REG_RD(bp,
4042 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4043 port*4);
4044 attn.sig[3] = REG_RD(bp,
4045 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4046 port*4);
4047
4048 if (!CHIP_IS_E1x(bp))
4049 attn.sig[4] = REG_RD(bp,
4050 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4051 port*4);
4052
4053 return bnx2x_parity_attn(bp, global, print, attn.sig);
4054 }
4055
4056
4057 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4058 {
4059 u32 val;
4060 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4061
4062 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4063 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4064 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4065 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4066 "ADDRESS_ERROR\n");
4067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4069 "INCORRECT_RCV_BEHAVIOR\n");
4070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4072 "WAS_ERROR_ATTN\n");
4073 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4074 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4075 "VF_LENGTH_VIOLATION_ATTN\n");
4076 if (val &
4077 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4079 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4080 if (val &
4081 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4083 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4086 "TCPL_ERROR_ATTN\n");
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "TCPL_IN_TWO_RCBS_ATTN\n");
4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4092 "CSSNOOP_FIFO_OVERFLOW\n");
4093 }
4094 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4095 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4096 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4097 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4098 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4099 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4100 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4101 "_ATC_TCPL_TO_NOT_PEND\n");
4102 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4103 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4104 "ATC_GPA_MULTIPLE_HITS\n");
4105 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4107 "ATC_RCPL_TO_EMPTY_CNT\n");
4108 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4109 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4110 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4111 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4112 "ATC_IREQ_LESS_THAN_STU\n");
4113 }
4114
4115 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4116 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4117 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4118 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4119 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4120 }
4121
4122 }
4123
4124 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4125 {
4126 struct attn_route attn, *group_mask;
4127 int port = BP_PORT(bp);
4128 int index;
4129 u32 reg_addr;
4130 u32 val;
4131 u32 aeu_mask;
4132 bool global = false;
4133
4134 /* need to take HW lock because MCP or other port might also
4135 try to handle this event */
4136 bnx2x_acquire_alr(bp);
4137
4138 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4139 #ifndef BNX2X_STOP_ON_ERROR
4140 bp->recovery_state = BNX2X_RECOVERY_INIT;
4141 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4142 /* Disable HW interrupts */
4143 bnx2x_int_disable(bp);
4144 /* In case of parity errors don't handle attentions so that
4145 * other function would "see" parity errors.
4146 */
4147 #else
4148 bnx2x_panic();
4149 #endif
4150 bnx2x_release_alr(bp);
4151 return;
4152 }
4153
4154 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4155 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4156 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4157 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4158 if (!CHIP_IS_E1x(bp))
4159 attn.sig[4] =
4160 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4161 else
4162 attn.sig[4] = 0;
4163
4164 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4165 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4166
4167 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4168 if (deasserted & (1 << index)) {
4169 group_mask = &bp->attn_group[index];
4170
4171 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4172 "%08x %08x %08x\n",
4173 index,
4174 group_mask->sig[0], group_mask->sig[1],
4175 group_mask->sig[2], group_mask->sig[3],
4176 group_mask->sig[4]);
4177
4178 bnx2x_attn_int_deasserted4(bp,
4179 attn.sig[4] & group_mask->sig[4]);
4180 bnx2x_attn_int_deasserted3(bp,
4181 attn.sig[3] & group_mask->sig[3]);
4182 bnx2x_attn_int_deasserted1(bp,
4183 attn.sig[1] & group_mask->sig[1]);
4184 bnx2x_attn_int_deasserted2(bp,
4185 attn.sig[2] & group_mask->sig[2]);
4186 bnx2x_attn_int_deasserted0(bp,
4187 attn.sig[0] & group_mask->sig[0]);
4188 }
4189 }
4190
4191 bnx2x_release_alr(bp);
4192
4193 if (bp->common.int_block == INT_BLOCK_HC)
4194 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4195 COMMAND_REG_ATTN_BITS_CLR);
4196 else
4197 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4198
4199 val = ~deasserted;
4200 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4201 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4202 REG_WR(bp, reg_addr, val);
4203
4204 if (~bp->attn_state & deasserted)
4205 BNX2X_ERR("IGU ERROR\n");
4206
4207 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4208 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4209
4210 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4211 aeu_mask = REG_RD(bp, reg_addr);
4212
4213 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4214 aeu_mask, deasserted);
4215 aeu_mask |= (deasserted & 0x3ff);
4216 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4217
4218 REG_WR(bp, reg_addr, aeu_mask);
4219 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4220
4221 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4222 bp->attn_state &= ~deasserted;
4223 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4224 }
4225
4226 static void bnx2x_attn_int(struct bnx2x *bp)
4227 {
4228 /* read local copy of bits */
4229 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4230 attn_bits);
4231 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4232 attn_bits_ack);
4233 u32 attn_state = bp->attn_state;
4234
4235 /* look for changed bits */
4236 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4237 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4238
4239 DP(NETIF_MSG_HW,
4240 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4241 attn_bits, attn_ack, asserted, deasserted);
4242
4243 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4244 BNX2X_ERR("BAD attention state\n");
4245
4246 /* handle bits that were raised */
4247 if (asserted)
4248 bnx2x_attn_int_asserted(bp, asserted);
4249
4250 if (deasserted)
4251 bnx2x_attn_int_deasserted(bp, deasserted);
4252 }
4253
4254 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4255 u16 index, u8 op, u8 update)
4256 {
4257 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4258
4259 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4260 igu_addr);
4261 }
4262
4263 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4264 {
4265 /* No memory barriers */
4266 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4267 mmiowb(); /* keep prod updates ordered */
4268 }
4269
4270 #ifdef BCM_CNIC
4271 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4272 union event_ring_elem *elem)
4273 {
4274 u8 err = elem->message.error;
4275
4276 if (!bp->cnic_eth_dev.starting_cid ||
4277 (cid < bp->cnic_eth_dev.starting_cid &&
4278 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4279 return 1;
4280
4281 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4282
4283 if (unlikely(err)) {
4284
4285 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4286 cid);
4287 bnx2x_panic_dump(bp);
4288 }
4289 bnx2x_cnic_cfc_comp(bp, cid, err);
4290 return 0;
4291 }
4292 #endif
4293
4294 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4295 {
4296 struct bnx2x_mcast_ramrod_params rparam;
4297 int rc;
4298
4299 memset(&rparam, 0, sizeof(rparam));
4300
4301 rparam.mcast_obj = &bp->mcast_obj;
4302
4303 netif_addr_lock_bh(bp->dev);
4304
4305 /* Clear pending state for the last command */
4306 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4307
4308 /* If there are pending mcast commands - send them */
4309 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4310 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4311 if (rc < 0)
4312 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4313 rc);
4314 }
4315
4316 netif_addr_unlock_bh(bp->dev);
4317 }
4318
4319 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4320 union event_ring_elem *elem)
4321 {
4322 unsigned long ramrod_flags = 0;
4323 int rc = 0;
4324 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4325 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4326
4327 /* Always push next commands out, don't wait here */
4328 __set_bit(RAMROD_CONT, &ramrod_flags);
4329
4330 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4331 case BNX2X_FILTER_MAC_PENDING:
4332 #ifdef BCM_CNIC
4333 if (cid == BNX2X_ISCSI_ETH_CID)
4334 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4335 else
4336 #endif
4337 vlan_mac_obj = &bp->fp[cid].mac_obj;
4338
4339 break;
4340 vlan_mac_obj = &bp->fp[cid].mac_obj;
4341
4342 case BNX2X_FILTER_MCAST_PENDING:
4343 /* This is only relevant for 57710 where multicast MACs are
4344 * configured as unicast MACs using the same ramrod.
4345 */
4346 bnx2x_handle_mcast_eqe(bp);
4347 return;
4348 default:
4349 BNX2X_ERR("Unsupported classification command: %d\n",
4350 elem->message.data.eth_event.echo);
4351 return;
4352 }
4353
4354 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4355
4356 if (rc < 0)
4357 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4358 else if (rc > 0)
4359 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4360
4361 }
4362
4363 #ifdef BCM_CNIC
4364 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4365 #endif
4366
4367 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4368 {
4369 netif_addr_lock_bh(bp->dev);
4370
4371 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4372
4373 /* Send rx_mode command again if was requested */
4374 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4375 bnx2x_set_storm_rx_mode(bp);
4376 #ifdef BCM_CNIC
4377 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4378 &bp->sp_state))
4379 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4380 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4381 &bp->sp_state))
4382 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4383 #endif
4384
4385 netif_addr_unlock_bh(bp->dev);
4386 }
4387
4388 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4389 struct bnx2x *bp, u32 cid)
4390 {
4391 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
4392 #ifdef BCM_CNIC
4393 if (cid == BNX2X_FCOE_ETH_CID)
4394 return &bnx2x_fcoe(bp, q_obj);
4395 else
4396 #endif
4397 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4398 }
4399
4400 static void bnx2x_eq_int(struct bnx2x *bp)
4401 {
4402 u16 hw_cons, sw_cons, sw_prod;
4403 union event_ring_elem *elem;
4404 u32 cid;
4405 u8 opcode;
4406 int spqe_cnt = 0;
4407 struct bnx2x_queue_sp_obj *q_obj;
4408 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4409 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4410
4411 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4412
4413 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4414 * when we get the the next-page we nned to adjust so the loop
4415 * condition below will be met. The next element is the size of a
4416 * regular element and hence incrementing by 1
4417 */
4418 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4419 hw_cons++;
4420
4421 /* This function may never run in parallel with itself for a
4422 * specific bp, thus there is no need in "paired" read memory
4423 * barrier here.
4424 */
4425 sw_cons = bp->eq_cons;
4426 sw_prod = bp->eq_prod;
4427
4428 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4429 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4430
4431 for (; sw_cons != hw_cons;
4432 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4433
4434
4435 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4436
4437 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4438 opcode = elem->message.opcode;
4439
4440
4441 /* handle eq element */
4442 switch (opcode) {
4443 case EVENT_RING_OPCODE_STAT_QUERY:
4444 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4445 bp->stats_comp++);
4446 /* nothing to do with stats comp */
4447 goto next_spqe;
4448
4449 case EVENT_RING_OPCODE_CFC_DEL:
4450 /* handle according to cid range */
4451 /*
4452 * we may want to verify here that the bp state is
4453 * HALTING
4454 */
4455 DP(BNX2X_MSG_SP,
4456 "got delete ramrod for MULTI[%d]\n", cid);
4457 #ifdef BCM_CNIC
4458 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4459 goto next_spqe;
4460 #endif
4461 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4462
4463 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4464 break;
4465
4466
4467
4468 goto next_spqe;
4469
4470 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4471 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4472 if (f_obj->complete_cmd(bp, f_obj,
4473 BNX2X_F_CMD_TX_STOP))
4474 break;
4475 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4476 goto next_spqe;
4477
4478 case EVENT_RING_OPCODE_START_TRAFFIC:
4479 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4480 if (f_obj->complete_cmd(bp, f_obj,
4481 BNX2X_F_CMD_TX_START))
4482 break;
4483 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4484 goto next_spqe;
4485 case EVENT_RING_OPCODE_FUNCTION_START:
4486 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4487 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4488 break;
4489
4490 goto next_spqe;
4491
4492 case EVENT_RING_OPCODE_FUNCTION_STOP:
4493 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4494 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4495 break;
4496
4497 goto next_spqe;
4498 }
4499
4500 switch (opcode | bp->state) {
4501 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4502 BNX2X_STATE_OPEN):
4503 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4504 BNX2X_STATE_OPENING_WAIT4_PORT):
4505 cid = elem->message.data.eth_event.echo &
4506 BNX2X_SWCID_MASK;
4507 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4508 cid);
4509 rss_raw->clear_pending(rss_raw);
4510 break;
4511
4512 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4513 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4514 case (EVENT_RING_OPCODE_SET_MAC |
4515 BNX2X_STATE_CLOSING_WAIT4_HALT):
4516 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4517 BNX2X_STATE_OPEN):
4518 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4519 BNX2X_STATE_DIAG):
4520 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4521 BNX2X_STATE_CLOSING_WAIT4_HALT):
4522 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4523 bnx2x_handle_classification_eqe(bp, elem);
4524 break;
4525
4526 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4527 BNX2X_STATE_OPEN):
4528 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4529 BNX2X_STATE_DIAG):
4530 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4531 BNX2X_STATE_CLOSING_WAIT4_HALT):
4532 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4533 bnx2x_handle_mcast_eqe(bp);
4534 break;
4535
4536 case (EVENT_RING_OPCODE_FILTERS_RULES |
4537 BNX2X_STATE_OPEN):
4538 case (EVENT_RING_OPCODE_FILTERS_RULES |
4539 BNX2X_STATE_DIAG):
4540 case (EVENT_RING_OPCODE_FILTERS_RULES |
4541 BNX2X_STATE_CLOSING_WAIT4_HALT):
4542 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4543 bnx2x_handle_rx_mode_eqe(bp);
4544 break;
4545 default:
4546 /* unknown event log error and continue */
4547 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4548 elem->message.opcode, bp->state);
4549 }
4550 next_spqe:
4551 spqe_cnt++;
4552 } /* for */
4553
4554 smp_mb__before_atomic_inc();
4555 atomic_add(spqe_cnt, &bp->eq_spq_left);
4556
4557 bp->eq_cons = sw_cons;
4558 bp->eq_prod = sw_prod;
4559 /* Make sure that above mem writes were issued towards the memory */
4560 smp_wmb();
4561
4562 /* update producer */
4563 bnx2x_update_eq_prod(bp, bp->eq_prod);
4564 }
4565
4566 static void bnx2x_sp_task(struct work_struct *work)
4567 {
4568 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4569 u16 status;
4570
4571 status = bnx2x_update_dsb_idx(bp);
4572 /* if (status == 0) */
4573 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4574
4575 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4576
4577 /* HW attentions */
4578 if (status & BNX2X_DEF_SB_ATT_IDX) {
4579 bnx2x_attn_int(bp);
4580 status &= ~BNX2X_DEF_SB_ATT_IDX;
4581 }
4582
4583 /* SP events: STAT_QUERY and others */
4584 if (status & BNX2X_DEF_SB_IDX) {
4585 #ifdef BCM_CNIC
4586 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4587
4588 if ((!NO_FCOE(bp)) &&
4589 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4590 /*
4591 * Prevent local bottom-halves from running as
4592 * we are going to change the local NAPI list.
4593 */
4594 local_bh_disable();
4595 napi_schedule(&bnx2x_fcoe(bp, napi));
4596 local_bh_enable();
4597 }
4598 #endif
4599 /* Handle EQ completions */
4600 bnx2x_eq_int(bp);
4601
4602 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4603 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4604
4605 status &= ~BNX2X_DEF_SB_IDX;
4606 }
4607
4608 if (unlikely(status))
4609 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4610 status);
4611
4612 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4613 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4614 }
4615
4616 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4617 {
4618 struct net_device *dev = dev_instance;
4619 struct bnx2x *bp = netdev_priv(dev);
4620
4621 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4622 IGU_INT_DISABLE, 0);
4623
4624 #ifdef BNX2X_STOP_ON_ERROR
4625 if (unlikely(bp->panic))
4626 return IRQ_HANDLED;
4627 #endif
4628
4629 #ifdef BCM_CNIC
4630 {
4631 struct cnic_ops *c_ops;
4632
4633 rcu_read_lock();
4634 c_ops = rcu_dereference(bp->cnic_ops);
4635 if (c_ops)
4636 c_ops->cnic_handler(bp->cnic_data, NULL);
4637 rcu_read_unlock();
4638 }
4639 #endif
4640 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4641
4642 return IRQ_HANDLED;
4643 }
4644
4645 /* end of slow path */
4646
4647
4648 void bnx2x_drv_pulse(struct bnx2x *bp)
4649 {
4650 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4651 bp->fw_drv_pulse_wr_seq);
4652 }
4653
4654
4655 static void bnx2x_timer(unsigned long data)
4656 {
4657 u8 cos;
4658 struct bnx2x *bp = (struct bnx2x *) data;
4659
4660 if (!netif_running(bp->dev))
4661 return;
4662
4663 if (poll) {
4664 struct bnx2x_fastpath *fp = &bp->fp[0];
4665
4666 for_each_cos_in_tx_queue(fp, cos)
4667 bnx2x_tx_int(bp, &fp->txdata[cos]);
4668 bnx2x_rx_int(fp, 1000);
4669 }
4670
4671 if (!BP_NOMCP(bp)) {
4672 int mb_idx = BP_FW_MB_IDX(bp);
4673 u32 drv_pulse;
4674 u32 mcp_pulse;
4675
4676 ++bp->fw_drv_pulse_wr_seq;
4677 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4678 /* TBD - add SYSTEM_TIME */
4679 drv_pulse = bp->fw_drv_pulse_wr_seq;
4680 bnx2x_drv_pulse(bp);
4681
4682 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4683 MCP_PULSE_SEQ_MASK);
4684 /* The delta between driver pulse and mcp response
4685 * should be 1 (before mcp response) or 0 (after mcp response)
4686 */
4687 if ((drv_pulse != mcp_pulse) &&
4688 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4689 /* someone lost a heartbeat... */
4690 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4691 drv_pulse, mcp_pulse);
4692 }
4693 }
4694
4695 if (bp->state == BNX2X_STATE_OPEN)
4696 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4697
4698 mod_timer(&bp->timer, jiffies + bp->current_interval);
4699 }
4700
4701 /* end of Statistics */
4702
4703 /* nic init */
4704
4705 /*
4706 * nic init service functions
4707 */
4708
4709 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4710 {
4711 u32 i;
4712 if (!(len%4) && !(addr%4))
4713 for (i = 0; i < len; i += 4)
4714 REG_WR(bp, addr + i, fill);
4715 else
4716 for (i = 0; i < len; i++)
4717 REG_WR8(bp, addr + i, fill);
4718
4719 }
4720
4721 /* helper: writes FP SP data to FW - data_size in dwords */
4722 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4723 int fw_sb_id,
4724 u32 *sb_data_p,
4725 u32 data_size)
4726 {
4727 int index;
4728 for (index = 0; index < data_size; index++)
4729 REG_WR(bp, BAR_CSTRORM_INTMEM +
4730 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4731 sizeof(u32)*index,
4732 *(sb_data_p + index));
4733 }
4734
4735 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4736 {
4737 u32 *sb_data_p;
4738 u32 data_size = 0;
4739 struct hc_status_block_data_e2 sb_data_e2;
4740 struct hc_status_block_data_e1x sb_data_e1x;
4741
4742 /* disable the function first */
4743 if (!CHIP_IS_E1x(bp)) {
4744 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4745 sb_data_e2.common.state = SB_DISABLED;
4746 sb_data_e2.common.p_func.vf_valid = false;
4747 sb_data_p = (u32 *)&sb_data_e2;
4748 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4749 } else {
4750 memset(&sb_data_e1x, 0,
4751 sizeof(struct hc_status_block_data_e1x));
4752 sb_data_e1x.common.state = SB_DISABLED;
4753 sb_data_e1x.common.p_func.vf_valid = false;
4754 sb_data_p = (u32 *)&sb_data_e1x;
4755 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4756 }
4757 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4758
4759 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4760 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4761 CSTORM_STATUS_BLOCK_SIZE);
4762 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4763 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4764 CSTORM_SYNC_BLOCK_SIZE);
4765 }
4766
4767 /* helper: writes SP SB data to FW */
4768 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4769 struct hc_sp_status_block_data *sp_sb_data)
4770 {
4771 int func = BP_FUNC(bp);
4772 int i;
4773 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4774 REG_WR(bp, BAR_CSTRORM_INTMEM +
4775 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4776 i*sizeof(u32),
4777 *((u32 *)sp_sb_data + i));
4778 }
4779
4780 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4781 {
4782 int func = BP_FUNC(bp);
4783 struct hc_sp_status_block_data sp_sb_data;
4784 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4785
4786 sp_sb_data.state = SB_DISABLED;
4787 sp_sb_data.p_func.vf_valid = false;
4788
4789 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4790
4791 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4792 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4793 CSTORM_SP_STATUS_BLOCK_SIZE);
4794 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4796 CSTORM_SP_SYNC_BLOCK_SIZE);
4797
4798 }
4799
4800
4801 static inline
4802 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4803 int igu_sb_id, int igu_seg_id)
4804 {
4805 hc_sm->igu_sb_id = igu_sb_id;
4806 hc_sm->igu_seg_id = igu_seg_id;
4807 hc_sm->timer_value = 0xFF;
4808 hc_sm->time_to_expire = 0xFFFFFFFF;
4809 }
4810
4811 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4812 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4813 {
4814 int igu_seg_id;
4815
4816 struct hc_status_block_data_e2 sb_data_e2;
4817 struct hc_status_block_data_e1x sb_data_e1x;
4818 struct hc_status_block_sm *hc_sm_p;
4819 int data_size;
4820 u32 *sb_data_p;
4821
4822 if (CHIP_INT_MODE_IS_BC(bp))
4823 igu_seg_id = HC_SEG_ACCESS_NORM;
4824 else
4825 igu_seg_id = IGU_SEG_ACCESS_NORM;
4826
4827 bnx2x_zero_fp_sb(bp, fw_sb_id);
4828
4829 if (!CHIP_IS_E1x(bp)) {
4830 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4831 sb_data_e2.common.state = SB_ENABLED;
4832 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4833 sb_data_e2.common.p_func.vf_id = vfid;
4834 sb_data_e2.common.p_func.vf_valid = vf_valid;
4835 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4836 sb_data_e2.common.same_igu_sb_1b = true;
4837 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4838 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4839 hc_sm_p = sb_data_e2.common.state_machine;
4840 sb_data_p = (u32 *)&sb_data_e2;
4841 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4842 } else {
4843 memset(&sb_data_e1x, 0,
4844 sizeof(struct hc_status_block_data_e1x));
4845 sb_data_e1x.common.state = SB_ENABLED;
4846 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4847 sb_data_e1x.common.p_func.vf_id = 0xff;
4848 sb_data_e1x.common.p_func.vf_valid = false;
4849 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4850 sb_data_e1x.common.same_igu_sb_1b = true;
4851 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4852 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4853 hc_sm_p = sb_data_e1x.common.state_machine;
4854 sb_data_p = (u32 *)&sb_data_e1x;
4855 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4856 }
4857
4858 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4859 igu_sb_id, igu_seg_id);
4860 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4861 igu_sb_id, igu_seg_id);
4862
4863 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4864
4865 /* write indecies to HW */
4866 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4867 }
4868
4869 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4870 u16 tx_usec, u16 rx_usec)
4871 {
4872 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4873 false, rx_usec);
4874 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4875 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4876 tx_usec);
4877 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4878 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4879 tx_usec);
4880 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4881 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4882 tx_usec);
4883 }
4884
4885 static void bnx2x_init_def_sb(struct bnx2x *bp)
4886 {
4887 struct host_sp_status_block *def_sb = bp->def_status_blk;
4888 dma_addr_t mapping = bp->def_status_blk_mapping;
4889 int igu_sp_sb_index;
4890 int igu_seg_id;
4891 int port = BP_PORT(bp);
4892 int func = BP_FUNC(bp);
4893 int reg_offset;
4894 u64 section;
4895 int index;
4896 struct hc_sp_status_block_data sp_sb_data;
4897 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4898
4899 if (CHIP_INT_MODE_IS_BC(bp)) {
4900 igu_sp_sb_index = DEF_SB_IGU_ID;
4901 igu_seg_id = HC_SEG_ACCESS_DEF;
4902 } else {
4903 igu_sp_sb_index = bp->igu_dsb_id;
4904 igu_seg_id = IGU_SEG_ACCESS_DEF;
4905 }
4906
4907 /* ATTN */
4908 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4909 atten_status_block);
4910 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4911
4912 bp->attn_state = 0;
4913
4914 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4915 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4916 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4917 int sindex;
4918 /* take care of sig[0]..sig[4] */
4919 for (sindex = 0; sindex < 4; sindex++)
4920 bp->attn_group[index].sig[sindex] =
4921 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4922
4923 if (!CHIP_IS_E1x(bp))
4924 /*
4925 * enable5 is separate from the rest of the registers,
4926 * and therefore the address skip is 4
4927 * and not 16 between the different groups
4928 */
4929 bp->attn_group[index].sig[4] = REG_RD(bp,
4930 reg_offset + 0x10 + 0x4*index);
4931 else
4932 bp->attn_group[index].sig[4] = 0;
4933 }
4934
4935 if (bp->common.int_block == INT_BLOCK_HC) {
4936 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4937 HC_REG_ATTN_MSG0_ADDR_L);
4938
4939 REG_WR(bp, reg_offset, U64_LO(section));
4940 REG_WR(bp, reg_offset + 4, U64_HI(section));
4941 } else if (!CHIP_IS_E1x(bp)) {
4942 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4943 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4944 }
4945
4946 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4947 sp_sb);
4948
4949 bnx2x_zero_sp_sb(bp);
4950
4951 sp_sb_data.state = SB_ENABLED;
4952 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4953 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4954 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4955 sp_sb_data.igu_seg_id = igu_seg_id;
4956 sp_sb_data.p_func.pf_id = func;
4957 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4958 sp_sb_data.p_func.vf_id = 0xff;
4959
4960 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4961
4962 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4963 }
4964
4965 void bnx2x_update_coalesce(struct bnx2x *bp)
4966 {
4967 int i;
4968
4969 for_each_eth_queue(bp, i)
4970 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4971 bp->tx_ticks, bp->rx_ticks);
4972 }
4973
4974 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4975 {
4976 spin_lock_init(&bp->spq_lock);
4977 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4978
4979 bp->spq_prod_idx = 0;
4980 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4981 bp->spq_prod_bd = bp->spq;
4982 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4983 }
4984
4985 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4986 {
4987 int i;
4988 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4989 union event_ring_elem *elem =
4990 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4991
4992 elem->next_page.addr.hi =
4993 cpu_to_le32(U64_HI(bp->eq_mapping +
4994 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4995 elem->next_page.addr.lo =
4996 cpu_to_le32(U64_LO(bp->eq_mapping +
4997 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4998 }
4999 bp->eq_cons = 0;
5000 bp->eq_prod = NUM_EQ_DESC;
5001 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5002 /* we want a warning message before it gets rought... */
5003 atomic_set(&bp->eq_spq_left,
5004 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5005 }
5006
5007
5008 /* called with netif_addr_lock_bh() */
5009 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5010 unsigned long rx_mode_flags,
5011 unsigned long rx_accept_flags,
5012 unsigned long tx_accept_flags,
5013 unsigned long ramrod_flags)
5014 {
5015 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5016 int rc;
5017
5018 memset(&ramrod_param, 0, sizeof(ramrod_param));
5019
5020 /* Prepare ramrod parameters */
5021 ramrod_param.cid = 0;
5022 ramrod_param.cl_id = cl_id;
5023 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5024 ramrod_param.func_id = BP_FUNC(bp);
5025
5026 ramrod_param.pstate = &bp->sp_state;
5027 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5028
5029 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5030 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5031
5032 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5033
5034 ramrod_param.ramrod_flags = ramrod_flags;
5035 ramrod_param.rx_mode_flags = rx_mode_flags;
5036
5037 ramrod_param.rx_accept_flags = rx_accept_flags;
5038 ramrod_param.tx_accept_flags = tx_accept_flags;
5039
5040 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5041 if (rc < 0) {
5042 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5043 return;
5044 }
5045 }
5046
5047 /* called with netif_addr_lock_bh() */
5048 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5049 {
5050 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5051 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5052
5053 #ifdef BCM_CNIC
5054 if (!NO_FCOE(bp))
5055
5056 /* Configure rx_mode of FCoE Queue */
5057 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5058 #endif
5059
5060 switch (bp->rx_mode) {
5061 case BNX2X_RX_MODE_NONE:
5062 /*
5063 * 'drop all' supersedes any accept flags that may have been
5064 * passed to the function.
5065 */
5066 break;
5067 case BNX2X_RX_MODE_NORMAL:
5068 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5069 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5070 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5071
5072 /* internal switching mode */
5073 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5074 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5075 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5076
5077 break;
5078 case BNX2X_RX_MODE_ALLMULTI:
5079 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5080 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5081 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5082
5083 /* internal switching mode */
5084 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5085 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5086 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5087
5088 break;
5089 case BNX2X_RX_MODE_PROMISC:
5090 /* According to deffinition of SI mode, iface in promisc mode
5091 * should receive matched and unmatched (in resolution of port)
5092 * unicast packets.
5093 */
5094 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5095 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5096 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5097 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5098
5099 /* internal switching mode */
5100 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5101 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5102
5103 if (IS_MF_SI(bp))
5104 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5105 else
5106 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5107
5108 break;
5109 default:
5110 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5111 return;
5112 }
5113
5114 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5115 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5117 }
5118
5119 __set_bit(RAMROD_RX, &ramrod_flags);
5120 __set_bit(RAMROD_TX, &ramrod_flags);
5121
5122 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5123 tx_accept_flags, ramrod_flags);
5124 }
5125
5126 static void bnx2x_init_internal_common(struct bnx2x *bp)
5127 {
5128 int i;
5129
5130 if (IS_MF_SI(bp))
5131 /*
5132 * In switch independent mode, the TSTORM needs to accept
5133 * packets that failed classification, since approximate match
5134 * mac addresses aren't written to NIG LLH
5135 */
5136 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5137 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5138 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5139 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5140 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5141
5142 /* Zero this manually as its initialization is
5143 currently missing in the initTool */
5144 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5145 REG_WR(bp, BAR_USTRORM_INTMEM +
5146 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5147 if (!CHIP_IS_E1x(bp)) {
5148 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5149 CHIP_INT_MODE_IS_BC(bp) ?
5150 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5151 }
5152 }
5153
5154 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5155 {
5156 switch (load_code) {
5157 case FW_MSG_CODE_DRV_LOAD_COMMON:
5158 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5159 bnx2x_init_internal_common(bp);
5160 /* no break */
5161
5162 case FW_MSG_CODE_DRV_LOAD_PORT:
5163 /* nothing to do */
5164 /* no break */
5165
5166 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5167 /* internal memory per function is
5168 initialized inside bnx2x_pf_init */
5169 break;
5170
5171 default:
5172 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5173 break;
5174 }
5175 }
5176
5177 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5178 {
5179 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5180 }
5181
5182 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5183 {
5184 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5185 }
5186
5187 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5188 {
5189 if (CHIP_IS_E1x(fp->bp))
5190 return BP_L_ID(fp->bp) + fp->index;
5191 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5192 return bnx2x_fp_igu_sb_id(fp);
5193 }
5194
5195 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5196 {
5197 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5198 u8 cos;
5199 unsigned long q_type = 0;
5200 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5201
5202 fp->cid = fp_idx;
5203 fp->cl_id = bnx2x_fp_cl_id(fp);
5204 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5205 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5206 /* qZone id equals to FW (per path) client id */
5207 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5208
5209 /* init shortcut */
5210 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5211 /* Setup SB indicies */
5212 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5213
5214 /* Configure Queue State object */
5215 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5216 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5217
5218 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5219
5220 /* init tx data */
5221 for_each_cos_in_tx_queue(fp, cos) {
5222 bnx2x_init_txdata(bp, &fp->txdata[cos],
5223 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5224 FP_COS_TO_TXQ(fp, cos),
5225 BNX2X_TX_SB_INDEX_BASE + cos);
5226 cids[cos] = fp->txdata[cos].cid;
5227 }
5228
5229 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5230 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5231 bnx2x_sp_mapping(bp, q_rdata), q_type);
5232
5233 /**
5234 * Configure classification DBs: Always enable Tx switching
5235 */
5236 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5237
5238 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5239 "cl_id %d fw_sb %d igu_sb %d\n",
5240 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5241 fp->igu_sb_id);
5242 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5243 fp->fw_sb_id, fp->igu_sb_id);
5244
5245 bnx2x_update_fpsb_idx(fp);
5246 }
5247
5248 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5249 {
5250 int i;
5251
5252 for_each_eth_queue(bp, i)
5253 bnx2x_init_eth_fp(bp, i);
5254 #ifdef BCM_CNIC
5255 if (!NO_FCOE(bp))
5256 bnx2x_init_fcoe_fp(bp);
5257
5258 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5259 BNX2X_VF_ID_INVALID, false,
5260 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5261
5262 #endif
5263
5264 /* Initialize MOD_ABS interrupts */
5265 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5266 bp->common.shmem_base, bp->common.shmem2_base,
5267 BP_PORT(bp));
5268 /* ensure status block indices were read */
5269 rmb();
5270
5271 bnx2x_init_def_sb(bp);
5272 bnx2x_update_dsb_idx(bp);
5273 bnx2x_init_rx_rings(bp);
5274 bnx2x_init_tx_rings(bp);
5275 bnx2x_init_sp_ring(bp);
5276 bnx2x_init_eq_ring(bp);
5277 bnx2x_init_internal(bp, load_code);
5278 bnx2x_pf_init(bp);
5279 bnx2x_stats_init(bp);
5280
5281 /* flush all before enabling interrupts */
5282 mb();
5283 mmiowb();
5284
5285 bnx2x_int_enable(bp);
5286
5287 /* Check for SPIO5 */
5288 bnx2x_attn_int_deasserted0(bp,
5289 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5290 AEU_INPUTS_ATTN_BITS_SPIO5);
5291 }
5292
5293 /* end of nic init */
5294
5295 /*
5296 * gzip service functions
5297 */
5298
5299 static int bnx2x_gunzip_init(struct bnx2x *bp)
5300 {
5301 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5302 &bp->gunzip_mapping, GFP_KERNEL);
5303 if (bp->gunzip_buf == NULL)
5304 goto gunzip_nomem1;
5305
5306 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5307 if (bp->strm == NULL)
5308 goto gunzip_nomem2;
5309
5310 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5311 if (bp->strm->workspace == NULL)
5312 goto gunzip_nomem3;
5313
5314 return 0;
5315
5316 gunzip_nomem3:
5317 kfree(bp->strm);
5318 bp->strm = NULL;
5319
5320 gunzip_nomem2:
5321 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5322 bp->gunzip_mapping);
5323 bp->gunzip_buf = NULL;
5324
5325 gunzip_nomem1:
5326 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5327 " un-compression\n");
5328 return -ENOMEM;
5329 }
5330
5331 static void bnx2x_gunzip_end(struct bnx2x *bp)
5332 {
5333 if (bp->strm) {
5334 vfree(bp->strm->workspace);
5335 kfree(bp->strm);
5336 bp->strm = NULL;
5337 }
5338
5339 if (bp->gunzip_buf) {
5340 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5341 bp->gunzip_mapping);
5342 bp->gunzip_buf = NULL;
5343 }
5344 }
5345
5346 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5347 {
5348 int n, rc;
5349
5350 /* check gzip header */
5351 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5352 BNX2X_ERR("Bad gzip header\n");
5353 return -EINVAL;
5354 }
5355
5356 n = 10;
5357
5358 #define FNAME 0x8
5359
5360 if (zbuf[3] & FNAME)
5361 while ((zbuf[n++] != 0) && (n < len));
5362
5363 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5364 bp->strm->avail_in = len - n;
5365 bp->strm->next_out = bp->gunzip_buf;
5366 bp->strm->avail_out = FW_BUF_SIZE;
5367
5368 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5369 if (rc != Z_OK)
5370 return rc;
5371
5372 rc = zlib_inflate(bp->strm, Z_FINISH);
5373 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5374 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5375 bp->strm->msg);
5376
5377 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5378 if (bp->gunzip_outlen & 0x3)
5379 netdev_err(bp->dev, "Firmware decompression error:"
5380 " gunzip_outlen (%d) not aligned\n",
5381 bp->gunzip_outlen);
5382 bp->gunzip_outlen >>= 2;
5383
5384 zlib_inflateEnd(bp->strm);
5385
5386 if (rc == Z_STREAM_END)
5387 return 0;
5388
5389 return rc;
5390 }
5391
5392 /* nic load/unload */
5393
5394 /*
5395 * General service functions
5396 */
5397
5398 /* send a NIG loopback debug packet */
5399 static void bnx2x_lb_pckt(struct bnx2x *bp)
5400 {
5401 u32 wb_write[3];
5402
5403 /* Ethernet source and destination addresses */
5404 wb_write[0] = 0x55555555;
5405 wb_write[1] = 0x55555555;
5406 wb_write[2] = 0x20; /* SOP */
5407 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5408
5409 /* NON-IP protocol */
5410 wb_write[0] = 0x09000000;
5411 wb_write[1] = 0x55555555;
5412 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5413 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5414 }
5415
5416 /* some of the internal memories
5417 * are not directly readable from the driver
5418 * to test them we send debug packets
5419 */
5420 static int bnx2x_int_mem_test(struct bnx2x *bp)
5421 {
5422 int factor;
5423 int count, i;
5424 u32 val = 0;
5425
5426 if (CHIP_REV_IS_FPGA(bp))
5427 factor = 120;
5428 else if (CHIP_REV_IS_EMUL(bp))
5429 factor = 200;
5430 else
5431 factor = 1;
5432
5433 /* Disable inputs of parser neighbor blocks */
5434 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5435 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5436 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5437 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5438
5439 /* Write 0 to parser credits for CFC search request */
5440 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5441
5442 /* send Ethernet packet */
5443 bnx2x_lb_pckt(bp);
5444
5445 /* TODO do i reset NIG statistic? */
5446 /* Wait until NIG register shows 1 packet of size 0x10 */
5447 count = 1000 * factor;
5448 while (count) {
5449
5450 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5451 val = *bnx2x_sp(bp, wb_data[0]);
5452 if (val == 0x10)
5453 break;
5454
5455 msleep(10);
5456 count--;
5457 }
5458 if (val != 0x10) {
5459 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5460 return -1;
5461 }
5462
5463 /* Wait until PRS register shows 1 packet */
5464 count = 1000 * factor;
5465 while (count) {
5466 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5467 if (val == 1)
5468 break;
5469
5470 msleep(10);
5471 count--;
5472 }
5473 if (val != 0x1) {
5474 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5475 return -2;
5476 }
5477
5478 /* Reset and init BRB, PRS */
5479 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5480 msleep(50);
5481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5482 msleep(50);
5483 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5484 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5485
5486 DP(NETIF_MSG_HW, "part2\n");
5487
5488 /* Disable inputs of parser neighbor blocks */
5489 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5490 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5491 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5492 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5493
5494 /* Write 0 to parser credits for CFC search request */
5495 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5496
5497 /* send 10 Ethernet packets */
5498 for (i = 0; i < 10; i++)
5499 bnx2x_lb_pckt(bp);
5500
5501 /* Wait until NIG register shows 10 + 1
5502 packets of size 11*0x10 = 0xb0 */
5503 count = 1000 * factor;
5504 while (count) {
5505
5506 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5507 val = *bnx2x_sp(bp, wb_data[0]);
5508 if (val == 0xb0)
5509 break;
5510
5511 msleep(10);
5512 count--;
5513 }
5514 if (val != 0xb0) {
5515 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5516 return -3;
5517 }
5518
5519 /* Wait until PRS register shows 2 packets */
5520 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5521 if (val != 2)
5522 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5523
5524 /* Write 1 to parser credits for CFC search request */
5525 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5526
5527 /* Wait until PRS register shows 3 packets */
5528 msleep(10 * factor);
5529 /* Wait until NIG register shows 1 packet of size 0x10 */
5530 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5531 if (val != 3)
5532 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5533
5534 /* clear NIG EOP FIFO */
5535 for (i = 0; i < 11; i++)
5536 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5537 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5538 if (val != 1) {
5539 BNX2X_ERR("clear of NIG failed\n");
5540 return -4;
5541 }
5542
5543 /* Reset and init BRB, PRS, NIG */
5544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5545 msleep(50);
5546 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5547 msleep(50);
5548 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5549 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5550 #ifndef BCM_CNIC
5551 /* set NIC mode */
5552 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5553 #endif
5554
5555 /* Enable inputs of parser neighbor blocks */
5556 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5557 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5558 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5559 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5560
5561 DP(NETIF_MSG_HW, "done\n");
5562
5563 return 0; /* OK */
5564 }
5565
5566 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5567 {
5568 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5569 if (!CHIP_IS_E1x(bp))
5570 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5571 else
5572 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5573 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5574 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5575 /*
5576 * mask read length error interrupts in brb for parser
5577 * (parsing unit and 'checksum and crc' unit)
5578 * these errors are legal (PU reads fixed length and CAC can cause
5579 * read length error on truncated packets)
5580 */
5581 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5582 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5583 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5584 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5585 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5586 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5587 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5588 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5589 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5590 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5591 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5592 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5593 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5594 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5595 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5596 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5597 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5598 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5599 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5600
5601 if (CHIP_REV_IS_FPGA(bp))
5602 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5603 else if (!CHIP_IS_E1x(bp))
5604 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5605 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5606 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5607 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5608 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5609 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5610 else
5611 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5612 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5613 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5614 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5615 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5616
5617 if (!CHIP_IS_E1x(bp))
5618 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5619 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5620
5621 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5622 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5623 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5624 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5625 }
5626
5627 static void bnx2x_reset_common(struct bnx2x *bp)
5628 {
5629 u32 val = 0x1400;
5630
5631 /* reset_common */
5632 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5633 0xd3ffff7f);
5634
5635 if (CHIP_IS_E3(bp)) {
5636 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5637 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5638 }
5639
5640 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5641 }
5642
5643 static void bnx2x_setup_dmae(struct bnx2x *bp)
5644 {
5645 bp->dmae_ready = 0;
5646 spin_lock_init(&bp->dmae_lock);
5647 }
5648
5649 static void bnx2x_init_pxp(struct bnx2x *bp)
5650 {
5651 u16 devctl;
5652 int r_order, w_order;
5653
5654 pci_read_config_word(bp->pdev,
5655 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5656 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5657 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5658 if (bp->mrrs == -1)
5659 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5660 else {
5661 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5662 r_order = bp->mrrs;
5663 }
5664
5665 bnx2x_init_pxp_arb(bp, r_order, w_order);
5666 }
5667
5668 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5669 {
5670 int is_required;
5671 u32 val;
5672 int port;
5673
5674 if (BP_NOMCP(bp))
5675 return;
5676
5677 is_required = 0;
5678 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5679 SHARED_HW_CFG_FAN_FAILURE_MASK;
5680
5681 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5682 is_required = 1;
5683
5684 /*
5685 * The fan failure mechanism is usually related to the PHY type since
5686 * the power consumption of the board is affected by the PHY. Currently,
5687 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5688 */
5689 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5690 for (port = PORT_0; port < PORT_MAX; port++) {
5691 is_required |=
5692 bnx2x_fan_failure_det_req(
5693 bp,
5694 bp->common.shmem_base,
5695 bp->common.shmem2_base,
5696 port);
5697 }
5698
5699 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5700
5701 if (is_required == 0)
5702 return;
5703
5704 /* Fan failure is indicated by SPIO 5 */
5705 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5706 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5707
5708 /* set to active low mode */
5709 val = REG_RD(bp, MISC_REG_SPIO_INT);
5710 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5711 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5712 REG_WR(bp, MISC_REG_SPIO_INT, val);
5713
5714 /* enable interrupt to signal the IGU */
5715 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5716 val |= (1 << MISC_REGISTERS_SPIO_5);
5717 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5718 }
5719
5720 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5721 {
5722 u32 offset = 0;
5723
5724 if (CHIP_IS_E1(bp))
5725 return;
5726 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5727 return;
5728
5729 switch (BP_ABS_FUNC(bp)) {
5730 case 0:
5731 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5732 break;
5733 case 1:
5734 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5735 break;
5736 case 2:
5737 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5738 break;
5739 case 3:
5740 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5741 break;
5742 case 4:
5743 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5744 break;
5745 case 5:
5746 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5747 break;
5748 case 6:
5749 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5750 break;
5751 case 7:
5752 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5753 break;
5754 default:
5755 return;
5756 }
5757
5758 REG_WR(bp, offset, pretend_func_num);
5759 REG_RD(bp, offset);
5760 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5761 }
5762
5763 void bnx2x_pf_disable(struct bnx2x *bp)
5764 {
5765 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5766 val &= ~IGU_PF_CONF_FUNC_EN;
5767
5768 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5769 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5770 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5771 }
5772
5773 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5774 {
5775 u32 shmem_base[2], shmem2_base[2];
5776 shmem_base[0] = bp->common.shmem_base;
5777 shmem2_base[0] = bp->common.shmem2_base;
5778 if (!CHIP_IS_E1x(bp)) {
5779 shmem_base[1] =
5780 SHMEM2_RD(bp, other_shmem_base_addr);
5781 shmem2_base[1] =
5782 SHMEM2_RD(bp, other_shmem2_base_addr);
5783 }
5784 bnx2x_acquire_phy_lock(bp);
5785 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5786 bp->common.chip_id);
5787 bnx2x_release_phy_lock(bp);
5788 }
5789
5790 /**
5791 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5792 *
5793 * @bp: driver handle
5794 */
5795 static int bnx2x_init_hw_common(struct bnx2x *bp)
5796 {
5797 u32 val;
5798
5799 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5800
5801 /*
5802 * take the UNDI lock to protect undi_unload flow from accessing
5803 * registers while we're resetting the chip
5804 */
5805 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5806
5807 bnx2x_reset_common(bp);
5808 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5809
5810 val = 0xfffc;
5811 if (CHIP_IS_E3(bp)) {
5812 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5813 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5814 }
5815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5816
5817 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5818
5819 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5820
5821 if (!CHIP_IS_E1x(bp)) {
5822 u8 abs_func_id;
5823
5824 /**
5825 * 4-port mode or 2-port mode we need to turn of master-enable
5826 * for everyone, after that, turn it back on for self.
5827 * so, we disregard multi-function or not, and always disable
5828 * for all functions on the given path, this means 0,2,4,6 for
5829 * path 0 and 1,3,5,7 for path 1
5830 */
5831 for (abs_func_id = BP_PATH(bp);
5832 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5833 if (abs_func_id == BP_ABS_FUNC(bp)) {
5834 REG_WR(bp,
5835 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5836 1);
5837 continue;
5838 }
5839
5840 bnx2x_pretend_func(bp, abs_func_id);
5841 /* clear pf enable */
5842 bnx2x_pf_disable(bp);
5843 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5844 }
5845 }
5846
5847 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5848 if (CHIP_IS_E1(bp)) {
5849 /* enable HW interrupt from PXP on USDM overflow
5850 bit 16 on INT_MASK_0 */
5851 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5852 }
5853
5854 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5855 bnx2x_init_pxp(bp);
5856
5857 #ifdef __BIG_ENDIAN
5858 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5859 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5860 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5861 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5862 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5863 /* make sure this value is 0 */
5864 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5865
5866 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5867 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5868 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5869 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5870 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5871 #endif
5872
5873 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5874
5875 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5876 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5877
5878 /* let the HW do it's magic ... */
5879 msleep(100);
5880 /* finish PXP init */
5881 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5882 if (val != 1) {
5883 BNX2X_ERR("PXP2 CFG failed\n");
5884 return -EBUSY;
5885 }
5886 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5887 if (val != 1) {
5888 BNX2X_ERR("PXP2 RD_INIT failed\n");
5889 return -EBUSY;
5890 }
5891
5892 /* Timers bug workaround E2 only. We need to set the entire ILT to
5893 * have entries with value "0" and valid bit on.
5894 * This needs to be done by the first PF that is loaded in a path
5895 * (i.e. common phase)
5896 */
5897 if (!CHIP_IS_E1x(bp)) {
5898 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5899 * (i.e. vnic3) to start even if it is marked as "scan-off".
5900 * This occurs when a different function (func2,3) is being marked
5901 * as "scan-off". Real-life scenario for example: if a driver is being
5902 * load-unloaded while func6,7 are down. This will cause the timer to access
5903 * the ilt, translate to a logical address and send a request to read/write.
5904 * Since the ilt for the function that is down is not valid, this will cause
5905 * a translation error which is unrecoverable.
5906 * The Workaround is intended to make sure that when this happens nothing fatal
5907 * will occur. The workaround:
5908 * 1. First PF driver which loads on a path will:
5909 * a. After taking the chip out of reset, by using pretend,
5910 * it will write "0" to the following registers of
5911 * the other vnics.
5912 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5913 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5914 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5915 * And for itself it will write '1' to
5916 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5917 * dmae-operations (writing to pram for example.)
5918 * note: can be done for only function 6,7 but cleaner this
5919 * way.
5920 * b. Write zero+valid to the entire ILT.
5921 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5922 * VNIC3 (of that port). The range allocated will be the
5923 * entire ILT. This is needed to prevent ILT range error.
5924 * 2. Any PF driver load flow:
5925 * a. ILT update with the physical addresses of the allocated
5926 * logical pages.
5927 * b. Wait 20msec. - note that this timeout is needed to make
5928 * sure there are no requests in one of the PXP internal
5929 * queues with "old" ILT addresses.
5930 * c. PF enable in the PGLC.
5931 * d. Clear the was_error of the PF in the PGLC. (could have
5932 * occured while driver was down)
5933 * e. PF enable in the CFC (WEAK + STRONG)
5934 * f. Timers scan enable
5935 * 3. PF driver unload flow:
5936 * a. Clear the Timers scan_en.
5937 * b. Polling for scan_on=0 for that PF.
5938 * c. Clear the PF enable bit in the PXP.
5939 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5940 * e. Write zero+valid to all ILT entries (The valid bit must
5941 * stay set)
5942 * f. If this is VNIC 3 of a port then also init
5943 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5944 * to the last enrty in the ILT.
5945 *
5946 * Notes:
5947 * Currently the PF error in the PGLC is non recoverable.
5948 * In the future the there will be a recovery routine for this error.
5949 * Currently attention is masked.
5950 * Having an MCP lock on the load/unload process does not guarantee that
5951 * there is no Timer disable during Func6/7 enable. This is because the
5952 * Timers scan is currently being cleared by the MCP on FLR.
5953 * Step 2.d can be done only for PF6/7 and the driver can also check if
5954 * there is error before clearing it. But the flow above is simpler and
5955 * more general.
5956 * All ILT entries are written by zero+valid and not just PF6/7
5957 * ILT entries since in the future the ILT entries allocation for
5958 * PF-s might be dynamic.
5959 */
5960 struct ilt_client_info ilt_cli;
5961 struct bnx2x_ilt ilt;
5962 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5963 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5964
5965 /* initialize dummy TM client */
5966 ilt_cli.start = 0;
5967 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5968 ilt_cli.client_num = ILT_CLIENT_TM;
5969
5970 /* Step 1: set zeroes to all ilt page entries with valid bit on
5971 * Step 2: set the timers first/last ilt entry to point
5972 * to the entire range to prevent ILT range error for 3rd/4th
5973 * vnic (this code assumes existance of the vnic)
5974 *
5975 * both steps performed by call to bnx2x_ilt_client_init_op()
5976 * with dummy TM client
5977 *
5978 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5979 * and his brother are split registers
5980 */
5981 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5982 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5983 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5984
5985 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5986 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5987 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5988 }
5989
5990
5991 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5992 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5993
5994 if (!CHIP_IS_E1x(bp)) {
5995 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5996 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5997 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5998
5999 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6000
6001 /* let the HW do it's magic ... */
6002 do {
6003 msleep(200);
6004 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6005 } while (factor-- && (val != 1));
6006
6007 if (val != 1) {
6008 BNX2X_ERR("ATC_INIT failed\n");
6009 return -EBUSY;
6010 }
6011 }
6012
6013 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6014
6015 /* clean the DMAE memory */
6016 bp->dmae_ready = 1;
6017 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6018
6019 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6020
6021 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6022
6023 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6024
6025 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6026
6027 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6028 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6029 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6030 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6031
6032 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6033
6034
6035 /* QM queues pointers table */
6036 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6037
6038 /* soft reset pulse */
6039 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6040 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6041
6042 #ifdef BCM_CNIC
6043 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6044 #endif
6045
6046 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6047 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6048 if (!CHIP_REV_IS_SLOW(bp))
6049 /* enable hw interrupt from doorbell Q */
6050 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6051
6052 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6053
6054 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6055 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6056
6057 if (!CHIP_IS_E1(bp))
6058 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6059
6060 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6061 /* Bit-map indicating which L2 hdrs may appear
6062 * after the basic Ethernet header
6063 */
6064 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6065 bp->path_has_ovlan ? 7 : 6);
6066
6067 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6068 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6069 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6070 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6071
6072 if (!CHIP_IS_E1x(bp)) {
6073 /* reset VFC memories */
6074 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6075 VFC_MEMORIES_RST_REG_CAM_RST |
6076 VFC_MEMORIES_RST_REG_RAM_RST);
6077 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6078 VFC_MEMORIES_RST_REG_CAM_RST |
6079 VFC_MEMORIES_RST_REG_RAM_RST);
6080
6081 msleep(20);
6082 }
6083
6084 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6085 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6086 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6087 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6088
6089 /* sync semi rtc */
6090 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6091 0x80000000);
6092 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6093 0x80000000);
6094
6095 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6096 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6097 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6098
6099 if (!CHIP_IS_E1x(bp))
6100 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6101 bp->path_has_ovlan ? 7 : 6);
6102
6103 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6104
6105 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6106
6107 #ifdef BCM_CNIC
6108 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6109 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6110 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6111 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6112 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6113 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6114 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6115 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6116 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6117 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6118 #endif
6119 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6120
6121 if (sizeof(union cdu_context) != 1024)
6122 /* we currently assume that a context is 1024 bytes */
6123 dev_alert(&bp->pdev->dev, "please adjust the size "
6124 "of cdu_context(%ld)\n",
6125 (long)sizeof(union cdu_context));
6126
6127 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6128 val = (4 << 24) + (0 << 12) + 1024;
6129 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6130
6131 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6132 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6133 /* enable context validation interrupt from CFC */
6134 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6135
6136 /* set the thresholds to prevent CFC/CDU race */
6137 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6138
6139 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6140
6141 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6142 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6143
6144 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6145 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6146
6147 /* Reset PCIE errors for debug */
6148 REG_WR(bp, 0x2814, 0xffffffff);
6149 REG_WR(bp, 0x3820, 0xffffffff);
6150
6151 if (!CHIP_IS_E1x(bp)) {
6152 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6153 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6154 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6155 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6156 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6157 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6158 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6159 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6160 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6161 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6162 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6163 }
6164
6165 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6166 if (!CHIP_IS_E1(bp)) {
6167 /* in E3 this done in per-port section */
6168 if (!CHIP_IS_E3(bp))
6169 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6170 }
6171 if (CHIP_IS_E1H(bp))
6172 /* not applicable for E2 (and above ...) */
6173 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6174
6175 if (CHIP_REV_IS_SLOW(bp))
6176 msleep(200);
6177
6178 /* finish CFC init */
6179 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6180 if (val != 1) {
6181 BNX2X_ERR("CFC LL_INIT failed\n");
6182 return -EBUSY;
6183 }
6184 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6185 if (val != 1) {
6186 BNX2X_ERR("CFC AC_INIT failed\n");
6187 return -EBUSY;
6188 }
6189 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6190 if (val != 1) {
6191 BNX2X_ERR("CFC CAM_INIT failed\n");
6192 return -EBUSY;
6193 }
6194 REG_WR(bp, CFC_REG_DEBUG0, 0);
6195
6196 if (CHIP_IS_E1(bp)) {
6197 /* read NIG statistic
6198 to see if this is our first up since powerup */
6199 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6200 val = *bnx2x_sp(bp, wb_data[0]);
6201
6202 /* do internal memory self test */
6203 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6204 BNX2X_ERR("internal mem self test failed\n");
6205 return -EBUSY;
6206 }
6207 }
6208
6209 bnx2x_setup_fan_failure_detection(bp);
6210
6211 /* clear PXP2 attentions */
6212 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6213
6214 bnx2x_enable_blocks_attention(bp);
6215 bnx2x_enable_blocks_parity(bp);
6216
6217 if (!BP_NOMCP(bp)) {
6218 if (CHIP_IS_E1x(bp))
6219 bnx2x__common_init_phy(bp);
6220 } else
6221 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6222
6223 return 0;
6224 }
6225
6226 /**
6227 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6228 *
6229 * @bp: driver handle
6230 */
6231 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6232 {
6233 int rc = bnx2x_init_hw_common(bp);
6234
6235 if (rc)
6236 return rc;
6237
6238 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6239 if (!BP_NOMCP(bp))
6240 bnx2x__common_init_phy(bp);
6241
6242 return 0;
6243 }
6244
6245 static int bnx2x_init_hw_port(struct bnx2x *bp)
6246 {
6247 int port = BP_PORT(bp);
6248 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6249 u32 low, high;
6250 u32 val;
6251
6252 bnx2x__link_reset(bp);
6253
6254 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6255
6256 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6257
6258 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6259 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6260 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6261
6262 /* Timers bug workaround: disables the pf_master bit in pglue at
6263 * common phase, we need to enable it here before any dmae access are
6264 * attempted. Therefore we manually added the enable-master to the
6265 * port phase (it also happens in the function phase)
6266 */
6267 if (!CHIP_IS_E1x(bp))
6268 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6269
6270 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6271 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6272 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6273 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6274
6275 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6276 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6277 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6278 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6279
6280 /* QM cid (connection) count */
6281 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6282
6283 #ifdef BCM_CNIC
6284 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6285 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6286 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6287 #endif
6288
6289 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6290
6291 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6292 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6293
6294 if (IS_MF(bp))
6295 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6296 else if (bp->dev->mtu > 4096) {
6297 if (bp->flags & ONE_PORT_FLAG)
6298 low = 160;
6299 else {
6300 val = bp->dev->mtu;
6301 /* (24*1024 + val*4)/256 */
6302 low = 96 + (val/64) +
6303 ((val % 64) ? 1 : 0);
6304 }
6305 } else
6306 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6307 high = low + 56; /* 14*1024/256 */
6308 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6309 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6310 }
6311
6312 if (CHIP_MODE_IS_4_PORT(bp))
6313 REG_WR(bp, (BP_PORT(bp) ?
6314 BRB1_REG_MAC_GUARANTIED_1 :
6315 BRB1_REG_MAC_GUARANTIED_0), 40);
6316
6317
6318 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6319 if (CHIP_IS_E3B0(bp))
6320 /* Ovlan exists only if we are in multi-function +
6321 * switch-dependent mode, in switch-independent there
6322 * is no ovlan headers
6323 */
6324 REG_WR(bp, BP_PORT(bp) ?
6325 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6326 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6327 (bp->path_has_ovlan ? 7 : 6));
6328
6329 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6330 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6331 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6332 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6333
6334 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6335 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6336 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6337 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6338
6339 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6340 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6341
6342 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6343
6344 if (CHIP_IS_E1x(bp)) {
6345 /* configure PBF to work without PAUSE mtu 9000 */
6346 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6347
6348 /* update threshold */
6349 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6350 /* update init credit */
6351 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6352
6353 /* probe changes */
6354 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6355 udelay(50);
6356 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6357 }
6358
6359 #ifdef BCM_CNIC
6360 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6361 #endif
6362 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6363 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6364
6365 if (CHIP_IS_E1(bp)) {
6366 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6367 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6368 }
6369 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6370
6371 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6372
6373 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6374 /* init aeu_mask_attn_func_0/1:
6375 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6376 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6377 * bits 4-7 are used for "per vn group attention" */
6378 val = IS_MF(bp) ? 0xF7 : 0x7;
6379 /* Enable DCBX attention for all but E1 */
6380 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6381 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6382
6383 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6384
6385 if (!CHIP_IS_E1x(bp)) {
6386 /* Bit-map indicating which L2 hdrs may appear after the
6387 * basic Ethernet header
6388 */
6389 REG_WR(bp, BP_PORT(bp) ?
6390 NIG_REG_P1_HDRS_AFTER_BASIC :
6391 NIG_REG_P0_HDRS_AFTER_BASIC,
6392 IS_MF_SD(bp) ? 7 : 6);
6393
6394 if (CHIP_IS_E3(bp))
6395 REG_WR(bp, BP_PORT(bp) ?
6396 NIG_REG_LLH1_MF_MODE :
6397 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6398 }
6399 if (!CHIP_IS_E3(bp))
6400 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6401
6402 if (!CHIP_IS_E1(bp)) {
6403 /* 0x2 disable mf_ov, 0x1 enable */
6404 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6405 (IS_MF_SD(bp) ? 0x1 : 0x2));
6406
6407 if (!CHIP_IS_E1x(bp)) {
6408 val = 0;
6409 switch (bp->mf_mode) {
6410 case MULTI_FUNCTION_SD:
6411 val = 1;
6412 break;
6413 case MULTI_FUNCTION_SI:
6414 val = 2;
6415 break;
6416 }
6417
6418 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6419 NIG_REG_LLH0_CLS_TYPE), val);
6420 }
6421 {
6422 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6423 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6424 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6425 }
6426 }
6427
6428
6429 /* If SPIO5 is set to generate interrupts, enable it for this port */
6430 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6431 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6432 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6433 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6434 val = REG_RD(bp, reg_addr);
6435 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6436 REG_WR(bp, reg_addr, val);
6437 }
6438
6439 return 0;
6440 }
6441
6442 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6443 {
6444 int reg;
6445
6446 if (CHIP_IS_E1(bp))
6447 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6448 else
6449 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6450
6451 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6452 }
6453
6454 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6455 {
6456 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6457 }
6458
6459 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6460 {
6461 u32 i, base = FUNC_ILT_BASE(func);
6462 for (i = base; i < base + ILT_PER_FUNC; i++)
6463 bnx2x_ilt_wr(bp, i, 0);
6464 }
6465
6466 static int bnx2x_init_hw_func(struct bnx2x *bp)
6467 {
6468 int port = BP_PORT(bp);
6469 int func = BP_FUNC(bp);
6470 int init_phase = PHASE_PF0 + func;
6471 struct bnx2x_ilt *ilt = BP_ILT(bp);
6472 u16 cdu_ilt_start;
6473 u32 addr, val;
6474 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6475 int i, main_mem_width;
6476
6477 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6478
6479 /* FLR cleanup - hmmm */
6480 if (!CHIP_IS_E1x(bp))
6481 bnx2x_pf_flr_clnup(bp);
6482
6483 /* set MSI reconfigure capability */
6484 if (bp->common.int_block == INT_BLOCK_HC) {
6485 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6486 val = REG_RD(bp, addr);
6487 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6488 REG_WR(bp, addr, val);
6489 }
6490
6491 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6492 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6493
6494 ilt = BP_ILT(bp);
6495 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6496
6497 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6498 ilt->lines[cdu_ilt_start + i].page =
6499 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6500 ilt->lines[cdu_ilt_start + i].page_mapping =
6501 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6502 /* cdu ilt pages are allocated manually so there's no need to
6503 set the size */
6504 }
6505 bnx2x_ilt_init_op(bp, INITOP_SET);
6506
6507 #ifdef BCM_CNIC
6508 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6509
6510 /* T1 hash bits value determines the T1 number of entries */
6511 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6512 #endif
6513
6514 #ifndef BCM_CNIC
6515 /* set NIC mode */
6516 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6517 #endif /* BCM_CNIC */
6518
6519 if (!CHIP_IS_E1x(bp)) {
6520 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6521
6522 /* Turn on a single ISR mode in IGU if driver is going to use
6523 * INT#x or MSI
6524 */
6525 if (!(bp->flags & USING_MSIX_FLAG))
6526 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6527 /*
6528 * Timers workaround bug: function init part.
6529 * Need to wait 20msec after initializing ILT,
6530 * needed to make sure there are no requests in
6531 * one of the PXP internal queues with "old" ILT addresses
6532 */
6533 msleep(20);
6534 /*
6535 * Master enable - Due to WB DMAE writes performed before this
6536 * register is re-initialized as part of the regular function
6537 * init
6538 */
6539 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6540 /* Enable the function in IGU */
6541 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6542 }
6543
6544 bp->dmae_ready = 1;
6545
6546 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6547
6548 if (!CHIP_IS_E1x(bp))
6549 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6550
6551 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6552 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6553 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6554 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6555 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6556 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6557 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6558 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6559 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6560 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6561 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6562 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6563 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6564
6565 if (!CHIP_IS_E1x(bp))
6566 REG_WR(bp, QM_REG_PF_EN, 1);
6567
6568 if (!CHIP_IS_E1x(bp)) {
6569 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6570 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6571 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6572 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6573 }
6574 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6575
6576 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6577 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6578 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6579 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6580 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6581 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6582 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6583 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6584 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6585 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6586 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6587 if (!CHIP_IS_E1x(bp))
6588 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6589
6590 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6591
6592 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6593
6594 if (!CHIP_IS_E1x(bp))
6595 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6596
6597 if (IS_MF(bp)) {
6598 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6599 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6600 }
6601
6602 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6603
6604 /* HC init per function */
6605 if (bp->common.int_block == INT_BLOCK_HC) {
6606 if (CHIP_IS_E1H(bp)) {
6607 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6608
6609 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6610 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6611 }
6612 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6613
6614 } else {
6615 int num_segs, sb_idx, prod_offset;
6616
6617 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6618
6619 if (!CHIP_IS_E1x(bp)) {
6620 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6621 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6622 }
6623
6624 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6625
6626 if (!CHIP_IS_E1x(bp)) {
6627 int dsb_idx = 0;
6628 /**
6629 * Producer memory:
6630 * E2 mode: address 0-135 match to the mapping memory;
6631 * 136 - PF0 default prod; 137 - PF1 default prod;
6632 * 138 - PF2 default prod; 139 - PF3 default prod;
6633 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6634 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6635 * 144-147 reserved.
6636 *
6637 * E1.5 mode - In backward compatible mode;
6638 * for non default SB; each even line in the memory
6639 * holds the U producer and each odd line hold
6640 * the C producer. The first 128 producers are for
6641 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6642 * producers are for the DSB for each PF.
6643 * Each PF has five segments: (the order inside each
6644 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6645 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6646 * 144-147 attn prods;
6647 */
6648 /* non-default-status-blocks */
6649 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6650 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6651 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6652 prod_offset = (bp->igu_base_sb + sb_idx) *
6653 num_segs;
6654
6655 for (i = 0; i < num_segs; i++) {
6656 addr = IGU_REG_PROD_CONS_MEMORY +
6657 (prod_offset + i) * 4;
6658 REG_WR(bp, addr, 0);
6659 }
6660 /* send consumer update with value 0 */
6661 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6662 USTORM_ID, 0, IGU_INT_NOP, 1);
6663 bnx2x_igu_clear_sb(bp,
6664 bp->igu_base_sb + sb_idx);
6665 }
6666
6667 /* default-status-blocks */
6668 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6669 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6670
6671 if (CHIP_MODE_IS_4_PORT(bp))
6672 dsb_idx = BP_FUNC(bp);
6673 else
6674 dsb_idx = BP_E1HVN(bp);
6675
6676 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6677 IGU_BC_BASE_DSB_PROD + dsb_idx :
6678 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6679
6680 for (i = 0; i < (num_segs * E1HVN_MAX);
6681 i += E1HVN_MAX) {
6682 addr = IGU_REG_PROD_CONS_MEMORY +
6683 (prod_offset + i)*4;
6684 REG_WR(bp, addr, 0);
6685 }
6686 /* send consumer update with 0 */
6687 if (CHIP_INT_MODE_IS_BC(bp)) {
6688 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6689 USTORM_ID, 0, IGU_INT_NOP, 1);
6690 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6691 CSTORM_ID, 0, IGU_INT_NOP, 1);
6692 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6693 XSTORM_ID, 0, IGU_INT_NOP, 1);
6694 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6695 TSTORM_ID, 0, IGU_INT_NOP, 1);
6696 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6697 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6698 } else {
6699 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6700 USTORM_ID, 0, IGU_INT_NOP, 1);
6701 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6702 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6703 }
6704 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6705
6706 /* !!! these should become driver const once
6707 rf-tool supports split-68 const */
6708 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6709 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6710 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6711 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6712 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6713 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6714 }
6715 }
6716
6717 /* Reset PCIE errors for debug */
6718 REG_WR(bp, 0x2114, 0xffffffff);
6719 REG_WR(bp, 0x2120, 0xffffffff);
6720
6721 if (CHIP_IS_E1x(bp)) {
6722 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6723 main_mem_base = HC_REG_MAIN_MEMORY +
6724 BP_PORT(bp) * (main_mem_size * 4);
6725 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6726 main_mem_width = 8;
6727
6728 val = REG_RD(bp, main_mem_prty_clr);
6729 if (val)
6730 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6731 "block during "
6732 "function init (0x%x)!\n", val);
6733
6734 /* Clear "false" parity errors in MSI-X table */
6735 for (i = main_mem_base;
6736 i < main_mem_base + main_mem_size * 4;
6737 i += main_mem_width) {
6738 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6739 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6740 i, main_mem_width / 4);
6741 }
6742 /* Clear HC parity attention */
6743 REG_RD(bp, main_mem_prty_clr);
6744 }
6745
6746 #ifdef BNX2X_STOP_ON_ERROR
6747 /* Enable STORMs SP logging */
6748 REG_WR8(bp, BAR_USTRORM_INTMEM +
6749 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6750 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6751 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6752 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6753 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6754 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6755 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6756 #endif
6757
6758 bnx2x_phy_probe(&bp->link_params);
6759
6760 return 0;
6761 }
6762
6763
6764 void bnx2x_free_mem(struct bnx2x *bp)
6765 {
6766 /* fastpath */
6767 bnx2x_free_fp_mem(bp);
6768 /* end of fastpath */
6769
6770 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6771 sizeof(struct host_sp_status_block));
6772
6773 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6774 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6775
6776 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6777 sizeof(struct bnx2x_slowpath));
6778
6779 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6780 bp->context.size);
6781
6782 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6783
6784 BNX2X_FREE(bp->ilt->lines);
6785
6786 #ifdef BCM_CNIC
6787 if (!CHIP_IS_E1x(bp))
6788 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6789 sizeof(struct host_hc_status_block_e2));
6790 else
6791 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6792 sizeof(struct host_hc_status_block_e1x));
6793
6794 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6795 #endif
6796
6797 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6798
6799 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6800 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6801 }
6802
6803 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6804 {
6805 int num_groups;
6806
6807 /* number of eth_queues */
6808 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6809
6810 /* Total number of FW statistics requests =
6811 * 1 for port stats + 1 for PF stats + num_eth_queues */
6812 bp->fw_stats_num = 2 + num_queue_stats;
6813
6814
6815 /* Request is built from stats_query_header and an array of
6816 * stats_query_cmd_group each of which contains
6817 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6818 * configured in the stats_query_header.
6819 */
6820 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6821 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6822
6823 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6824 num_groups * sizeof(struct stats_query_cmd_group);
6825
6826 /* Data for statistics requests + stats_conter
6827 *
6828 * stats_counter holds per-STORM counters that are incremented
6829 * when STORM has finished with the current request.
6830 */
6831 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6832 sizeof(struct per_pf_stats) +
6833 sizeof(struct per_queue_stats) * num_queue_stats +
6834 sizeof(struct stats_counter);
6835
6836 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6837 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6838
6839 /* Set shortcuts */
6840 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6841 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6842
6843 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6844 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6845
6846 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6847 bp->fw_stats_req_sz;
6848 return 0;
6849
6850 alloc_mem_err:
6851 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6852 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6853 return -ENOMEM;
6854 }
6855
6856
6857 int bnx2x_alloc_mem(struct bnx2x *bp)
6858 {
6859 #ifdef BCM_CNIC
6860 if (!CHIP_IS_E1x(bp))
6861 /* size = the status block + ramrod buffers */
6862 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6863 sizeof(struct host_hc_status_block_e2));
6864 else
6865 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6866 sizeof(struct host_hc_status_block_e1x));
6867
6868 /* allocate searcher T2 table */
6869 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6870 #endif
6871
6872
6873 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6874 sizeof(struct host_sp_status_block));
6875
6876 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6877 sizeof(struct bnx2x_slowpath));
6878
6879 /* Allocated memory for FW statistics */
6880 if (bnx2x_alloc_fw_stats_mem(bp))
6881 goto alloc_mem_err;
6882
6883 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6884
6885 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6886 bp->context.size);
6887
6888 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6889
6890 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6891 goto alloc_mem_err;
6892
6893 /* Slow path ring */
6894 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6895
6896 /* EQ */
6897 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6898 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6899
6900
6901 /* fastpath */
6902 /* need to be done at the end, since it's self adjusting to amount
6903 * of memory available for RSS queues
6904 */
6905 if (bnx2x_alloc_fp_mem(bp))
6906 goto alloc_mem_err;
6907 return 0;
6908
6909 alloc_mem_err:
6910 bnx2x_free_mem(bp);
6911 return -ENOMEM;
6912 }
6913
6914 /*
6915 * Init service functions
6916 */
6917
6918 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6919 struct bnx2x_vlan_mac_obj *obj, bool set,
6920 int mac_type, unsigned long *ramrod_flags)
6921 {
6922 int rc;
6923 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6924
6925 memset(&ramrod_param, 0, sizeof(ramrod_param));
6926
6927 /* Fill general parameters */
6928 ramrod_param.vlan_mac_obj = obj;
6929 ramrod_param.ramrod_flags = *ramrod_flags;
6930
6931 /* Fill a user request section if needed */
6932 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6933 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6934
6935 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6936
6937 /* Set the command: ADD or DEL */
6938 if (set)
6939 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6940 else
6941 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6942 }
6943
6944 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6945 if (rc < 0)
6946 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6947 return rc;
6948 }
6949
6950 int bnx2x_del_all_macs(struct bnx2x *bp,
6951 struct bnx2x_vlan_mac_obj *mac_obj,
6952 int mac_type, bool wait_for_comp)
6953 {
6954 int rc;
6955 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6956
6957 /* Wait for completion of requested */
6958 if (wait_for_comp)
6959 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6960
6961 /* Set the mac type of addresses we want to clear */
6962 __set_bit(mac_type, &vlan_mac_flags);
6963
6964 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6965 if (rc < 0)
6966 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6967
6968 return rc;
6969 }
6970
6971 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6972 {
6973 unsigned long ramrod_flags = 0;
6974
6975 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6976
6977 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6978 /* Eth MAC is set on RSS leading client (fp[0]) */
6979 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6980 BNX2X_ETH_MAC, &ramrod_flags);
6981 }
6982
6983 int bnx2x_setup_leading(struct bnx2x *bp)
6984 {
6985 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6986 }
6987
6988 /**
6989 * bnx2x_set_int_mode - configure interrupt mode
6990 *
6991 * @bp: driver handle
6992 *
6993 * In case of MSI-X it will also try to enable MSI-X.
6994 */
6995 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6996 {
6997 switch (int_mode) {
6998 case INT_MODE_MSI:
6999 bnx2x_enable_msi(bp);
7000 /* falling through... */
7001 case INT_MODE_INTx:
7002 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7003 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7004 break;
7005 default:
7006 /* Set number of queues according to bp->multi_mode value */
7007 bnx2x_set_num_queues(bp);
7008
7009 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7010 bp->num_queues);
7011
7012 /* if we can't use MSI-X we only need one fp,
7013 * so try to enable MSI-X with the requested number of fp's
7014 * and fallback to MSI or legacy INTx with one fp
7015 */
7016 if (bnx2x_enable_msix(bp)) {
7017 /* failed to enable MSI-X */
7018 if (bp->multi_mode)
7019 DP(NETIF_MSG_IFUP,
7020 "Multi requested but failed to "
7021 "enable MSI-X (%d), "
7022 "set number of queues to %d\n",
7023 bp->num_queues,
7024 1 + NON_ETH_CONTEXT_USE);
7025 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7026
7027 /* Try to enable MSI */
7028 if (!(bp->flags & DISABLE_MSI_FLAG))
7029 bnx2x_enable_msi(bp);
7030 }
7031 break;
7032 }
7033 }
7034
7035 /* must be called prioir to any HW initializations */
7036 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7037 {
7038 return L2_ILT_LINES(bp);
7039 }
7040
7041 void bnx2x_ilt_set_info(struct bnx2x *bp)
7042 {
7043 struct ilt_client_info *ilt_client;
7044 struct bnx2x_ilt *ilt = BP_ILT(bp);
7045 u16 line = 0;
7046
7047 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7048 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7049
7050 /* CDU */
7051 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7052 ilt_client->client_num = ILT_CLIENT_CDU;
7053 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7054 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7055 ilt_client->start = line;
7056 line += bnx2x_cid_ilt_lines(bp);
7057 #ifdef BCM_CNIC
7058 line += CNIC_ILT_LINES;
7059 #endif
7060 ilt_client->end = line - 1;
7061
7062 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7063 "flags 0x%x, hw psz %d\n",
7064 ilt_client->start,
7065 ilt_client->end,
7066 ilt_client->page_size,
7067 ilt_client->flags,
7068 ilog2(ilt_client->page_size >> 12));
7069
7070 /* QM */
7071 if (QM_INIT(bp->qm_cid_count)) {
7072 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7073 ilt_client->client_num = ILT_CLIENT_QM;
7074 ilt_client->page_size = QM_ILT_PAGE_SZ;
7075 ilt_client->flags = 0;
7076 ilt_client->start = line;
7077
7078 /* 4 bytes for each cid */
7079 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7080 QM_ILT_PAGE_SZ);
7081
7082 ilt_client->end = line - 1;
7083
7084 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7085 "flags 0x%x, hw psz %d\n",
7086 ilt_client->start,
7087 ilt_client->end,
7088 ilt_client->page_size,
7089 ilt_client->flags,
7090 ilog2(ilt_client->page_size >> 12));
7091
7092 }
7093 /* SRC */
7094 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7095 #ifdef BCM_CNIC
7096 ilt_client->client_num = ILT_CLIENT_SRC;
7097 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7098 ilt_client->flags = 0;
7099 ilt_client->start = line;
7100 line += SRC_ILT_LINES;
7101 ilt_client->end = line - 1;
7102
7103 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7104 "flags 0x%x, hw psz %d\n",
7105 ilt_client->start,
7106 ilt_client->end,
7107 ilt_client->page_size,
7108 ilt_client->flags,
7109 ilog2(ilt_client->page_size >> 12));
7110
7111 #else
7112 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7113 #endif
7114
7115 /* TM */
7116 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7117 #ifdef BCM_CNIC
7118 ilt_client->client_num = ILT_CLIENT_TM;
7119 ilt_client->page_size = TM_ILT_PAGE_SZ;
7120 ilt_client->flags = 0;
7121 ilt_client->start = line;
7122 line += TM_ILT_LINES;
7123 ilt_client->end = line - 1;
7124
7125 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7126 "flags 0x%x, hw psz %d\n",
7127 ilt_client->start,
7128 ilt_client->end,
7129 ilt_client->page_size,
7130 ilt_client->flags,
7131 ilog2(ilt_client->page_size >> 12));
7132
7133 #else
7134 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7135 #endif
7136 BUG_ON(line > ILT_MAX_LINES);
7137 }
7138
7139 /**
7140 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7141 *
7142 * @bp: driver handle
7143 * @fp: pointer to fastpath
7144 * @init_params: pointer to parameters structure
7145 *
7146 * parameters configured:
7147 * - HC configuration
7148 * - Queue's CDU context
7149 */
7150 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7151 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7152 {
7153
7154 u8 cos;
7155 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7156 if (!IS_FCOE_FP(fp)) {
7157 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7158 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7159
7160 /* If HC is supporterd, enable host coalescing in the transition
7161 * to INIT state.
7162 */
7163 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7164 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7165
7166 /* HC rate */
7167 init_params->rx.hc_rate = bp->rx_ticks ?
7168 (1000000 / bp->rx_ticks) : 0;
7169 init_params->tx.hc_rate = bp->tx_ticks ?
7170 (1000000 / bp->tx_ticks) : 0;
7171
7172 /* FW SB ID */
7173 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7174 fp->fw_sb_id;
7175
7176 /*
7177 * CQ index among the SB indices: FCoE clients uses the default
7178 * SB, therefore it's different.
7179 */
7180 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7181 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7182 }
7183
7184 /* set maximum number of COSs supported by this queue */
7185 init_params->max_cos = fp->max_cos;
7186
7187 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7188 fp->index, init_params->max_cos);
7189
7190 /* set the context pointers queue object */
7191 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7192 init_params->cxts[cos] =
7193 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7194 }
7195
7196 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7197 struct bnx2x_queue_state_params *q_params,
7198 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7199 int tx_index, bool leading)
7200 {
7201 memset(tx_only_params, 0, sizeof(*tx_only_params));
7202
7203 /* Set the command */
7204 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7205
7206 /* Set tx-only QUEUE flags: don't zero statistics */
7207 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7208
7209 /* choose the index of the cid to send the slow path on */
7210 tx_only_params->cid_index = tx_index;
7211
7212 /* Set general TX_ONLY_SETUP parameters */
7213 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7214
7215 /* Set Tx TX_ONLY_SETUP parameters */
7216 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7217
7218 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7219 "cos %d, primary cid %d, cid %d, "
7220 "client id %d, sp-client id %d, flags %lx",
7221 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7222 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7223 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7224
7225 /* send the ramrod */
7226 return bnx2x_queue_state_change(bp, q_params);
7227 }
7228
7229
7230 /**
7231 * bnx2x_setup_queue - setup queue
7232 *
7233 * @bp: driver handle
7234 * @fp: pointer to fastpath
7235 * @leading: is leading
7236 *
7237 * This function performs 2 steps in a Queue state machine
7238 * actually: 1) RESET->INIT 2) INIT->SETUP
7239 */
7240
7241 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7242 bool leading)
7243 {
7244 struct bnx2x_queue_state_params q_params = {0};
7245 struct bnx2x_queue_setup_params *setup_params =
7246 &q_params.params.setup;
7247 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7248 &q_params.params.tx_only;
7249 int rc;
7250 u8 tx_index;
7251
7252 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
7253
7254 /* reset IGU state skip FCoE L2 queue */
7255 if (!IS_FCOE_FP(fp))
7256 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7257 IGU_INT_ENABLE, 0);
7258
7259 q_params.q_obj = &fp->q_obj;
7260 /* We want to wait for completion in this context */
7261 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7262
7263 /* Prepare the INIT parameters */
7264 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7265
7266 /* Set the command */
7267 q_params.cmd = BNX2X_Q_CMD_INIT;
7268
7269 /* Change the state to INIT */
7270 rc = bnx2x_queue_state_change(bp, &q_params);
7271 if (rc) {
7272 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7273 return rc;
7274 }
7275
7276 DP(BNX2X_MSG_SP, "init complete");
7277
7278
7279 /* Now move the Queue to the SETUP state... */
7280 memset(setup_params, 0, sizeof(*setup_params));
7281
7282 /* Set QUEUE flags */
7283 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7284
7285 /* Set general SETUP parameters */
7286 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7287 FIRST_TX_COS_INDEX);
7288
7289 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7290 &setup_params->rxq_params);
7291
7292 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7293 FIRST_TX_COS_INDEX);
7294
7295 /* Set the command */
7296 q_params.cmd = BNX2X_Q_CMD_SETUP;
7297
7298 /* Change the state to SETUP */
7299 rc = bnx2x_queue_state_change(bp, &q_params);
7300 if (rc) {
7301 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7302 return rc;
7303 }
7304
7305 /* loop through the relevant tx-only indices */
7306 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7307 tx_index < fp->max_cos;
7308 tx_index++) {
7309
7310 /* prepare and send tx-only ramrod*/
7311 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7312 tx_only_params, tx_index, leading);
7313 if (rc) {
7314 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7315 fp->index, tx_index);
7316 return rc;
7317 }
7318 }
7319
7320 return rc;
7321 }
7322
7323 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7324 {
7325 struct bnx2x_fastpath *fp = &bp->fp[index];
7326 struct bnx2x_fp_txdata *txdata;
7327 struct bnx2x_queue_state_params q_params = {0};
7328 int rc, tx_index;
7329
7330 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
7331
7332 q_params.q_obj = &fp->q_obj;
7333 /* We want to wait for completion in this context */
7334 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7335
7336
7337 /* close tx-only connections */
7338 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7339 tx_index < fp->max_cos;
7340 tx_index++){
7341
7342 /* ascertain this is a normal queue*/
7343 txdata = &fp->txdata[tx_index];
7344
7345 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7346 txdata->txq_index);
7347
7348 /* send halt terminate on tx-only connection */
7349 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7350 memset(&q_params.params.terminate, 0,
7351 sizeof(q_params.params.terminate));
7352 q_params.params.terminate.cid_index = tx_index;
7353
7354 rc = bnx2x_queue_state_change(bp, &q_params);
7355 if (rc)
7356 return rc;
7357
7358 /* send halt terminate on tx-only connection */
7359 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7360 memset(&q_params.params.cfc_del, 0,
7361 sizeof(q_params.params.cfc_del));
7362 q_params.params.cfc_del.cid_index = tx_index;
7363 rc = bnx2x_queue_state_change(bp, &q_params);
7364 if (rc)
7365 return rc;
7366 }
7367 /* Stop the primary connection: */
7368 /* ...halt the connection */
7369 q_params.cmd = BNX2X_Q_CMD_HALT;
7370 rc = bnx2x_queue_state_change(bp, &q_params);
7371 if (rc)
7372 return rc;
7373
7374 /* ...terminate the connection */
7375 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7376 memset(&q_params.params.terminate, 0,
7377 sizeof(q_params.params.terminate));
7378 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7379 rc = bnx2x_queue_state_change(bp, &q_params);
7380 if (rc)
7381 return rc;
7382 /* ...delete cfc entry */
7383 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7384 memset(&q_params.params.cfc_del, 0,
7385 sizeof(q_params.params.cfc_del));
7386 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7387 return bnx2x_queue_state_change(bp, &q_params);
7388 }
7389
7390
7391 static void bnx2x_reset_func(struct bnx2x *bp)
7392 {
7393 int port = BP_PORT(bp);
7394 int func = BP_FUNC(bp);
7395 int i;
7396
7397 /* Disable the function in the FW */
7398 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7399 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7400 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7401 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7402
7403 /* FP SBs */
7404 for_each_eth_queue(bp, i) {
7405 struct bnx2x_fastpath *fp = &bp->fp[i];
7406 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7407 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7408 SB_DISABLED);
7409 }
7410
7411 #ifdef BCM_CNIC
7412 /* CNIC SB */
7413 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7414 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7415 SB_DISABLED);
7416 #endif
7417 /* SP SB */
7418 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7419 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7420 SB_DISABLED);
7421
7422 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7423 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7424 0);
7425
7426 /* Configure IGU */
7427 if (bp->common.int_block == INT_BLOCK_HC) {
7428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7430 } else {
7431 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7432 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7433 }
7434
7435 #ifdef BCM_CNIC
7436 /* Disable Timer scan */
7437 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7438 /*
7439 * Wait for at least 10ms and up to 2 second for the timers scan to
7440 * complete
7441 */
7442 for (i = 0; i < 200; i++) {
7443 msleep(10);
7444 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7445 break;
7446 }
7447 #endif
7448 /* Clear ILT */
7449 bnx2x_clear_func_ilt(bp, func);
7450
7451 /* Timers workaround bug for E2: if this is vnic-3,
7452 * we need to set the entire ilt range for this timers.
7453 */
7454 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7455 struct ilt_client_info ilt_cli;
7456 /* use dummy TM client */
7457 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7458 ilt_cli.start = 0;
7459 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7460 ilt_cli.client_num = ILT_CLIENT_TM;
7461
7462 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7463 }
7464
7465 /* this assumes that reset_port() called before reset_func()*/
7466 if (!CHIP_IS_E1x(bp))
7467 bnx2x_pf_disable(bp);
7468
7469 bp->dmae_ready = 0;
7470 }
7471
7472 static void bnx2x_reset_port(struct bnx2x *bp)
7473 {
7474 int port = BP_PORT(bp);
7475 u32 val;
7476
7477 /* Reset physical Link */
7478 bnx2x__link_reset(bp);
7479
7480 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7481
7482 /* Do not rcv packets to BRB */
7483 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7484 /* Do not direct rcv packets that are not for MCP to the BRB */
7485 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7486 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7487
7488 /* Configure AEU */
7489 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7490
7491 msleep(100);
7492 /* Check for BRB port occupancy */
7493 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7494 if (val)
7495 DP(NETIF_MSG_IFDOWN,
7496 "BRB1 is not empty %d blocks are occupied\n", val);
7497
7498 /* TODO: Close Doorbell port? */
7499 }
7500
7501 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7502 {
7503 struct bnx2x_func_state_params func_params = {0};
7504
7505 /* Prepare parameters for function state transitions */
7506 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7507
7508 func_params.f_obj = &bp->func_obj;
7509 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7510
7511 func_params.params.hw_init.load_phase = load_code;
7512
7513 return bnx2x_func_state_change(bp, &func_params);
7514 }
7515
7516 static inline int bnx2x_func_stop(struct bnx2x *bp)
7517 {
7518 struct bnx2x_func_state_params func_params = {0};
7519 int rc;
7520
7521 /* Prepare parameters for function state transitions */
7522 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7523 func_params.f_obj = &bp->func_obj;
7524 func_params.cmd = BNX2X_F_CMD_STOP;
7525
7526 /*
7527 * Try to stop the function the 'good way'. If fails (in case
7528 * of a parity error during bnx2x_chip_cleanup()) and we are
7529 * not in a debug mode, perform a state transaction in order to
7530 * enable further HW_RESET transaction.
7531 */
7532 rc = bnx2x_func_state_change(bp, &func_params);
7533 if (rc) {
7534 #ifdef BNX2X_STOP_ON_ERROR
7535 return rc;
7536 #else
7537 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7538 "transaction\n");
7539 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7540 return bnx2x_func_state_change(bp, &func_params);
7541 #endif
7542 }
7543
7544 return 0;
7545 }
7546
7547 /**
7548 * bnx2x_send_unload_req - request unload mode from the MCP.
7549 *
7550 * @bp: driver handle
7551 * @unload_mode: requested function's unload mode
7552 *
7553 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7554 */
7555 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7556 {
7557 u32 reset_code = 0;
7558 int port = BP_PORT(bp);
7559
7560 /* Select the UNLOAD request mode */
7561 if (unload_mode == UNLOAD_NORMAL)
7562 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7563
7564 else if (bp->flags & NO_WOL_FLAG)
7565 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7566
7567 else if (bp->wol) {
7568 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7569 u8 *mac_addr = bp->dev->dev_addr;
7570 u32 val;
7571 /* The mac address is written to entries 1-4 to
7572 preserve entry 0 which is used by the PMF */
7573 u8 entry = (BP_E1HVN(bp) + 1)*8;
7574
7575 val = (mac_addr[0] << 8) | mac_addr[1];
7576 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7577
7578 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7579 (mac_addr[4] << 8) | mac_addr[5];
7580 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7581
7582 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7583
7584 } else
7585 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7586
7587 /* Send the request to the MCP */
7588 if (!BP_NOMCP(bp))
7589 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7590 else {
7591 int path = BP_PATH(bp);
7592
7593 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7594 "%d, %d, %d\n",
7595 path, load_count[path][0], load_count[path][1],
7596 load_count[path][2]);
7597 load_count[path][0]--;
7598 load_count[path][1 + port]--;
7599 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7600 "%d, %d, %d\n",
7601 path, load_count[path][0], load_count[path][1],
7602 load_count[path][2]);
7603 if (load_count[path][0] == 0)
7604 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7605 else if (load_count[path][1 + port] == 0)
7606 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7607 else
7608 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7609 }
7610
7611 return reset_code;
7612 }
7613
7614 /**
7615 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7616 *
7617 * @bp: driver handle
7618 */
7619 void bnx2x_send_unload_done(struct bnx2x *bp)
7620 {
7621 /* Report UNLOAD_DONE to MCP */
7622 if (!BP_NOMCP(bp))
7623 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7624 }
7625
7626 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7627 {
7628 int tout = 50;
7629 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7630
7631 if (!bp->port.pmf)
7632 return 0;
7633
7634 /*
7635 * (assumption: No Attention from MCP at this stage)
7636 * PMF probably in the middle of TXdisable/enable transaction
7637 * 1. Sync IRS for default SB
7638 * 2. Sync SP queue - this guarantes us that attention handling started
7639 * 3. Wait, that TXdisable/enable transaction completes
7640 *
7641 * 1+2 guranty that if DCBx attention was scheduled it already changed
7642 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7643 * received complettion for the transaction the state is TX_STOPPED.
7644 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7645 * transaction.
7646 */
7647
7648 /* make sure default SB ISR is done */
7649 if (msix)
7650 synchronize_irq(bp->msix_table[0].vector);
7651 else
7652 synchronize_irq(bp->pdev->irq);
7653
7654 flush_workqueue(bnx2x_wq);
7655
7656 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7657 BNX2X_F_STATE_STARTED && tout--)
7658 msleep(20);
7659
7660 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7661 BNX2X_F_STATE_STARTED) {
7662 #ifdef BNX2X_STOP_ON_ERROR
7663 return -EBUSY;
7664 #else
7665 /*
7666 * Failed to complete the transaction in a "good way"
7667 * Force both transactions with CLR bit
7668 */
7669 struct bnx2x_func_state_params func_params = {0};
7670
7671 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7672 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7673
7674 func_params.f_obj = &bp->func_obj;
7675 __set_bit(RAMROD_DRV_CLR_ONLY,
7676 &func_params.ramrod_flags);
7677
7678 /* STARTED-->TX_ST0PPED */
7679 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7680 bnx2x_func_state_change(bp, &func_params);
7681
7682 /* TX_ST0PPED-->STARTED */
7683 func_params.cmd = BNX2X_F_CMD_TX_START;
7684 return bnx2x_func_state_change(bp, &func_params);
7685 #endif
7686 }
7687
7688 return 0;
7689 }
7690
7691 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7692 {
7693 int port = BP_PORT(bp);
7694 int i, rc = 0;
7695 u8 cos;
7696 struct bnx2x_mcast_ramrod_params rparam = {0};
7697 u32 reset_code;
7698
7699 /* Wait until tx fastpath tasks complete */
7700 for_each_tx_queue(bp, i) {
7701 struct bnx2x_fastpath *fp = &bp->fp[i];
7702
7703 for_each_cos_in_tx_queue(fp, cos)
7704 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7705 #ifdef BNX2X_STOP_ON_ERROR
7706 if (rc)
7707 return;
7708 #endif
7709 }
7710
7711 /* Give HW time to discard old tx messages */
7712 usleep_range(1000, 1000);
7713
7714 /* Clean all ETH MACs */
7715 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7716 if (rc < 0)
7717 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7718
7719 /* Clean up UC list */
7720 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7721 true);
7722 if (rc < 0)
7723 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7724 "%d\n", rc);
7725
7726 /* Disable LLH */
7727 if (!CHIP_IS_E1(bp))
7728 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7729
7730 /* Set "drop all" (stop Rx).
7731 * We need to take a netif_addr_lock() here in order to prevent
7732 * a race between the completion code and this code.
7733 */
7734 netif_addr_lock_bh(bp->dev);
7735 /* Schedule the rx_mode command */
7736 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7737 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7738 else
7739 bnx2x_set_storm_rx_mode(bp);
7740
7741 /* Cleanup multicast configuration */
7742 rparam.mcast_obj = &bp->mcast_obj;
7743 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7744 if (rc < 0)
7745 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7746
7747 netif_addr_unlock_bh(bp->dev);
7748
7749
7750
7751 /*
7752 * Send the UNLOAD_REQUEST to the MCP. This will return if
7753 * this function should perform FUNC, PORT or COMMON HW
7754 * reset.
7755 */
7756 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7757
7758 /*
7759 * (assumption: No Attention from MCP at this stage)
7760 * PMF probably in the middle of TXdisable/enable transaction
7761 */
7762 rc = bnx2x_func_wait_started(bp);
7763 if (rc) {
7764 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7765 #ifdef BNX2X_STOP_ON_ERROR
7766 return;
7767 #endif
7768 }
7769
7770 /* Close multi and leading connections
7771 * Completions for ramrods are collected in a synchronous way
7772 */
7773 for_each_queue(bp, i)
7774 if (bnx2x_stop_queue(bp, i))
7775 #ifdef BNX2X_STOP_ON_ERROR
7776 return;
7777 #else
7778 goto unload_error;
7779 #endif
7780 /* If SP settings didn't get completed so far - something
7781 * very wrong has happen.
7782 */
7783 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7784 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7785
7786 #ifndef BNX2X_STOP_ON_ERROR
7787 unload_error:
7788 #endif
7789 rc = bnx2x_func_stop(bp);
7790 if (rc) {
7791 BNX2X_ERR("Function stop failed!\n");
7792 #ifdef BNX2X_STOP_ON_ERROR
7793 return;
7794 #endif
7795 }
7796
7797 /* Disable HW interrupts, NAPI */
7798 bnx2x_netif_stop(bp, 1);
7799
7800 /* Release IRQs */
7801 bnx2x_free_irq(bp);
7802
7803 /* Reset the chip */
7804 rc = bnx2x_reset_hw(bp, reset_code);
7805 if (rc)
7806 BNX2X_ERR("HW_RESET failed\n");
7807
7808
7809 /* Report UNLOAD_DONE to MCP */
7810 bnx2x_send_unload_done(bp);
7811 }
7812
7813 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7814 {
7815 u32 val;
7816
7817 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7818
7819 if (CHIP_IS_E1(bp)) {
7820 int port = BP_PORT(bp);
7821 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7822 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7823
7824 val = REG_RD(bp, addr);
7825 val &= ~(0x300);
7826 REG_WR(bp, addr, val);
7827 } else {
7828 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7829 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7830 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7831 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7832 }
7833 }
7834
7835 /* Close gates #2, #3 and #4: */
7836 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7837 {
7838 u32 val;
7839
7840 /* Gates #2 and #4a are closed/opened for "not E1" only */
7841 if (!CHIP_IS_E1(bp)) {
7842 /* #4 */
7843 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7844 /* #2 */
7845 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7846 }
7847
7848 /* #3 */
7849 if (CHIP_IS_E1x(bp)) {
7850 /* Prevent interrupts from HC on both ports */
7851 val = REG_RD(bp, HC_REG_CONFIG_1);
7852 REG_WR(bp, HC_REG_CONFIG_1,
7853 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7854 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7855
7856 val = REG_RD(bp, HC_REG_CONFIG_0);
7857 REG_WR(bp, HC_REG_CONFIG_0,
7858 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7859 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7860 } else {
7861 /* Prevent incomming interrupts in IGU */
7862 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7863
7864 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7865 (!close) ?
7866 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7867 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7868 }
7869
7870 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7871 close ? "closing" : "opening");
7872 mmiowb();
7873 }
7874
7875 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7876
7877 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7878 {
7879 /* Do some magic... */
7880 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7881 *magic_val = val & SHARED_MF_CLP_MAGIC;
7882 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7883 }
7884
7885 /**
7886 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7887 *
7888 * @bp: driver handle
7889 * @magic_val: old value of the `magic' bit.
7890 */
7891 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7892 {
7893 /* Restore the `magic' bit value... */
7894 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7895 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7896 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7897 }
7898
7899 /**
7900 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7901 *
7902 * @bp: driver handle
7903 * @magic_val: old value of 'magic' bit.
7904 *
7905 * Takes care of CLP configurations.
7906 */
7907 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7908 {
7909 u32 shmem;
7910 u32 validity_offset;
7911
7912 DP(NETIF_MSG_HW, "Starting\n");
7913
7914 /* Set `magic' bit in order to save MF config */
7915 if (!CHIP_IS_E1(bp))
7916 bnx2x_clp_reset_prep(bp, magic_val);
7917
7918 /* Get shmem offset */
7919 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7920 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7921
7922 /* Clear validity map flags */
7923 if (shmem > 0)
7924 REG_WR(bp, shmem + validity_offset, 0);
7925 }
7926
7927 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7928 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7929
7930 /**
7931 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7932 *
7933 * @bp: driver handle
7934 */
7935 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7936 {
7937 /* special handling for emulation and FPGA,
7938 wait 10 times longer */
7939 if (CHIP_REV_IS_SLOW(bp))
7940 msleep(MCP_ONE_TIMEOUT*10);
7941 else
7942 msleep(MCP_ONE_TIMEOUT);
7943 }
7944
7945 /*
7946 * initializes bp->common.shmem_base and waits for validity signature to appear
7947 */
7948 static int bnx2x_init_shmem(struct bnx2x *bp)
7949 {
7950 int cnt = 0;
7951 u32 val = 0;
7952
7953 do {
7954 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7955 if (bp->common.shmem_base) {
7956 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7957 if (val & SHR_MEM_VALIDITY_MB)
7958 return 0;
7959 }
7960
7961 bnx2x_mcp_wait_one(bp);
7962
7963 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7964
7965 BNX2X_ERR("BAD MCP validity signature\n");
7966
7967 return -ENODEV;
7968 }
7969
7970 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7971 {
7972 int rc = bnx2x_init_shmem(bp);
7973
7974 /* Restore the `magic' bit value */
7975 if (!CHIP_IS_E1(bp))
7976 bnx2x_clp_reset_done(bp, magic_val);
7977
7978 return rc;
7979 }
7980
7981 static void bnx2x_pxp_prep(struct bnx2x *bp)
7982 {
7983 if (!CHIP_IS_E1(bp)) {
7984 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7985 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7986 mmiowb();
7987 }
7988 }
7989
7990 /*
7991 * Reset the whole chip except for:
7992 * - PCIE core
7993 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7994 * one reset bit)
7995 * - IGU
7996 * - MISC (including AEU)
7997 * - GRC
7998 * - RBCN, RBCP
7999 */
8000 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8001 {
8002 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8003 u32 global_bits2, stay_reset2;
8004
8005 /*
8006 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8007 * (per chip) blocks.
8008 */
8009 global_bits2 =
8010 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8011 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8012
8013 /* Don't reset the following blocks */
8014 not_reset_mask1 =
8015 MISC_REGISTERS_RESET_REG_1_RST_HC |
8016 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8017 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8018
8019 not_reset_mask2 =
8020 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8021 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8022 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8023 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8024 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8025 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8026 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8027 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8028 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8029 MISC_REGISTERS_RESET_REG_2_PGLC;
8030
8031 /*
8032 * Keep the following blocks in reset:
8033 * - all xxMACs are handled by the bnx2x_link code.
8034 */
8035 stay_reset2 =
8036 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8037 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8038 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8039 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8040 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8041 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8042 MISC_REGISTERS_RESET_REG_2_XMAC |
8043 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8044
8045 /* Full reset masks according to the chip */
8046 reset_mask1 = 0xffffffff;
8047
8048 if (CHIP_IS_E1(bp))
8049 reset_mask2 = 0xffff;
8050 else if (CHIP_IS_E1H(bp))
8051 reset_mask2 = 0x1ffff;
8052 else if (CHIP_IS_E2(bp))
8053 reset_mask2 = 0xfffff;
8054 else /* CHIP_IS_E3 */
8055 reset_mask2 = 0x3ffffff;
8056
8057 /* Don't reset global blocks unless we need to */
8058 if (!global)
8059 reset_mask2 &= ~global_bits2;
8060
8061 /*
8062 * In case of attention in the QM, we need to reset PXP
8063 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8064 * because otherwise QM reset would release 'close the gates' shortly
8065 * before resetting the PXP, then the PSWRQ would send a write
8066 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8067 * read the payload data from PSWWR, but PSWWR would not
8068 * respond. The write queue in PGLUE would stuck, dmae commands
8069 * would not return. Therefore it's important to reset the second
8070 * reset register (containing the
8071 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8072 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8073 * bit).
8074 */
8075 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8076 reset_mask2 & (~not_reset_mask2));
8077
8078 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8079 reset_mask1 & (~not_reset_mask1));
8080
8081 barrier();
8082 mmiowb();
8083
8084 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8085 reset_mask2 & (~stay_reset2));
8086
8087 barrier();
8088 mmiowb();
8089
8090 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8091 mmiowb();
8092 }
8093
8094 /**
8095 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8096 * It should get cleared in no more than 1s.
8097 *
8098 * @bp: driver handle
8099 *
8100 * It should get cleared in no more than 1s. Returns 0 if
8101 * pending writes bit gets cleared.
8102 */
8103 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8104 {
8105 u32 cnt = 1000;
8106 u32 pend_bits = 0;
8107
8108 do {
8109 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8110
8111 if (pend_bits == 0)
8112 break;
8113
8114 usleep_range(1000, 1000);
8115 } while (cnt-- > 0);
8116
8117 if (cnt <= 0) {
8118 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8119 pend_bits);
8120 return -EBUSY;
8121 }
8122
8123 return 0;
8124 }
8125
8126 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8127 {
8128 int cnt = 1000;
8129 u32 val = 0;
8130 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8131
8132
8133 /* Empty the Tetris buffer, wait for 1s */
8134 do {
8135 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8136 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8137 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8138 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8139 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8140 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8141 ((port_is_idle_0 & 0x1) == 0x1) &&
8142 ((port_is_idle_1 & 0x1) == 0x1) &&
8143 (pgl_exp_rom2 == 0xffffffff))
8144 break;
8145 usleep_range(1000, 1000);
8146 } while (cnt-- > 0);
8147
8148 if (cnt <= 0) {
8149 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8150 " are still"
8151 " outstanding read requests after 1s!\n");
8152 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8153 " port_is_idle_0=0x%08x,"
8154 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8155 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8156 pgl_exp_rom2);
8157 return -EAGAIN;
8158 }
8159
8160 barrier();
8161
8162 /* Close gates #2, #3 and #4 */
8163 bnx2x_set_234_gates(bp, true);
8164
8165 /* Poll for IGU VQs for 57712 and newer chips */
8166 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8167 return -EAGAIN;
8168
8169
8170 /* TBD: Indicate that "process kill" is in progress to MCP */
8171
8172 /* Clear "unprepared" bit */
8173 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8174 barrier();
8175
8176 /* Make sure all is written to the chip before the reset */
8177 mmiowb();
8178
8179 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8180 * PSWHST, GRC and PSWRD Tetris buffer.
8181 */
8182 usleep_range(1000, 1000);
8183
8184 /* Prepare to chip reset: */
8185 /* MCP */
8186 if (global)
8187 bnx2x_reset_mcp_prep(bp, &val);
8188
8189 /* PXP */
8190 bnx2x_pxp_prep(bp);
8191 barrier();
8192
8193 /* reset the chip */
8194 bnx2x_process_kill_chip_reset(bp, global);
8195 barrier();
8196
8197 /* Recover after reset: */
8198 /* MCP */
8199 if (global && bnx2x_reset_mcp_comp(bp, val))
8200 return -EAGAIN;
8201
8202 /* TBD: Add resetting the NO_MCP mode DB here */
8203
8204 /* PXP */
8205 bnx2x_pxp_prep(bp);
8206
8207 /* Open the gates #2, #3 and #4 */
8208 bnx2x_set_234_gates(bp, false);
8209
8210 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8211 * reset state, re-enable attentions. */
8212
8213 return 0;
8214 }
8215
8216 int bnx2x_leader_reset(struct bnx2x *bp)
8217 {
8218 int rc = 0;
8219 bool global = bnx2x_reset_is_global(bp);
8220
8221 /* Try to recover after the failure */
8222 if (bnx2x_process_kill(bp, global)) {
8223 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8224 "Aii!\n", BP_PATH(bp));
8225 rc = -EAGAIN;
8226 goto exit_leader_reset;
8227 }
8228
8229 /*
8230 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8231 * state.
8232 */
8233 bnx2x_set_reset_done(bp);
8234 if (global)
8235 bnx2x_clear_reset_global(bp);
8236
8237 exit_leader_reset:
8238 bp->is_leader = 0;
8239 bnx2x_release_leader_lock(bp);
8240 smp_mb();
8241 return rc;
8242 }
8243
8244 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8245 {
8246 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8247
8248 /* Disconnect this device */
8249 netif_device_detach(bp->dev);
8250
8251 /*
8252 * Block ifup for all function on this engine until "process kill"
8253 * or power cycle.
8254 */
8255 bnx2x_set_reset_in_progress(bp);
8256
8257 /* Shut down the power */
8258 bnx2x_set_power_state(bp, PCI_D3hot);
8259
8260 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8261
8262 smp_mb();
8263 }
8264
8265 /*
8266 * Assumption: runs under rtnl lock. This together with the fact
8267 * that it's called only from bnx2x_sp_rtnl() ensure that it
8268 * will never be called when netif_running(bp->dev) is false.
8269 */
8270 static void bnx2x_parity_recover(struct bnx2x *bp)
8271 {
8272 bool global = false;
8273
8274 DP(NETIF_MSG_HW, "Handling parity\n");
8275 while (1) {
8276 switch (bp->recovery_state) {
8277 case BNX2X_RECOVERY_INIT:
8278 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8279 bnx2x_chk_parity_attn(bp, &global, false);
8280
8281 /* Try to get a LEADER_LOCK HW lock */
8282 if (bnx2x_trylock_leader_lock(bp)) {
8283 bnx2x_set_reset_in_progress(bp);
8284 /*
8285 * Check if there is a global attention and if
8286 * there was a global attention, set the global
8287 * reset bit.
8288 */
8289
8290 if (global)
8291 bnx2x_set_reset_global(bp);
8292
8293 bp->is_leader = 1;
8294 }
8295
8296 /* Stop the driver */
8297 /* If interface has been removed - break */
8298 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8299 return;
8300
8301 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8302
8303 /*
8304 * Reset MCP command sequence number and MCP mail box
8305 * sequence as we are going to reset the MCP.
8306 */
8307 if (global) {
8308 bp->fw_seq = 0;
8309 bp->fw_drv_pulse_wr_seq = 0;
8310 }
8311
8312 /* Ensure "is_leader", MCP command sequence and
8313 * "recovery_state" update values are seen on other
8314 * CPUs.
8315 */
8316 smp_mb();
8317 break;
8318
8319 case BNX2X_RECOVERY_WAIT:
8320 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8321 if (bp->is_leader) {
8322 int other_engine = BP_PATH(bp) ? 0 : 1;
8323 u32 other_load_counter =
8324 bnx2x_get_load_cnt(bp, other_engine);
8325 u32 load_counter =
8326 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8327 global = bnx2x_reset_is_global(bp);
8328
8329 /*
8330 * In case of a parity in a global block, let
8331 * the first leader that performs a
8332 * leader_reset() reset the global blocks in
8333 * order to clear global attentions. Otherwise
8334 * the the gates will remain closed for that
8335 * engine.
8336 */
8337 if (load_counter ||
8338 (global && other_load_counter)) {
8339 /* Wait until all other functions get
8340 * down.
8341 */
8342 schedule_delayed_work(&bp->sp_rtnl_task,
8343 HZ/10);
8344 return;
8345 } else {
8346 /* If all other functions got down -
8347 * try to bring the chip back to
8348 * normal. In any case it's an exit
8349 * point for a leader.
8350 */
8351 if (bnx2x_leader_reset(bp)) {
8352 bnx2x_recovery_failed(bp);
8353 return;
8354 }
8355
8356 /* If we are here, means that the
8357 * leader has succeeded and doesn't
8358 * want to be a leader any more. Try
8359 * to continue as a none-leader.
8360 */
8361 break;
8362 }
8363 } else { /* non-leader */
8364 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8365 /* Try to get a LEADER_LOCK HW lock as
8366 * long as a former leader may have
8367 * been unloaded by the user or
8368 * released a leadership by another
8369 * reason.
8370 */
8371 if (bnx2x_trylock_leader_lock(bp)) {
8372 /* I'm a leader now! Restart a
8373 * switch case.
8374 */
8375 bp->is_leader = 1;
8376 break;
8377 }
8378
8379 schedule_delayed_work(&bp->sp_rtnl_task,
8380 HZ/10);
8381 return;
8382
8383 } else {
8384 /*
8385 * If there was a global attention, wait
8386 * for it to be cleared.
8387 */
8388 if (bnx2x_reset_is_global(bp)) {
8389 schedule_delayed_work(
8390 &bp->sp_rtnl_task,
8391 HZ/10);
8392 return;
8393 }
8394
8395 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8396 bnx2x_recovery_failed(bp);
8397 else {
8398 bp->recovery_state =
8399 BNX2X_RECOVERY_DONE;
8400 smp_mb();
8401 }
8402
8403 return;
8404 }
8405 }
8406 default:
8407 return;
8408 }
8409 }
8410 }
8411
8412 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8413 * scheduled on a general queue in order to prevent a dead lock.
8414 */
8415 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8416 {
8417 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8418
8419 rtnl_lock();
8420
8421 if (!netif_running(bp->dev))
8422 goto sp_rtnl_exit;
8423
8424 /* if stop on error is defined no recovery flows should be executed */
8425 #ifdef BNX2X_STOP_ON_ERROR
8426 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8427 "so reset not done to allow debug dump,\n"
8428 "you will need to reboot when done\n");
8429 goto sp_rtnl_not_reset;
8430 #endif
8431
8432 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8433 /*
8434 * Clear all pending SP commands as we are going to reset the
8435 * function anyway.
8436 */
8437 bp->sp_rtnl_state = 0;
8438 smp_mb();
8439
8440 bnx2x_parity_recover(bp);
8441
8442 goto sp_rtnl_exit;
8443 }
8444
8445 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8446 /*
8447 * Clear all pending SP commands as we are going to reset the
8448 * function anyway.
8449 */
8450 bp->sp_rtnl_state = 0;
8451 smp_mb();
8452
8453 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8454 bnx2x_nic_load(bp, LOAD_NORMAL);
8455
8456 goto sp_rtnl_exit;
8457 }
8458 #ifdef BNX2X_STOP_ON_ERROR
8459 sp_rtnl_not_reset:
8460 #endif
8461 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8462 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8463
8464 sp_rtnl_exit:
8465 rtnl_unlock();
8466 }
8467
8468 /* end of nic load/unload */
8469
8470 static void bnx2x_period_task(struct work_struct *work)
8471 {
8472 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8473
8474 if (!netif_running(bp->dev))
8475 goto period_task_exit;
8476
8477 if (CHIP_REV_IS_SLOW(bp)) {
8478 BNX2X_ERR("period task called on emulation, ignoring\n");
8479 goto period_task_exit;
8480 }
8481
8482 bnx2x_acquire_phy_lock(bp);
8483 /*
8484 * The barrier is needed to ensure the ordering between the writing to
8485 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8486 * the reading here.
8487 */
8488 smp_mb();
8489 if (bp->port.pmf) {
8490 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8491
8492 /* Re-queue task in 1 sec */
8493 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8494 }
8495
8496 bnx2x_release_phy_lock(bp);
8497 period_task_exit:
8498 return;
8499 }
8500
8501 /*
8502 * Init service functions
8503 */
8504
8505 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8506 {
8507 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8508 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8509 return base + (BP_ABS_FUNC(bp)) * stride;
8510 }
8511
8512 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8513 {
8514 u32 reg = bnx2x_get_pretend_reg(bp);
8515
8516 /* Flush all outstanding writes */
8517 mmiowb();
8518
8519 /* Pretend to be function 0 */
8520 REG_WR(bp, reg, 0);
8521 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8522
8523 /* From now we are in the "like-E1" mode */
8524 bnx2x_int_disable(bp);
8525
8526 /* Flush all outstanding writes */
8527 mmiowb();
8528
8529 /* Restore the original function */
8530 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8531 REG_RD(bp, reg);
8532 }
8533
8534 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8535 {
8536 if (CHIP_IS_E1(bp))
8537 bnx2x_int_disable(bp);
8538 else
8539 bnx2x_undi_int_disable_e1h(bp);
8540 }
8541
8542 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8543 {
8544 u32 val;
8545
8546 /* Check if there is any driver already loaded */
8547 val = REG_RD(bp, MISC_REG_UNPREPARED);
8548 if (val == 0x1) {
8549 /* Check if it is the UNDI driver
8550 * UNDI driver initializes CID offset for normal bell to 0x7
8551 */
8552 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8553 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8554 if (val == 0x7) {
8555 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8556 /* save our pf_num */
8557 int orig_pf_num = bp->pf_num;
8558 int port;
8559 u32 swap_en, swap_val, value;
8560
8561 /* clear the UNDI indication */
8562 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8563
8564 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8565
8566 /* try unload UNDI on port 0 */
8567 bp->pf_num = 0;
8568 bp->fw_seq =
8569 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8570 DRV_MSG_SEQ_NUMBER_MASK);
8571 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8572
8573 /* if UNDI is loaded on the other port */
8574 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8575
8576 /* send "DONE" for previous unload */
8577 bnx2x_fw_command(bp,
8578 DRV_MSG_CODE_UNLOAD_DONE, 0);
8579
8580 /* unload UNDI on port 1 */
8581 bp->pf_num = 1;
8582 bp->fw_seq =
8583 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8584 DRV_MSG_SEQ_NUMBER_MASK);
8585 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8586
8587 bnx2x_fw_command(bp, reset_code, 0);
8588 }
8589
8590 /* now it's safe to release the lock */
8591 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8592
8593 bnx2x_undi_int_disable(bp);
8594 port = BP_PORT(bp);
8595
8596 /* close input traffic and wait for it */
8597 /* Do not rcv packets to BRB */
8598 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8599 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8600 /* Do not direct rcv packets that are not for MCP to
8601 * the BRB */
8602 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8603 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8604 /* clear AEU */
8605 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8606 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8607 msleep(10);
8608
8609 /* save NIG port swap info */
8610 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8611 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8612 /* reset device */
8613 REG_WR(bp,
8614 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8615 0xd3ffffff);
8616
8617 value = 0x1400;
8618 if (CHIP_IS_E3(bp)) {
8619 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8620 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8621 }
8622
8623 REG_WR(bp,
8624 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8625 value);
8626
8627 /* take the NIG out of reset and restore swap values */
8628 REG_WR(bp,
8629 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8630 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8631 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8632 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8633
8634 /* send unload done to the MCP */
8635 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8636
8637 /* restore our func and fw_seq */
8638 bp->pf_num = orig_pf_num;
8639 bp->fw_seq =
8640 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8641 DRV_MSG_SEQ_NUMBER_MASK);
8642 } else
8643 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8644 }
8645 }
8646
8647 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8648 {
8649 u32 val, val2, val3, val4, id;
8650 u16 pmc;
8651
8652 /* Get the chip revision id and number. */
8653 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8654 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8655 id = ((val & 0xffff) << 16);
8656 val = REG_RD(bp, MISC_REG_CHIP_REV);
8657 id |= ((val & 0xf) << 12);
8658 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8659 id |= ((val & 0xff) << 4);
8660 val = REG_RD(bp, MISC_REG_BOND_ID);
8661 id |= (val & 0xf);
8662 bp->common.chip_id = id;
8663
8664 /* Set doorbell size */
8665 bp->db_size = (1 << BNX2X_DB_SHIFT);
8666
8667 if (!CHIP_IS_E1x(bp)) {
8668 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8669 if ((val & 1) == 0)
8670 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8671 else
8672 val = (val >> 1) & 1;
8673 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8674 "2_PORT_MODE");
8675 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8676 CHIP_2_PORT_MODE;
8677
8678 if (CHIP_MODE_IS_4_PORT(bp))
8679 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8680 else
8681 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8682 } else {
8683 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8684 bp->pfid = bp->pf_num; /* 0..7 */
8685 }
8686
8687 bp->link_params.chip_id = bp->common.chip_id;
8688 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8689
8690 val = (REG_RD(bp, 0x2874) & 0x55);
8691 if ((bp->common.chip_id & 0x1) ||
8692 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8693 bp->flags |= ONE_PORT_FLAG;
8694 BNX2X_DEV_INFO("single port device\n");
8695 }
8696
8697 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8698 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8699 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8700 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8701 bp->common.flash_size, bp->common.flash_size);
8702
8703 bnx2x_init_shmem(bp);
8704
8705
8706
8707 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8708 MISC_REG_GENERIC_CR_1 :
8709 MISC_REG_GENERIC_CR_0));
8710
8711 bp->link_params.shmem_base = bp->common.shmem_base;
8712 bp->link_params.shmem2_base = bp->common.shmem2_base;
8713 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8714 bp->common.shmem_base, bp->common.shmem2_base);
8715
8716 if (!bp->common.shmem_base) {
8717 BNX2X_DEV_INFO("MCP not active\n");
8718 bp->flags |= NO_MCP_FLAG;
8719 return;
8720 }
8721
8722 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8723 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8724
8725 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8726 SHARED_HW_CFG_LED_MODE_MASK) >>
8727 SHARED_HW_CFG_LED_MODE_SHIFT);
8728
8729 bp->link_params.feature_config_flags = 0;
8730 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8731 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8732 bp->link_params.feature_config_flags |=
8733 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8734 else
8735 bp->link_params.feature_config_flags &=
8736 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8737
8738 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8739 bp->common.bc_ver = val;
8740 BNX2X_DEV_INFO("bc_ver %X\n", val);
8741 if (val < BNX2X_BC_VER) {
8742 /* for now only warn
8743 * later we might need to enforce this */
8744 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8745 "please upgrade BC\n", BNX2X_BC_VER, val);
8746 }
8747 bp->link_params.feature_config_flags |=
8748 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8749 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8750
8751 bp->link_params.feature_config_flags |=
8752 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8753 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8754
8755 bp->link_params.feature_config_flags |=
8756 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8757 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8758
8759 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8760 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8761
8762 BNX2X_DEV_INFO("%sWoL capable\n",
8763 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8764
8765 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8766 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8767 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8768 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8769
8770 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8771 val, val2, val3, val4);
8772 }
8773
8774 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8775 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8776
8777 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8778 {
8779 int pfid = BP_FUNC(bp);
8780 int vn = BP_E1HVN(bp);
8781 int igu_sb_id;
8782 u32 val;
8783 u8 fid, igu_sb_cnt = 0;
8784
8785 bp->igu_base_sb = 0xff;
8786 if (CHIP_INT_MODE_IS_BC(bp)) {
8787 igu_sb_cnt = bp->igu_sb_cnt;
8788 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8789 FP_SB_MAX_E1x;
8790
8791 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8792 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8793
8794 return;
8795 }
8796
8797 /* IGU in normal mode - read CAM */
8798 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8799 igu_sb_id++) {
8800 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8801 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8802 continue;
8803 fid = IGU_FID(val);
8804 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8805 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8806 continue;
8807 if (IGU_VEC(val) == 0)
8808 /* default status block */
8809 bp->igu_dsb_id = igu_sb_id;
8810 else {
8811 if (bp->igu_base_sb == 0xff)
8812 bp->igu_base_sb = igu_sb_id;
8813 igu_sb_cnt++;
8814 }
8815 }
8816 }
8817
8818 #ifdef CONFIG_PCI_MSI
8819 /*
8820 * It's expected that number of CAM entries for this functions is equal
8821 * to the number evaluated based on the MSI-X table size. We want a
8822 * harsh warning if these values are different!
8823 */
8824 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8825 #endif
8826
8827 if (igu_sb_cnt == 0)
8828 BNX2X_ERR("CAM configuration error\n");
8829 }
8830
8831 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8832 u32 switch_cfg)
8833 {
8834 int cfg_size = 0, idx, port = BP_PORT(bp);
8835
8836 /* Aggregation of supported attributes of all external phys */
8837 bp->port.supported[0] = 0;
8838 bp->port.supported[1] = 0;
8839 switch (bp->link_params.num_phys) {
8840 case 1:
8841 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8842 cfg_size = 1;
8843 break;
8844 case 2:
8845 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8846 cfg_size = 1;
8847 break;
8848 case 3:
8849 if (bp->link_params.multi_phy_config &
8850 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8851 bp->port.supported[1] =
8852 bp->link_params.phy[EXT_PHY1].supported;
8853 bp->port.supported[0] =
8854 bp->link_params.phy[EXT_PHY2].supported;
8855 } else {
8856 bp->port.supported[0] =
8857 bp->link_params.phy[EXT_PHY1].supported;
8858 bp->port.supported[1] =
8859 bp->link_params.phy[EXT_PHY2].supported;
8860 }
8861 cfg_size = 2;
8862 break;
8863 }
8864
8865 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8866 BNX2X_ERR("NVRAM config error. BAD phy config."
8867 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8868 SHMEM_RD(bp,
8869 dev_info.port_hw_config[port].external_phy_config),
8870 SHMEM_RD(bp,
8871 dev_info.port_hw_config[port].external_phy_config2));
8872 return;
8873 }
8874
8875 if (CHIP_IS_E3(bp))
8876 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8877 else {
8878 switch (switch_cfg) {
8879 case SWITCH_CFG_1G:
8880 bp->port.phy_addr = REG_RD(
8881 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8882 break;
8883 case SWITCH_CFG_10G:
8884 bp->port.phy_addr = REG_RD(
8885 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8886 break;
8887 default:
8888 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8889 bp->port.link_config[0]);
8890 return;
8891 }
8892 }
8893 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8894 /* mask what we support according to speed_cap_mask per configuration */
8895 for (idx = 0; idx < cfg_size; idx++) {
8896 if (!(bp->link_params.speed_cap_mask[idx] &
8897 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8898 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8899
8900 if (!(bp->link_params.speed_cap_mask[idx] &
8901 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8902 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8903
8904 if (!(bp->link_params.speed_cap_mask[idx] &
8905 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8906 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8907
8908 if (!(bp->link_params.speed_cap_mask[idx] &
8909 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8910 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8911
8912 if (!(bp->link_params.speed_cap_mask[idx] &
8913 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8914 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8915 SUPPORTED_1000baseT_Full);
8916
8917 if (!(bp->link_params.speed_cap_mask[idx] &
8918 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8919 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8920
8921 if (!(bp->link_params.speed_cap_mask[idx] &
8922 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8923 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8924
8925 }
8926
8927 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8928 bp->port.supported[1]);
8929 }
8930
8931 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8932 {
8933 u32 link_config, idx, cfg_size = 0;
8934 bp->port.advertising[0] = 0;
8935 bp->port.advertising[1] = 0;
8936 switch (bp->link_params.num_phys) {
8937 case 1:
8938 case 2:
8939 cfg_size = 1;
8940 break;
8941 case 3:
8942 cfg_size = 2;
8943 break;
8944 }
8945 for (idx = 0; idx < cfg_size; idx++) {
8946 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8947 link_config = bp->port.link_config[idx];
8948 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8949 case PORT_FEATURE_LINK_SPEED_AUTO:
8950 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8951 bp->link_params.req_line_speed[idx] =
8952 SPEED_AUTO_NEG;
8953 bp->port.advertising[idx] |=
8954 bp->port.supported[idx];
8955 } else {
8956 /* force 10G, no AN */
8957 bp->link_params.req_line_speed[idx] =
8958 SPEED_10000;
8959 bp->port.advertising[idx] |=
8960 (ADVERTISED_10000baseT_Full |
8961 ADVERTISED_FIBRE);
8962 continue;
8963 }
8964 break;
8965
8966 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8967 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8968 bp->link_params.req_line_speed[idx] =
8969 SPEED_10;
8970 bp->port.advertising[idx] |=
8971 (ADVERTISED_10baseT_Full |
8972 ADVERTISED_TP);
8973 } else {
8974 BNX2X_ERR("NVRAM config error. "
8975 "Invalid link_config 0x%x"
8976 " speed_cap_mask 0x%x\n",
8977 link_config,
8978 bp->link_params.speed_cap_mask[idx]);
8979 return;
8980 }
8981 break;
8982
8983 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8984 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8985 bp->link_params.req_line_speed[idx] =
8986 SPEED_10;
8987 bp->link_params.req_duplex[idx] =
8988 DUPLEX_HALF;
8989 bp->port.advertising[idx] |=
8990 (ADVERTISED_10baseT_Half |
8991 ADVERTISED_TP);
8992 } else {
8993 BNX2X_ERR("NVRAM config error. "
8994 "Invalid link_config 0x%x"
8995 " speed_cap_mask 0x%x\n",
8996 link_config,
8997 bp->link_params.speed_cap_mask[idx]);
8998 return;
8999 }
9000 break;
9001
9002 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9003 if (bp->port.supported[idx] &
9004 SUPPORTED_100baseT_Full) {
9005 bp->link_params.req_line_speed[idx] =
9006 SPEED_100;
9007 bp->port.advertising[idx] |=
9008 (ADVERTISED_100baseT_Full |
9009 ADVERTISED_TP);
9010 } else {
9011 BNX2X_ERR("NVRAM config error. "
9012 "Invalid link_config 0x%x"
9013 " speed_cap_mask 0x%x\n",
9014 link_config,
9015 bp->link_params.speed_cap_mask[idx]);
9016 return;
9017 }
9018 break;
9019
9020 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9021 if (bp->port.supported[idx] &
9022 SUPPORTED_100baseT_Half) {
9023 bp->link_params.req_line_speed[idx] =
9024 SPEED_100;
9025 bp->link_params.req_duplex[idx] =
9026 DUPLEX_HALF;
9027 bp->port.advertising[idx] |=
9028 (ADVERTISED_100baseT_Half |
9029 ADVERTISED_TP);
9030 } else {
9031 BNX2X_ERR("NVRAM config error. "
9032 "Invalid link_config 0x%x"
9033 " speed_cap_mask 0x%x\n",
9034 link_config,
9035 bp->link_params.speed_cap_mask[idx]);
9036 return;
9037 }
9038 break;
9039
9040 case PORT_FEATURE_LINK_SPEED_1G:
9041 if (bp->port.supported[idx] &
9042 SUPPORTED_1000baseT_Full) {
9043 bp->link_params.req_line_speed[idx] =
9044 SPEED_1000;
9045 bp->port.advertising[idx] |=
9046 (ADVERTISED_1000baseT_Full |
9047 ADVERTISED_TP);
9048 } else {
9049 BNX2X_ERR("NVRAM config error. "
9050 "Invalid link_config 0x%x"
9051 " speed_cap_mask 0x%x\n",
9052 link_config,
9053 bp->link_params.speed_cap_mask[idx]);
9054 return;
9055 }
9056 break;
9057
9058 case PORT_FEATURE_LINK_SPEED_2_5G:
9059 if (bp->port.supported[idx] &
9060 SUPPORTED_2500baseX_Full) {
9061 bp->link_params.req_line_speed[idx] =
9062 SPEED_2500;
9063 bp->port.advertising[idx] |=
9064 (ADVERTISED_2500baseX_Full |
9065 ADVERTISED_TP);
9066 } else {
9067 BNX2X_ERR("NVRAM config error. "
9068 "Invalid link_config 0x%x"
9069 " speed_cap_mask 0x%x\n",
9070 link_config,
9071 bp->link_params.speed_cap_mask[idx]);
9072 return;
9073 }
9074 break;
9075
9076 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9077 if (bp->port.supported[idx] &
9078 SUPPORTED_10000baseT_Full) {
9079 bp->link_params.req_line_speed[idx] =
9080 SPEED_10000;
9081 bp->port.advertising[idx] |=
9082 (ADVERTISED_10000baseT_Full |
9083 ADVERTISED_FIBRE);
9084 } else {
9085 BNX2X_ERR("NVRAM config error. "
9086 "Invalid link_config 0x%x"
9087 " speed_cap_mask 0x%x\n",
9088 link_config,
9089 bp->link_params.speed_cap_mask[idx]);
9090 return;
9091 }
9092 break;
9093 case PORT_FEATURE_LINK_SPEED_20G:
9094 bp->link_params.req_line_speed[idx] = SPEED_20000;
9095
9096 break;
9097 default:
9098 BNX2X_ERR("NVRAM config error. "
9099 "BAD link speed link_config 0x%x\n",
9100 link_config);
9101 bp->link_params.req_line_speed[idx] =
9102 SPEED_AUTO_NEG;
9103 bp->port.advertising[idx] =
9104 bp->port.supported[idx];
9105 break;
9106 }
9107
9108 bp->link_params.req_flow_ctrl[idx] = (link_config &
9109 PORT_FEATURE_FLOW_CONTROL_MASK);
9110 if ((bp->link_params.req_flow_ctrl[idx] ==
9111 BNX2X_FLOW_CTRL_AUTO) &&
9112 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9113 bp->link_params.req_flow_ctrl[idx] =
9114 BNX2X_FLOW_CTRL_NONE;
9115 }
9116
9117 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9118 " 0x%x advertising 0x%x\n",
9119 bp->link_params.req_line_speed[idx],
9120 bp->link_params.req_duplex[idx],
9121 bp->link_params.req_flow_ctrl[idx],
9122 bp->port.advertising[idx]);
9123 }
9124 }
9125
9126 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9127 {
9128 mac_hi = cpu_to_be16(mac_hi);
9129 mac_lo = cpu_to_be32(mac_lo);
9130 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9131 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9132 }
9133
9134 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9135 {
9136 int port = BP_PORT(bp);
9137 u32 config;
9138 u32 ext_phy_type, ext_phy_config;
9139
9140 bp->link_params.bp = bp;
9141 bp->link_params.port = port;
9142
9143 bp->link_params.lane_config =
9144 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9145
9146 bp->link_params.speed_cap_mask[0] =
9147 SHMEM_RD(bp,
9148 dev_info.port_hw_config[port].speed_capability_mask);
9149 bp->link_params.speed_cap_mask[1] =
9150 SHMEM_RD(bp,
9151 dev_info.port_hw_config[port].speed_capability_mask2);
9152 bp->port.link_config[0] =
9153 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9154
9155 bp->port.link_config[1] =
9156 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9157
9158 bp->link_params.multi_phy_config =
9159 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9160 /* If the device is capable of WoL, set the default state according
9161 * to the HW
9162 */
9163 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9164 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9165 (config & PORT_FEATURE_WOL_ENABLED));
9166
9167 BNX2X_DEV_INFO("lane_config 0x%08x "
9168 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9169 bp->link_params.lane_config,
9170 bp->link_params.speed_cap_mask[0],
9171 bp->port.link_config[0]);
9172
9173 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9174 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9175 bnx2x_phy_probe(&bp->link_params);
9176 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9177
9178 bnx2x_link_settings_requested(bp);
9179
9180 /*
9181 * If connected directly, work with the internal PHY, otherwise, work
9182 * with the external PHY
9183 */
9184 ext_phy_config =
9185 SHMEM_RD(bp,
9186 dev_info.port_hw_config[port].external_phy_config);
9187 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9188 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9189 bp->mdio.prtad = bp->port.phy_addr;
9190
9191 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9192 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9193 bp->mdio.prtad =
9194 XGXS_EXT_PHY_ADDR(ext_phy_config);
9195
9196 /*
9197 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9198 * In MF mode, it is set to cover self test cases
9199 */
9200 if (IS_MF(bp))
9201 bp->port.need_hw_lock = 1;
9202 else
9203 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9204 bp->common.shmem_base,
9205 bp->common.shmem2_base);
9206 }
9207
9208 #ifdef BCM_CNIC
9209 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9210 {
9211 int port = BP_PORT(bp);
9212 int func = BP_ABS_FUNC(bp);
9213
9214 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9215 drv_lic_key[port].max_iscsi_conn);
9216 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9217 drv_lic_key[port].max_fcoe_conn);
9218
9219 /* Get the number of maximum allowed iSCSI and FCoE connections */
9220 bp->cnic_eth_dev.max_iscsi_conn =
9221 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9222 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9223
9224 bp->cnic_eth_dev.max_fcoe_conn =
9225 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9226 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9227
9228 /* Read the WWN: */
9229 if (!IS_MF(bp)) {
9230 /* Port info */
9231 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9232 SHMEM_RD(bp,
9233 dev_info.port_hw_config[port].
9234 fcoe_wwn_port_name_upper);
9235 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9236 SHMEM_RD(bp,
9237 dev_info.port_hw_config[port].
9238 fcoe_wwn_port_name_lower);
9239
9240 /* Node info */
9241 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9242 SHMEM_RD(bp,
9243 dev_info.port_hw_config[port].
9244 fcoe_wwn_node_name_upper);
9245 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9246 SHMEM_RD(bp,
9247 dev_info.port_hw_config[port].
9248 fcoe_wwn_node_name_lower);
9249 } else if (!IS_MF_SD(bp)) {
9250 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9251
9252 /*
9253 * Read the WWN info only if the FCoE feature is enabled for
9254 * this function.
9255 */
9256 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9257 /* Port info */
9258 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9259 MF_CFG_RD(bp, func_ext_config[func].
9260 fcoe_wwn_port_name_upper);
9261 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9262 MF_CFG_RD(bp, func_ext_config[func].
9263 fcoe_wwn_port_name_lower);
9264
9265 /* Node info */
9266 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9267 MF_CFG_RD(bp, func_ext_config[func].
9268 fcoe_wwn_node_name_upper);
9269 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9270 MF_CFG_RD(bp, func_ext_config[func].
9271 fcoe_wwn_node_name_lower);
9272 }
9273 }
9274
9275 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9276 bp->cnic_eth_dev.max_iscsi_conn,
9277 bp->cnic_eth_dev.max_fcoe_conn);
9278
9279 /*
9280 * If maximum allowed number of connections is zero -
9281 * disable the feature.
9282 */
9283 if (!bp->cnic_eth_dev.max_iscsi_conn)
9284 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9285
9286 if (!bp->cnic_eth_dev.max_fcoe_conn)
9287 bp->flags |= NO_FCOE_FLAG;
9288 }
9289 #endif
9290
9291 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9292 {
9293 u32 val, val2;
9294 int func = BP_ABS_FUNC(bp);
9295 int port = BP_PORT(bp);
9296 #ifdef BCM_CNIC
9297 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9298 u8 *fip_mac = bp->fip_mac;
9299 #endif
9300
9301 /* Zero primary MAC configuration */
9302 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9303
9304 if (BP_NOMCP(bp)) {
9305 BNX2X_ERROR("warning: random MAC workaround active\n");
9306 random_ether_addr(bp->dev->dev_addr);
9307 } else if (IS_MF(bp)) {
9308 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9309 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9310 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9311 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9312 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9313
9314 #ifdef BCM_CNIC
9315 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9316 * FCoE MAC then the appropriate feature should be disabled.
9317 */
9318 if (IS_MF_SI(bp)) {
9319 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9320 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9321 val2 = MF_CFG_RD(bp, func_ext_config[func].
9322 iscsi_mac_addr_upper);
9323 val = MF_CFG_RD(bp, func_ext_config[func].
9324 iscsi_mac_addr_lower);
9325 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9326 BNX2X_DEV_INFO("Read iSCSI MAC: "
9327 BNX2X_MAC_FMT"\n",
9328 BNX2X_MAC_PRN_LIST(iscsi_mac));
9329 } else
9330 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9331
9332 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9333 val2 = MF_CFG_RD(bp, func_ext_config[func].
9334 fcoe_mac_addr_upper);
9335 val = MF_CFG_RD(bp, func_ext_config[func].
9336 fcoe_mac_addr_lower);
9337 bnx2x_set_mac_buf(fip_mac, val, val2);
9338 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9339 BNX2X_MAC_FMT"\n",
9340 BNX2X_MAC_PRN_LIST(fip_mac));
9341
9342 } else
9343 bp->flags |= NO_FCOE_FLAG;
9344 }
9345 #endif
9346 } else {
9347 /* in SF read MACs from port configuration */
9348 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9349 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9350 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9351
9352 #ifdef BCM_CNIC
9353 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9354 iscsi_mac_upper);
9355 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9356 iscsi_mac_lower);
9357 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9358
9359 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9360 fcoe_fip_mac_upper);
9361 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9362 fcoe_fip_mac_lower);
9363 bnx2x_set_mac_buf(fip_mac, val, val2);
9364 #endif
9365 }
9366
9367 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9368 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9369
9370 #ifdef BCM_CNIC
9371 /* Set the FCoE MAC in MF_SD mode */
9372 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9373 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9374
9375 /* Disable iSCSI if MAC configuration is
9376 * invalid.
9377 */
9378 if (!is_valid_ether_addr(iscsi_mac)) {
9379 bp->flags |= NO_ISCSI_FLAG;
9380 memset(iscsi_mac, 0, ETH_ALEN);
9381 }
9382
9383 /* Disable FCoE if MAC configuration is
9384 * invalid.
9385 */
9386 if (!is_valid_ether_addr(fip_mac)) {
9387 bp->flags |= NO_FCOE_FLAG;
9388 memset(bp->fip_mac, 0, ETH_ALEN);
9389 }
9390 #endif
9391
9392 if (!is_valid_ether_addr(bp->dev->dev_addr))
9393 dev_err(&bp->pdev->dev,
9394 "bad Ethernet MAC address configuration: "
9395 BNX2X_MAC_FMT", change it manually before bringing up "
9396 "the appropriate network interface\n",
9397 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
9398 }
9399
9400 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9401 {
9402 int /*abs*/func = BP_ABS_FUNC(bp);
9403 int vn;
9404 u32 val = 0;
9405 int rc = 0;
9406
9407 bnx2x_get_common_hwinfo(bp);
9408
9409 /*
9410 * initialize IGU parameters
9411 */
9412 if (CHIP_IS_E1x(bp)) {
9413 bp->common.int_block = INT_BLOCK_HC;
9414
9415 bp->igu_dsb_id = DEF_SB_IGU_ID;
9416 bp->igu_base_sb = 0;
9417 } else {
9418 bp->common.int_block = INT_BLOCK_IGU;
9419 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9420
9421 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9422 int tout = 5000;
9423
9424 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9425
9426 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9427 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9428 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9429
9430 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9431 tout--;
9432 usleep_range(1000, 1000);
9433 }
9434
9435 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9436 dev_err(&bp->pdev->dev,
9437 "FORCING Normal Mode failed!!!\n");
9438 return -EPERM;
9439 }
9440 }
9441
9442 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9443 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9444 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9445 } else
9446 BNX2X_DEV_INFO("IGU Normal Mode\n");
9447
9448 bnx2x_get_igu_cam_info(bp);
9449
9450 }
9451
9452 /*
9453 * set base FW non-default (fast path) status block id, this value is
9454 * used to initialize the fw_sb_id saved on the fp/queue structure to
9455 * determine the id used by the FW.
9456 */
9457 if (CHIP_IS_E1x(bp))
9458 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9459 else /*
9460 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9461 * the same queue are indicated on the same IGU SB). So we prefer
9462 * FW and IGU SBs to be the same value.
9463 */
9464 bp->base_fw_ndsb = bp->igu_base_sb;
9465
9466 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9467 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9468 bp->igu_sb_cnt, bp->base_fw_ndsb);
9469
9470 /*
9471 * Initialize MF configuration
9472 */
9473
9474 bp->mf_ov = 0;
9475 bp->mf_mode = 0;
9476 vn = BP_E1HVN(bp);
9477
9478 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9479 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9480 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9481 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9482
9483 if (SHMEM2_HAS(bp, mf_cfg_addr))
9484 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9485 else
9486 bp->common.mf_cfg_base = bp->common.shmem_base +
9487 offsetof(struct shmem_region, func_mb) +
9488 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9489 /*
9490 * get mf configuration:
9491 * 1. existence of MF configuration
9492 * 2. MAC address must be legal (check only upper bytes)
9493 * for Switch-Independent mode;
9494 * OVLAN must be legal for Switch-Dependent mode
9495 * 3. SF_MODE configures specific MF mode
9496 */
9497 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9498 /* get mf configuration */
9499 val = SHMEM_RD(bp,
9500 dev_info.shared_feature_config.config);
9501 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9502
9503 switch (val) {
9504 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9505 val = MF_CFG_RD(bp, func_mf_config[func].
9506 mac_upper);
9507 /* check for legal mac (upper bytes)*/
9508 if (val != 0xffff) {
9509 bp->mf_mode = MULTI_FUNCTION_SI;
9510 bp->mf_config[vn] = MF_CFG_RD(bp,
9511 func_mf_config[func].config);
9512 } else
9513 BNX2X_DEV_INFO("illegal MAC address "
9514 "for SI\n");
9515 break;
9516 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9517 /* get OV configuration */
9518 val = MF_CFG_RD(bp,
9519 func_mf_config[FUNC_0].e1hov_tag);
9520 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9521
9522 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9523 bp->mf_mode = MULTI_FUNCTION_SD;
9524 bp->mf_config[vn] = MF_CFG_RD(bp,
9525 func_mf_config[func].config);
9526 } else
9527 BNX2X_DEV_INFO("illegal OV for SD\n");
9528 break;
9529 default:
9530 /* Unknown configuration: reset mf_config */
9531 bp->mf_config[vn] = 0;
9532 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9533 }
9534 }
9535
9536 BNX2X_DEV_INFO("%s function mode\n",
9537 IS_MF(bp) ? "multi" : "single");
9538
9539 switch (bp->mf_mode) {
9540 case MULTI_FUNCTION_SD:
9541 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9542 FUNC_MF_CFG_E1HOV_TAG_MASK;
9543 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9544 bp->mf_ov = val;
9545 bp->path_has_ovlan = true;
9546
9547 BNX2X_DEV_INFO("MF OV for func %d is %d "
9548 "(0x%04x)\n", func, bp->mf_ov,
9549 bp->mf_ov);
9550 } else {
9551 dev_err(&bp->pdev->dev,
9552 "No valid MF OV for func %d, "
9553 "aborting\n", func);
9554 return -EPERM;
9555 }
9556 break;
9557 case MULTI_FUNCTION_SI:
9558 BNX2X_DEV_INFO("func %d is in MF "
9559 "switch-independent mode\n", func);
9560 break;
9561 default:
9562 if (vn) {
9563 dev_err(&bp->pdev->dev,
9564 "VN %d is in a single function mode, "
9565 "aborting\n", vn);
9566 return -EPERM;
9567 }
9568 break;
9569 }
9570
9571 /* check if other port on the path needs ovlan:
9572 * Since MF configuration is shared between ports
9573 * Possible mixed modes are only
9574 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9575 */
9576 if (CHIP_MODE_IS_4_PORT(bp) &&
9577 !bp->path_has_ovlan &&
9578 !IS_MF(bp) &&
9579 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9580 u8 other_port = !BP_PORT(bp);
9581 u8 other_func = BP_PATH(bp) + 2*other_port;
9582 val = MF_CFG_RD(bp,
9583 func_mf_config[other_func].e1hov_tag);
9584 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9585 bp->path_has_ovlan = true;
9586 }
9587 }
9588
9589 /* adjust igu_sb_cnt to MF for E1x */
9590 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9591 bp->igu_sb_cnt /= E1HVN_MAX;
9592
9593 /* port info */
9594 bnx2x_get_port_hwinfo(bp);
9595
9596 if (!BP_NOMCP(bp)) {
9597 bp->fw_seq =
9598 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9599 DRV_MSG_SEQ_NUMBER_MASK);
9600 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9601 }
9602
9603 /* Get MAC addresses */
9604 bnx2x_get_mac_hwinfo(bp);
9605
9606 #ifdef BCM_CNIC
9607 bnx2x_get_cnic_info(bp);
9608 #endif
9609
9610 /* Get current FW pulse sequence */
9611 if (!BP_NOMCP(bp)) {
9612 int mb_idx = BP_FW_MB_IDX(bp);
9613
9614 bp->fw_drv_pulse_wr_seq =
9615 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9616 DRV_PULSE_SEQ_MASK);
9617 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9618 }
9619
9620 return rc;
9621 }
9622
9623 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9624 {
9625 int cnt, i, block_end, rodi;
9626 char vpd_data[BNX2X_VPD_LEN+1];
9627 char str_id_reg[VENDOR_ID_LEN+1];
9628 char str_id_cap[VENDOR_ID_LEN+1];
9629 u8 len;
9630
9631 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9632 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9633
9634 if (cnt < BNX2X_VPD_LEN)
9635 goto out_not_found;
9636
9637 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9638 PCI_VPD_LRDT_RO_DATA);
9639 if (i < 0)
9640 goto out_not_found;
9641
9642
9643 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9644 pci_vpd_lrdt_size(&vpd_data[i]);
9645
9646 i += PCI_VPD_LRDT_TAG_SIZE;
9647
9648 if (block_end > BNX2X_VPD_LEN)
9649 goto out_not_found;
9650
9651 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9652 PCI_VPD_RO_KEYWORD_MFR_ID);
9653 if (rodi < 0)
9654 goto out_not_found;
9655
9656 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9657
9658 if (len != VENDOR_ID_LEN)
9659 goto out_not_found;
9660
9661 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9662
9663 /* vendor specific info */
9664 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9665 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9666 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9667 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9668
9669 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9670 PCI_VPD_RO_KEYWORD_VENDOR0);
9671 if (rodi >= 0) {
9672 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9673
9674 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9675
9676 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9677 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9678 bp->fw_ver[len] = ' ';
9679 }
9680 }
9681 return;
9682 }
9683 out_not_found:
9684 return;
9685 }
9686
9687 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9688 {
9689 u32 flags = 0;
9690
9691 if (CHIP_REV_IS_FPGA(bp))
9692 SET_FLAGS(flags, MODE_FPGA);
9693 else if (CHIP_REV_IS_EMUL(bp))
9694 SET_FLAGS(flags, MODE_EMUL);
9695 else
9696 SET_FLAGS(flags, MODE_ASIC);
9697
9698 if (CHIP_MODE_IS_4_PORT(bp))
9699 SET_FLAGS(flags, MODE_PORT4);
9700 else
9701 SET_FLAGS(flags, MODE_PORT2);
9702
9703 if (CHIP_IS_E2(bp))
9704 SET_FLAGS(flags, MODE_E2);
9705 else if (CHIP_IS_E3(bp)) {
9706 SET_FLAGS(flags, MODE_E3);
9707 if (CHIP_REV(bp) == CHIP_REV_Ax)
9708 SET_FLAGS(flags, MODE_E3_A0);
9709 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9710 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9711 }
9712
9713 if (IS_MF(bp)) {
9714 SET_FLAGS(flags, MODE_MF);
9715 switch (bp->mf_mode) {
9716 case MULTI_FUNCTION_SD:
9717 SET_FLAGS(flags, MODE_MF_SD);
9718 break;
9719 case MULTI_FUNCTION_SI:
9720 SET_FLAGS(flags, MODE_MF_SI);
9721 break;
9722 }
9723 } else
9724 SET_FLAGS(flags, MODE_SF);
9725
9726 #if defined(__LITTLE_ENDIAN)
9727 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9728 #else /*(__BIG_ENDIAN)*/
9729 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9730 #endif
9731 INIT_MODE_FLAGS(bp) = flags;
9732 }
9733
9734 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9735 {
9736 int func;
9737 int timer_interval;
9738 int rc;
9739
9740 mutex_init(&bp->port.phy_mutex);
9741 mutex_init(&bp->fw_mb_mutex);
9742 spin_lock_init(&bp->stats_lock);
9743 #ifdef BCM_CNIC
9744 mutex_init(&bp->cnic_mutex);
9745 #endif
9746
9747 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9748 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9749 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9750 rc = bnx2x_get_hwinfo(bp);
9751 if (rc)
9752 return rc;
9753
9754 bnx2x_set_modes_bitmap(bp);
9755
9756 rc = bnx2x_alloc_mem_bp(bp);
9757 if (rc)
9758 return rc;
9759
9760 bnx2x_read_fwinfo(bp);
9761
9762 func = BP_FUNC(bp);
9763
9764 /* need to reset chip if undi was active */
9765 if (!BP_NOMCP(bp))
9766 bnx2x_undi_unload(bp);
9767
9768 if (CHIP_REV_IS_FPGA(bp))
9769 dev_err(&bp->pdev->dev, "FPGA detected\n");
9770
9771 if (BP_NOMCP(bp) && (func == 0))
9772 dev_err(&bp->pdev->dev, "MCP disabled, "
9773 "must load devices in order!\n");
9774
9775 bp->multi_mode = multi_mode;
9776
9777 /* Set TPA flags */
9778 if (disable_tpa) {
9779 bp->flags &= ~TPA_ENABLE_FLAG;
9780 bp->dev->features &= ~NETIF_F_LRO;
9781 } else {
9782 bp->flags |= TPA_ENABLE_FLAG;
9783 bp->dev->features |= NETIF_F_LRO;
9784 }
9785 bp->disable_tpa = disable_tpa;
9786
9787 if (CHIP_IS_E1(bp))
9788 bp->dropless_fc = 0;
9789 else
9790 bp->dropless_fc = dropless_fc;
9791
9792 bp->mrrs = mrrs;
9793
9794 bp->tx_ring_size = MAX_TX_AVAIL;
9795
9796 /* make sure that the numbers are in the right granularity */
9797 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9798 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9799
9800 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9801 bp->current_interval = (poll ? poll : timer_interval);
9802
9803 init_timer(&bp->timer);
9804 bp->timer.expires = jiffies + bp->current_interval;
9805 bp->timer.data = (unsigned long) bp;
9806 bp->timer.function = bnx2x_timer;
9807
9808 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9809 bnx2x_dcbx_init_params(bp);
9810
9811 #ifdef BCM_CNIC
9812 if (CHIP_IS_E1x(bp))
9813 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9814 else
9815 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9816 #endif
9817
9818 /* multiple tx priority */
9819 if (CHIP_IS_E1x(bp))
9820 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9821 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9822 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9823 if (CHIP_IS_E3B0(bp))
9824 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9825
9826 return rc;
9827 }
9828
9829
9830 /****************************************************************************
9831 * General service functions
9832 ****************************************************************************/
9833
9834 /*
9835 * net_device service functions
9836 */
9837
9838 /* called with rtnl_lock */
9839 static int bnx2x_open(struct net_device *dev)
9840 {
9841 struct bnx2x *bp = netdev_priv(dev);
9842 bool global = false;
9843 int other_engine = BP_PATH(bp) ? 0 : 1;
9844 u32 other_load_counter, load_counter;
9845
9846 netif_carrier_off(dev);
9847
9848 bnx2x_set_power_state(bp, PCI_D0);
9849
9850 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9851 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9852
9853 /*
9854 * If parity had happen during the unload, then attentions
9855 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9856 * want the first function loaded on the current engine to
9857 * complete the recovery.
9858 */
9859 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9860 bnx2x_chk_parity_attn(bp, &global, true))
9861 do {
9862 /*
9863 * If there are attentions and they are in a global
9864 * blocks, set the GLOBAL_RESET bit regardless whether
9865 * it will be this function that will complete the
9866 * recovery or not.
9867 */
9868 if (global)
9869 bnx2x_set_reset_global(bp);
9870
9871 /*
9872 * Only the first function on the current engine should
9873 * try to recover in open. In case of attentions in
9874 * global blocks only the first in the chip should try
9875 * to recover.
9876 */
9877 if ((!load_counter &&
9878 (!global || !other_load_counter)) &&
9879 bnx2x_trylock_leader_lock(bp) &&
9880 !bnx2x_leader_reset(bp)) {
9881 netdev_info(bp->dev, "Recovered in open\n");
9882 break;
9883 }
9884
9885 /* recovery has failed... */
9886 bnx2x_set_power_state(bp, PCI_D3hot);
9887 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9888
9889 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9890 " completed yet. Try again later. If u still see this"
9891 " message after a few retries then power cycle is"
9892 " required.\n");
9893
9894 return -EAGAIN;
9895 } while (0);
9896
9897 bp->recovery_state = BNX2X_RECOVERY_DONE;
9898 return bnx2x_nic_load(bp, LOAD_OPEN);
9899 }
9900
9901 /* called with rtnl_lock */
9902 static int bnx2x_close(struct net_device *dev)
9903 {
9904 struct bnx2x *bp = netdev_priv(dev);
9905
9906 /* Unload the driver, release IRQs */
9907 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9908
9909 /* Power off */
9910 bnx2x_set_power_state(bp, PCI_D3hot);
9911
9912 return 0;
9913 }
9914
9915 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9916 struct bnx2x_mcast_ramrod_params *p)
9917 {
9918 int mc_count = netdev_mc_count(bp->dev);
9919 struct bnx2x_mcast_list_elem *mc_mac =
9920 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9921 struct netdev_hw_addr *ha;
9922
9923 if (!mc_mac)
9924 return -ENOMEM;
9925
9926 INIT_LIST_HEAD(&p->mcast_list);
9927
9928 netdev_for_each_mc_addr(ha, bp->dev) {
9929 mc_mac->mac = bnx2x_mc_addr(ha);
9930 list_add_tail(&mc_mac->link, &p->mcast_list);
9931 mc_mac++;
9932 }
9933
9934 p->mcast_list_len = mc_count;
9935
9936 return 0;
9937 }
9938
9939 static inline void bnx2x_free_mcast_macs_list(
9940 struct bnx2x_mcast_ramrod_params *p)
9941 {
9942 struct bnx2x_mcast_list_elem *mc_mac =
9943 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9944 link);
9945
9946 WARN_ON(!mc_mac);
9947 kfree(mc_mac);
9948 }
9949
9950 /**
9951 * bnx2x_set_uc_list - configure a new unicast MACs list.
9952 *
9953 * @bp: driver handle
9954 *
9955 * We will use zero (0) as a MAC type for these MACs.
9956 */
9957 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9958 {
9959 int rc;
9960 struct net_device *dev = bp->dev;
9961 struct netdev_hw_addr *ha;
9962 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9963 unsigned long ramrod_flags = 0;
9964
9965 /* First schedule a cleanup up of old configuration */
9966 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9967 if (rc < 0) {
9968 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9969 return rc;
9970 }
9971
9972 netdev_for_each_uc_addr(ha, dev) {
9973 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9974 BNX2X_UC_LIST_MAC, &ramrod_flags);
9975 if (rc < 0) {
9976 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9977 rc);
9978 return rc;
9979 }
9980 }
9981
9982 /* Execute the pending commands */
9983 __set_bit(RAMROD_CONT, &ramrod_flags);
9984 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9985 BNX2X_UC_LIST_MAC, &ramrod_flags);
9986 }
9987
9988 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9989 {
9990 struct net_device *dev = bp->dev;
9991 struct bnx2x_mcast_ramrod_params rparam = {0};
9992 int rc = 0;
9993
9994 rparam.mcast_obj = &bp->mcast_obj;
9995
9996 /* first, clear all configured multicast MACs */
9997 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9998 if (rc < 0) {
9999 BNX2X_ERR("Failed to clear multicast "
10000 "configuration: %d\n", rc);
10001 return rc;
10002 }
10003
10004 /* then, configure a new MACs list */
10005 if (netdev_mc_count(dev)) {
10006 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10007 if (rc) {
10008 BNX2X_ERR("Failed to create multicast MACs "
10009 "list: %d\n", rc);
10010 return rc;
10011 }
10012
10013 /* Now add the new MACs */
10014 rc = bnx2x_config_mcast(bp, &rparam,
10015 BNX2X_MCAST_CMD_ADD);
10016 if (rc < 0)
10017 BNX2X_ERR("Failed to set a new multicast "
10018 "configuration: %d\n", rc);
10019
10020 bnx2x_free_mcast_macs_list(&rparam);
10021 }
10022
10023 return rc;
10024 }
10025
10026
10027 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10028 void bnx2x_set_rx_mode(struct net_device *dev)
10029 {
10030 struct bnx2x *bp = netdev_priv(dev);
10031 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10032
10033 if (bp->state != BNX2X_STATE_OPEN) {
10034 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10035 return;
10036 }
10037
10038 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10039
10040 if (dev->flags & IFF_PROMISC)
10041 rx_mode = BNX2X_RX_MODE_PROMISC;
10042 else if ((dev->flags & IFF_ALLMULTI) ||
10043 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10044 CHIP_IS_E1(bp)))
10045 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10046 else {
10047 /* some multicasts */
10048 if (bnx2x_set_mc_list(bp) < 0)
10049 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10050
10051 if (bnx2x_set_uc_list(bp) < 0)
10052 rx_mode = BNX2X_RX_MODE_PROMISC;
10053 }
10054
10055 bp->rx_mode = rx_mode;
10056
10057 /* Schedule the rx_mode command */
10058 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10059 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10060 return;
10061 }
10062
10063 bnx2x_set_storm_rx_mode(bp);
10064 }
10065
10066 /* called with rtnl_lock */
10067 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10068 int devad, u16 addr)
10069 {
10070 struct bnx2x *bp = netdev_priv(netdev);
10071 u16 value;
10072 int rc;
10073
10074 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10075 prtad, devad, addr);
10076
10077 /* The HW expects different devad if CL22 is used */
10078 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10079
10080 bnx2x_acquire_phy_lock(bp);
10081 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10082 bnx2x_release_phy_lock(bp);
10083 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10084
10085 if (!rc)
10086 rc = value;
10087 return rc;
10088 }
10089
10090 /* called with rtnl_lock */
10091 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10092 u16 addr, u16 value)
10093 {
10094 struct bnx2x *bp = netdev_priv(netdev);
10095 int rc;
10096
10097 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10098 " value 0x%x\n", prtad, devad, addr, value);
10099
10100 /* The HW expects different devad if CL22 is used */
10101 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10102
10103 bnx2x_acquire_phy_lock(bp);
10104 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10105 bnx2x_release_phy_lock(bp);
10106 return rc;
10107 }
10108
10109 /* called with rtnl_lock */
10110 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10111 {
10112 struct bnx2x *bp = netdev_priv(dev);
10113 struct mii_ioctl_data *mdio = if_mii(ifr);
10114
10115 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10116 mdio->phy_id, mdio->reg_num, mdio->val_in);
10117
10118 if (!netif_running(dev))
10119 return -EAGAIN;
10120
10121 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10122 }
10123
10124 #ifdef CONFIG_NET_POLL_CONTROLLER
10125 static void poll_bnx2x(struct net_device *dev)
10126 {
10127 struct bnx2x *bp = netdev_priv(dev);
10128
10129 disable_irq(bp->pdev->irq);
10130 bnx2x_interrupt(bp->pdev->irq, dev);
10131 enable_irq(bp->pdev->irq);
10132 }
10133 #endif
10134
10135 static const struct net_device_ops bnx2x_netdev_ops = {
10136 .ndo_open = bnx2x_open,
10137 .ndo_stop = bnx2x_close,
10138 .ndo_start_xmit = bnx2x_start_xmit,
10139 .ndo_select_queue = bnx2x_select_queue,
10140 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10141 .ndo_set_mac_address = bnx2x_change_mac_addr,
10142 .ndo_validate_addr = eth_validate_addr,
10143 .ndo_do_ioctl = bnx2x_ioctl,
10144 .ndo_change_mtu = bnx2x_change_mtu,
10145 .ndo_fix_features = bnx2x_fix_features,
10146 .ndo_set_features = bnx2x_set_features,
10147 .ndo_tx_timeout = bnx2x_tx_timeout,
10148 #ifdef CONFIG_NET_POLL_CONTROLLER
10149 .ndo_poll_controller = poll_bnx2x,
10150 #endif
10151 .ndo_setup_tc = bnx2x_setup_tc,
10152
10153 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10154 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10155 #endif
10156 };
10157
10158 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10159 {
10160 struct device *dev = &bp->pdev->dev;
10161
10162 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10163 bp->flags |= USING_DAC_FLAG;
10164 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10165 dev_err(dev, "dma_set_coherent_mask failed, "
10166 "aborting\n");
10167 return -EIO;
10168 }
10169 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10170 dev_err(dev, "System does not support DMA, aborting\n");
10171 return -EIO;
10172 }
10173
10174 return 0;
10175 }
10176
10177 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10178 struct net_device *dev,
10179 unsigned long board_type)
10180 {
10181 struct bnx2x *bp;
10182 int rc;
10183
10184 SET_NETDEV_DEV(dev, &pdev->dev);
10185 bp = netdev_priv(dev);
10186
10187 bp->dev = dev;
10188 bp->pdev = pdev;
10189 bp->flags = 0;
10190 bp->pf_num = PCI_FUNC(pdev->devfn);
10191
10192 rc = pci_enable_device(pdev);
10193 if (rc) {
10194 dev_err(&bp->pdev->dev,
10195 "Cannot enable PCI device, aborting\n");
10196 goto err_out;
10197 }
10198
10199 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10200 dev_err(&bp->pdev->dev,
10201 "Cannot find PCI device base address, aborting\n");
10202 rc = -ENODEV;
10203 goto err_out_disable;
10204 }
10205
10206 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10207 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10208 " base address, aborting\n");
10209 rc = -ENODEV;
10210 goto err_out_disable;
10211 }
10212
10213 if (atomic_read(&pdev->enable_cnt) == 1) {
10214 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10215 if (rc) {
10216 dev_err(&bp->pdev->dev,
10217 "Cannot obtain PCI resources, aborting\n");
10218 goto err_out_disable;
10219 }
10220
10221 pci_set_master(pdev);
10222 pci_save_state(pdev);
10223 }
10224
10225 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10226 if (bp->pm_cap == 0) {
10227 dev_err(&bp->pdev->dev,
10228 "Cannot find power management capability, aborting\n");
10229 rc = -EIO;
10230 goto err_out_release;
10231 }
10232
10233 if (!pci_is_pcie(pdev)) {
10234 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10235 rc = -EIO;
10236 goto err_out_release;
10237 }
10238
10239 rc = bnx2x_set_coherency_mask(bp);
10240 if (rc)
10241 goto err_out_release;
10242
10243 dev->mem_start = pci_resource_start(pdev, 0);
10244 dev->base_addr = dev->mem_start;
10245 dev->mem_end = pci_resource_end(pdev, 0);
10246
10247 dev->irq = pdev->irq;
10248
10249 bp->regview = pci_ioremap_bar(pdev, 0);
10250 if (!bp->regview) {
10251 dev_err(&bp->pdev->dev,
10252 "Cannot map register space, aborting\n");
10253 rc = -ENOMEM;
10254 goto err_out_release;
10255 }
10256
10257 bnx2x_set_power_state(bp, PCI_D0);
10258
10259 /* clean indirect addresses */
10260 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10261 PCICFG_VENDOR_ID_OFFSET);
10262 /* Clean the following indirect addresses for all functions since it
10263 * is not used by the driver.
10264 */
10265 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10266 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10267 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10268 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10269 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10270 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10271 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10272 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10273
10274 /*
10275 * Enable internal target-read (in case we are probed after PF FLR).
10276 * Must be done prior to any BAR read access. Only for 57712 and up
10277 */
10278 if (board_type != BCM57710 &&
10279 board_type != BCM57711 &&
10280 board_type != BCM57711E)
10281 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10282
10283 /* Reset the load counter */
10284 bnx2x_clear_load_cnt(bp);
10285
10286 dev->watchdog_timeo = TX_TIMEOUT;
10287
10288 dev->netdev_ops = &bnx2x_netdev_ops;
10289 bnx2x_set_ethtool_ops(dev);
10290
10291 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10292 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10293 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10294
10295 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10296 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10297
10298 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10299 if (bp->flags & USING_DAC_FLAG)
10300 dev->features |= NETIF_F_HIGHDMA;
10301
10302 /* Add Loopback capability to the device */
10303 dev->hw_features |= NETIF_F_LOOPBACK;
10304
10305 #ifdef BCM_DCBNL
10306 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10307 #endif
10308
10309 /* get_port_hwinfo() will set prtad and mmds properly */
10310 bp->mdio.prtad = MDIO_PRTAD_NONE;
10311 bp->mdio.mmds = 0;
10312 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10313 bp->mdio.dev = dev;
10314 bp->mdio.mdio_read = bnx2x_mdio_read;
10315 bp->mdio.mdio_write = bnx2x_mdio_write;
10316
10317 return 0;
10318
10319 err_out_release:
10320 if (atomic_read(&pdev->enable_cnt) == 1)
10321 pci_release_regions(pdev);
10322
10323 err_out_disable:
10324 pci_disable_device(pdev);
10325 pci_set_drvdata(pdev, NULL);
10326
10327 err_out:
10328 return rc;
10329 }
10330
10331 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10332 int *width, int *speed)
10333 {
10334 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10335
10336 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10337
10338 /* return value of 1=2.5GHz 2=5GHz */
10339 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10340 }
10341
10342 static int bnx2x_check_firmware(struct bnx2x *bp)
10343 {
10344 const struct firmware *firmware = bp->firmware;
10345 struct bnx2x_fw_file_hdr *fw_hdr;
10346 struct bnx2x_fw_file_section *sections;
10347 u32 offset, len, num_ops;
10348 u16 *ops_offsets;
10349 int i;
10350 const u8 *fw_ver;
10351
10352 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10353 return -EINVAL;
10354
10355 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10356 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10357
10358 /* Make sure none of the offsets and sizes make us read beyond
10359 * the end of the firmware data */
10360 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10361 offset = be32_to_cpu(sections[i].offset);
10362 len = be32_to_cpu(sections[i].len);
10363 if (offset + len > firmware->size) {
10364 dev_err(&bp->pdev->dev,
10365 "Section %d length is out of bounds\n", i);
10366 return -EINVAL;
10367 }
10368 }
10369
10370 /* Likewise for the init_ops offsets */
10371 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10372 ops_offsets = (u16 *)(firmware->data + offset);
10373 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10374
10375 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10376 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10377 dev_err(&bp->pdev->dev,
10378 "Section offset %d is out of bounds\n", i);
10379 return -EINVAL;
10380 }
10381 }
10382
10383 /* Check FW version */
10384 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10385 fw_ver = firmware->data + offset;
10386 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10387 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10388 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10389 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10390 dev_err(&bp->pdev->dev,
10391 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10392 fw_ver[0], fw_ver[1], fw_ver[2],
10393 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10394 BCM_5710_FW_MINOR_VERSION,
10395 BCM_5710_FW_REVISION_VERSION,
10396 BCM_5710_FW_ENGINEERING_VERSION);
10397 return -EINVAL;
10398 }
10399
10400 return 0;
10401 }
10402
10403 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10404 {
10405 const __be32 *source = (const __be32 *)_source;
10406 u32 *target = (u32 *)_target;
10407 u32 i;
10408
10409 for (i = 0; i < n/4; i++)
10410 target[i] = be32_to_cpu(source[i]);
10411 }
10412
10413 /*
10414 Ops array is stored in the following format:
10415 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10416 */
10417 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10418 {
10419 const __be32 *source = (const __be32 *)_source;
10420 struct raw_op *target = (struct raw_op *)_target;
10421 u32 i, j, tmp;
10422
10423 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10424 tmp = be32_to_cpu(source[j]);
10425 target[i].op = (tmp >> 24) & 0xff;
10426 target[i].offset = tmp & 0xffffff;
10427 target[i].raw_data = be32_to_cpu(source[j + 1]);
10428 }
10429 }
10430
10431 /**
10432 * IRO array is stored in the following format:
10433 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10434 */
10435 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10436 {
10437 const __be32 *source = (const __be32 *)_source;
10438 struct iro *target = (struct iro *)_target;
10439 u32 i, j, tmp;
10440
10441 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10442 target[i].base = be32_to_cpu(source[j]);
10443 j++;
10444 tmp = be32_to_cpu(source[j]);
10445 target[i].m1 = (tmp >> 16) & 0xffff;
10446 target[i].m2 = tmp & 0xffff;
10447 j++;
10448 tmp = be32_to_cpu(source[j]);
10449 target[i].m3 = (tmp >> 16) & 0xffff;
10450 target[i].size = tmp & 0xffff;
10451 j++;
10452 }
10453 }
10454
10455 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10456 {
10457 const __be16 *source = (const __be16 *)_source;
10458 u16 *target = (u16 *)_target;
10459 u32 i;
10460
10461 for (i = 0; i < n/2; i++)
10462 target[i] = be16_to_cpu(source[i]);
10463 }
10464
10465 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10466 do { \
10467 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10468 bp->arr = kmalloc(len, GFP_KERNEL); \
10469 if (!bp->arr) { \
10470 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10471 goto lbl; \
10472 } \
10473 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10474 (u8 *)bp->arr, len); \
10475 } while (0)
10476
10477 int bnx2x_init_firmware(struct bnx2x *bp)
10478 {
10479 const char *fw_file_name;
10480 struct bnx2x_fw_file_hdr *fw_hdr;
10481 int rc;
10482
10483 if (CHIP_IS_E1(bp))
10484 fw_file_name = FW_FILE_NAME_E1;
10485 else if (CHIP_IS_E1H(bp))
10486 fw_file_name = FW_FILE_NAME_E1H;
10487 else if (!CHIP_IS_E1x(bp))
10488 fw_file_name = FW_FILE_NAME_E2;
10489 else {
10490 BNX2X_ERR("Unsupported chip revision\n");
10491 return -EINVAL;
10492 }
10493
10494 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10495
10496 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10497 if (rc) {
10498 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10499 goto request_firmware_exit;
10500 }
10501
10502 rc = bnx2x_check_firmware(bp);
10503 if (rc) {
10504 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10505 goto request_firmware_exit;
10506 }
10507
10508 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10509
10510 /* Initialize the pointers to the init arrays */
10511 /* Blob */
10512 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10513
10514 /* Opcodes */
10515 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10516
10517 /* Offsets */
10518 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10519 be16_to_cpu_n);
10520
10521 /* STORMs firmware */
10522 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10523 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10524 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10525 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10526 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10527 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10528 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10529 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10530 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10531 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10532 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10533 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10534 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10535 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10536 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10537 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10538 /* IRO */
10539 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10540
10541 return 0;
10542
10543 iro_alloc_err:
10544 kfree(bp->init_ops_offsets);
10545 init_offsets_alloc_err:
10546 kfree(bp->init_ops);
10547 init_ops_alloc_err:
10548 kfree(bp->init_data);
10549 request_firmware_exit:
10550 release_firmware(bp->firmware);
10551
10552 return rc;
10553 }
10554
10555 static void bnx2x_release_firmware(struct bnx2x *bp)
10556 {
10557 kfree(bp->init_ops_offsets);
10558 kfree(bp->init_ops);
10559 kfree(bp->init_data);
10560 release_firmware(bp->firmware);
10561 }
10562
10563
10564 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10565 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10566 .init_hw_cmn = bnx2x_init_hw_common,
10567 .init_hw_port = bnx2x_init_hw_port,
10568 .init_hw_func = bnx2x_init_hw_func,
10569
10570 .reset_hw_cmn = bnx2x_reset_common,
10571 .reset_hw_port = bnx2x_reset_port,
10572 .reset_hw_func = bnx2x_reset_func,
10573
10574 .gunzip_init = bnx2x_gunzip_init,
10575 .gunzip_end = bnx2x_gunzip_end,
10576
10577 .init_fw = bnx2x_init_firmware,
10578 .release_fw = bnx2x_release_firmware,
10579 };
10580
10581 void bnx2x__init_func_obj(struct bnx2x *bp)
10582 {
10583 /* Prepare DMAE related driver resources */
10584 bnx2x_setup_dmae(bp);
10585
10586 bnx2x_init_func_obj(bp, &bp->func_obj,
10587 bnx2x_sp(bp, func_rdata),
10588 bnx2x_sp_mapping(bp, func_rdata),
10589 &bnx2x_func_sp_drv);
10590 }
10591
10592 /* must be called after sriov-enable */
10593 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10594 {
10595 int cid_count = BNX2X_L2_CID_COUNT(bp);
10596
10597 #ifdef BCM_CNIC
10598 cid_count += CNIC_CID_MAX;
10599 #endif
10600 return roundup(cid_count, QM_CID_ROUND);
10601 }
10602
10603 /**
10604 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10605 *
10606 * @dev: pci device
10607 *
10608 */
10609 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10610 {
10611 int pos;
10612 u16 control;
10613
10614 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10615
10616 /*
10617 * If MSI-X is not supported - return number of SBs needed to support
10618 * one fast path queue: one FP queue + SB for CNIC
10619 */
10620 if (!pos)
10621 return 1 + CNIC_PRESENT;
10622
10623 /*
10624 * The value in the PCI configuration space is the index of the last
10625 * entry, namely one less than the actual size of the table, which is
10626 * exactly what we want to return from this function: number of all SBs
10627 * without the default SB.
10628 */
10629 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10630 return control & PCI_MSIX_FLAGS_QSIZE;
10631 }
10632
10633 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10634 const struct pci_device_id *ent)
10635 {
10636 struct net_device *dev = NULL;
10637 struct bnx2x *bp;
10638 int pcie_width, pcie_speed;
10639 int rc, max_non_def_sbs;
10640 int rx_count, tx_count, rss_count;
10641 /*
10642 * An estimated maximum supported CoS number according to the chip
10643 * version.
10644 * We will try to roughly estimate the maximum number of CoSes this chip
10645 * may support in order to minimize the memory allocated for Tx
10646 * netdev_queue's. This number will be accurately calculated during the
10647 * initialization of bp->max_cos based on the chip versions AND chip
10648 * revision in the bnx2x_init_bp().
10649 */
10650 u8 max_cos_est = 0;
10651
10652 switch (ent->driver_data) {
10653 case BCM57710:
10654 case BCM57711:
10655 case BCM57711E:
10656 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10657 break;
10658
10659 case BCM57712:
10660 case BCM57712_MF:
10661 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10662 break;
10663
10664 case BCM57800:
10665 case BCM57800_MF:
10666 case BCM57810:
10667 case BCM57810_MF:
10668 case BCM57840:
10669 case BCM57840_MF:
10670 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10671 break;
10672
10673 default:
10674 pr_err("Unknown board_type (%ld), aborting\n",
10675 ent->driver_data);
10676 return -ENODEV;
10677 }
10678
10679 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10680
10681 /* !!! FIXME !!!
10682 * Do not allow the maximum SB count to grow above 16
10683 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10684 * We will use the FP_SB_MAX_E1x macro for this matter.
10685 */
10686 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10687
10688 WARN_ON(!max_non_def_sbs);
10689
10690 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10691 rss_count = max_non_def_sbs - CNIC_PRESENT;
10692
10693 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10694 rx_count = rss_count + FCOE_PRESENT;
10695
10696 /*
10697 * Maximum number of netdev Tx queues:
10698 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10699 */
10700 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10701
10702 /* dev zeroed in init_etherdev */
10703 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10704 if (!dev) {
10705 dev_err(&pdev->dev, "Cannot allocate net device\n");
10706 return -ENOMEM;
10707 }
10708
10709 bp = netdev_priv(dev);
10710
10711 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10712 tx_count, rx_count);
10713
10714 bp->igu_sb_cnt = max_non_def_sbs;
10715 bp->msg_enable = debug;
10716 pci_set_drvdata(pdev, dev);
10717
10718 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10719 if (rc < 0) {
10720 free_netdev(dev);
10721 return rc;
10722 }
10723
10724 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
10725
10726 rc = bnx2x_init_bp(bp);
10727 if (rc)
10728 goto init_one_exit;
10729
10730 /*
10731 * Map doorbels here as we need the real value of bp->max_cos which
10732 * is initialized in bnx2x_init_bp().
10733 */
10734 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10735 min_t(u64, BNX2X_DB_SIZE(bp),
10736 pci_resource_len(pdev, 2)));
10737 if (!bp->doorbells) {
10738 dev_err(&bp->pdev->dev,
10739 "Cannot map doorbell space, aborting\n");
10740 rc = -ENOMEM;
10741 goto init_one_exit;
10742 }
10743
10744 /* calc qm_cid_count */
10745 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10746
10747 #ifdef BCM_CNIC
10748 /* disable FCOE L2 queue for E1x and E3*/
10749 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10750 bp->flags |= NO_FCOE_FLAG;
10751
10752 #endif
10753
10754 /* Configure interrupt mode: try to enable MSI-X/MSI if
10755 * needed, set bp->num_queues appropriately.
10756 */
10757 bnx2x_set_int_mode(bp);
10758
10759 /* Add all NAPI objects */
10760 bnx2x_add_all_napi(bp);
10761
10762 rc = register_netdev(dev);
10763 if (rc) {
10764 dev_err(&pdev->dev, "Cannot register net device\n");
10765 goto init_one_exit;
10766 }
10767
10768 #ifdef BCM_CNIC
10769 if (!NO_FCOE(bp)) {
10770 /* Add storage MAC address */
10771 rtnl_lock();
10772 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10773 rtnl_unlock();
10774 }
10775 #endif
10776
10777 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10778
10779 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10780 " IRQ %d, ", board_info[ent->driver_data].name,
10781 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10782 pcie_width,
10783 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10784 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10785 "5GHz (Gen2)" : "2.5GHz",
10786 dev->base_addr, bp->pdev->irq);
10787 pr_cont("node addr %pM\n", dev->dev_addr);
10788
10789 return 0;
10790
10791 init_one_exit:
10792 if (bp->regview)
10793 iounmap(bp->regview);
10794
10795 if (bp->doorbells)
10796 iounmap(bp->doorbells);
10797
10798 free_netdev(dev);
10799
10800 if (atomic_read(&pdev->enable_cnt) == 1)
10801 pci_release_regions(pdev);
10802
10803 pci_disable_device(pdev);
10804 pci_set_drvdata(pdev, NULL);
10805
10806 return rc;
10807 }
10808
10809 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10810 {
10811 struct net_device *dev = pci_get_drvdata(pdev);
10812 struct bnx2x *bp;
10813
10814 if (!dev) {
10815 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10816 return;
10817 }
10818 bp = netdev_priv(dev);
10819
10820 #ifdef BCM_CNIC
10821 /* Delete storage MAC address */
10822 if (!NO_FCOE(bp)) {
10823 rtnl_lock();
10824 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10825 rtnl_unlock();
10826 }
10827 #endif
10828
10829 #ifdef BCM_DCBNL
10830 /* Delete app tlvs from dcbnl */
10831 bnx2x_dcbnl_update_applist(bp, true);
10832 #endif
10833
10834 unregister_netdev(dev);
10835
10836 /* Delete all NAPI objects */
10837 bnx2x_del_all_napi(bp);
10838
10839 /* Power on: we can't let PCI layer write to us while we are in D3 */
10840 bnx2x_set_power_state(bp, PCI_D0);
10841
10842 /* Disable MSI/MSI-X */
10843 bnx2x_disable_msi(bp);
10844
10845 /* Power off */
10846 bnx2x_set_power_state(bp, PCI_D3hot);
10847
10848 /* Make sure RESET task is not scheduled before continuing */
10849 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10850
10851 if (bp->regview)
10852 iounmap(bp->regview);
10853
10854 if (bp->doorbells)
10855 iounmap(bp->doorbells);
10856
10857 bnx2x_free_mem_bp(bp);
10858
10859 free_netdev(dev);
10860
10861 if (atomic_read(&pdev->enable_cnt) == 1)
10862 pci_release_regions(pdev);
10863
10864 pci_disable_device(pdev);
10865 pci_set_drvdata(pdev, NULL);
10866 }
10867
10868 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10869 {
10870 int i;
10871
10872 bp->state = BNX2X_STATE_ERROR;
10873
10874 bp->rx_mode = BNX2X_RX_MODE_NONE;
10875
10876 #ifdef BCM_CNIC
10877 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10878 #endif
10879 /* Stop Tx */
10880 bnx2x_tx_disable(bp);
10881
10882 bnx2x_netif_stop(bp, 0);
10883
10884 del_timer_sync(&bp->timer);
10885
10886 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10887
10888 /* Release IRQs */
10889 bnx2x_free_irq(bp);
10890
10891 /* Free SKBs, SGEs, TPA pool and driver internals */
10892 bnx2x_free_skbs(bp);
10893
10894 for_each_rx_queue(bp, i)
10895 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10896
10897 bnx2x_free_mem(bp);
10898
10899 bp->state = BNX2X_STATE_CLOSED;
10900
10901 netif_carrier_off(bp->dev);
10902
10903 return 0;
10904 }
10905
10906 static void bnx2x_eeh_recover(struct bnx2x *bp)
10907 {
10908 u32 val;
10909
10910 mutex_init(&bp->port.phy_mutex);
10911
10912 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10913 bp->link_params.shmem_base = bp->common.shmem_base;
10914 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10915
10916 if (!bp->common.shmem_base ||
10917 (bp->common.shmem_base < 0xA0000) ||
10918 (bp->common.shmem_base >= 0xC0000)) {
10919 BNX2X_DEV_INFO("MCP not active\n");
10920 bp->flags |= NO_MCP_FLAG;
10921 return;
10922 }
10923
10924 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10925 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10926 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10927 BNX2X_ERR("BAD MCP validity signature\n");
10928
10929 if (!BP_NOMCP(bp)) {
10930 bp->fw_seq =
10931 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10932 DRV_MSG_SEQ_NUMBER_MASK);
10933 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10934 }
10935 }
10936
10937 /**
10938 * bnx2x_io_error_detected - called when PCI error is detected
10939 * @pdev: Pointer to PCI device
10940 * @state: The current pci connection state
10941 *
10942 * This function is called after a PCI bus error affecting
10943 * this device has been detected.
10944 */
10945 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10946 pci_channel_state_t state)
10947 {
10948 struct net_device *dev = pci_get_drvdata(pdev);
10949 struct bnx2x *bp = netdev_priv(dev);
10950
10951 rtnl_lock();
10952
10953 netif_device_detach(dev);
10954
10955 if (state == pci_channel_io_perm_failure) {
10956 rtnl_unlock();
10957 return PCI_ERS_RESULT_DISCONNECT;
10958 }
10959
10960 if (netif_running(dev))
10961 bnx2x_eeh_nic_unload(bp);
10962
10963 pci_disable_device(pdev);
10964
10965 rtnl_unlock();
10966
10967 /* Request a slot reset */
10968 return PCI_ERS_RESULT_NEED_RESET;
10969 }
10970
10971 /**
10972 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10973 * @pdev: Pointer to PCI device
10974 *
10975 * Restart the card from scratch, as if from a cold-boot.
10976 */
10977 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10978 {
10979 struct net_device *dev = pci_get_drvdata(pdev);
10980 struct bnx2x *bp = netdev_priv(dev);
10981
10982 rtnl_lock();
10983
10984 if (pci_enable_device(pdev)) {
10985 dev_err(&pdev->dev,
10986 "Cannot re-enable PCI device after reset\n");
10987 rtnl_unlock();
10988 return PCI_ERS_RESULT_DISCONNECT;
10989 }
10990
10991 pci_set_master(pdev);
10992 pci_restore_state(pdev);
10993
10994 if (netif_running(dev))
10995 bnx2x_set_power_state(bp, PCI_D0);
10996
10997 rtnl_unlock();
10998
10999 return PCI_ERS_RESULT_RECOVERED;
11000 }
11001
11002 /**
11003 * bnx2x_io_resume - called when traffic can start flowing again
11004 * @pdev: Pointer to PCI device
11005 *
11006 * This callback is called when the error recovery driver tells us that
11007 * its OK to resume normal operation.
11008 */
11009 static void bnx2x_io_resume(struct pci_dev *pdev)
11010 {
11011 struct net_device *dev = pci_get_drvdata(pdev);
11012 struct bnx2x *bp = netdev_priv(dev);
11013
11014 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11015 netdev_err(bp->dev, "Handling parity error recovery. "
11016 "Try again later\n");
11017 return;
11018 }
11019
11020 rtnl_lock();
11021
11022 bnx2x_eeh_recover(bp);
11023
11024 if (netif_running(dev))
11025 bnx2x_nic_load(bp, LOAD_NORMAL);
11026
11027 netif_device_attach(dev);
11028
11029 rtnl_unlock();
11030 }
11031
11032 static struct pci_error_handlers bnx2x_err_handler = {
11033 .error_detected = bnx2x_io_error_detected,
11034 .slot_reset = bnx2x_io_slot_reset,
11035 .resume = bnx2x_io_resume,
11036 };
11037
11038 static struct pci_driver bnx2x_pci_driver = {
11039 .name = DRV_MODULE_NAME,
11040 .id_table = bnx2x_pci_tbl,
11041 .probe = bnx2x_init_one,
11042 .remove = __devexit_p(bnx2x_remove_one),
11043 .suspend = bnx2x_suspend,
11044 .resume = bnx2x_resume,
11045 .err_handler = &bnx2x_err_handler,
11046 };
11047
11048 static int __init bnx2x_init(void)
11049 {
11050 int ret;
11051
11052 pr_info("%s", version);
11053
11054 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11055 if (bnx2x_wq == NULL) {
11056 pr_err("Cannot create workqueue\n");
11057 return -ENOMEM;
11058 }
11059
11060 ret = pci_register_driver(&bnx2x_pci_driver);
11061 if (ret) {
11062 pr_err("Cannot register driver\n");
11063 destroy_workqueue(bnx2x_wq);
11064 }
11065 return ret;
11066 }
11067
11068 static void __exit bnx2x_cleanup(void)
11069 {
11070 pci_unregister_driver(&bnx2x_pci_driver);
11071
11072 destroy_workqueue(bnx2x_wq);
11073 }
11074
11075 void bnx2x_notify_link_changed(struct bnx2x *bp)
11076 {
11077 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11078 }
11079
11080 module_init(bnx2x_init);
11081 module_exit(bnx2x_cleanup);
11082
11083 #ifdef BCM_CNIC
11084 /**
11085 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11086 *
11087 * @bp: driver handle
11088 * @set: set or clear the CAM entry
11089 *
11090 * This function will wait until the ramdord completion returns.
11091 * Return 0 if success, -ENODEV if ramrod doesn't return.
11092 */
11093 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11094 {
11095 unsigned long ramrod_flags = 0;
11096
11097 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11098 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11099 &bp->iscsi_l2_mac_obj, true,
11100 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11101 }
11102
11103 /* count denotes the number of new completions we have seen */
11104 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11105 {
11106 struct eth_spe *spe;
11107
11108 #ifdef BNX2X_STOP_ON_ERROR
11109 if (unlikely(bp->panic))
11110 return;
11111 #endif
11112
11113 spin_lock_bh(&bp->spq_lock);
11114 BUG_ON(bp->cnic_spq_pending < count);
11115 bp->cnic_spq_pending -= count;
11116
11117
11118 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11119 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11120 & SPE_HDR_CONN_TYPE) >>
11121 SPE_HDR_CONN_TYPE_SHIFT;
11122 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11123 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11124
11125 /* Set validation for iSCSI L2 client before sending SETUP
11126 * ramrod
11127 */
11128 if (type == ETH_CONNECTION_TYPE) {
11129 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11130 bnx2x_set_ctx_validation(bp, &bp->context.
11131 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11132 BNX2X_ISCSI_ETH_CID);
11133 }
11134
11135 /*
11136 * There may be not more than 8 L2, not more than 8 L5 SPEs
11137 * and in the air. We also check that number of outstanding
11138 * COMMON ramrods is not more than the EQ and SPQ can
11139 * accommodate.
11140 */
11141 if (type == ETH_CONNECTION_TYPE) {
11142 if (!atomic_read(&bp->cq_spq_left))
11143 break;
11144 else
11145 atomic_dec(&bp->cq_spq_left);
11146 } else if (type == NONE_CONNECTION_TYPE) {
11147 if (!atomic_read(&bp->eq_spq_left))
11148 break;
11149 else
11150 atomic_dec(&bp->eq_spq_left);
11151 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11152 (type == FCOE_CONNECTION_TYPE)) {
11153 if (bp->cnic_spq_pending >=
11154 bp->cnic_eth_dev.max_kwqe_pending)
11155 break;
11156 else
11157 bp->cnic_spq_pending++;
11158 } else {
11159 BNX2X_ERR("Unknown SPE type: %d\n", type);
11160 bnx2x_panic();
11161 break;
11162 }
11163
11164 spe = bnx2x_sp_get_next(bp);
11165 *spe = *bp->cnic_kwq_cons;
11166
11167 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11168 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11169
11170 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11171 bp->cnic_kwq_cons = bp->cnic_kwq;
11172 else
11173 bp->cnic_kwq_cons++;
11174 }
11175 bnx2x_sp_prod_update(bp);
11176 spin_unlock_bh(&bp->spq_lock);
11177 }
11178
11179 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11180 struct kwqe_16 *kwqes[], u32 count)
11181 {
11182 struct bnx2x *bp = netdev_priv(dev);
11183 int i;
11184
11185 #ifdef BNX2X_STOP_ON_ERROR
11186 if (unlikely(bp->panic))
11187 return -EIO;
11188 #endif
11189
11190 spin_lock_bh(&bp->spq_lock);
11191
11192 for (i = 0; i < count; i++) {
11193 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11194
11195 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11196 break;
11197
11198 *bp->cnic_kwq_prod = *spe;
11199
11200 bp->cnic_kwq_pending++;
11201
11202 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11203 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11204 spe->data.update_data_addr.hi,
11205 spe->data.update_data_addr.lo,
11206 bp->cnic_kwq_pending);
11207
11208 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11209 bp->cnic_kwq_prod = bp->cnic_kwq;
11210 else
11211 bp->cnic_kwq_prod++;
11212 }
11213
11214 spin_unlock_bh(&bp->spq_lock);
11215
11216 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11217 bnx2x_cnic_sp_post(bp, 0);
11218
11219 return i;
11220 }
11221
11222 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11223 {
11224 struct cnic_ops *c_ops;
11225 int rc = 0;
11226
11227 mutex_lock(&bp->cnic_mutex);
11228 c_ops = rcu_dereference_protected(bp->cnic_ops,
11229 lockdep_is_held(&bp->cnic_mutex));
11230 if (c_ops)
11231 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11232 mutex_unlock(&bp->cnic_mutex);
11233
11234 return rc;
11235 }
11236
11237 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11238 {
11239 struct cnic_ops *c_ops;
11240 int rc = 0;
11241
11242 rcu_read_lock();
11243 c_ops = rcu_dereference(bp->cnic_ops);
11244 if (c_ops)
11245 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11246 rcu_read_unlock();
11247
11248 return rc;
11249 }
11250
11251 /*
11252 * for commands that have no data
11253 */
11254 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11255 {
11256 struct cnic_ctl_info ctl = {0};
11257
11258 ctl.cmd = cmd;
11259
11260 return bnx2x_cnic_ctl_send(bp, &ctl);
11261 }
11262
11263 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11264 {
11265 struct cnic_ctl_info ctl = {0};
11266
11267 /* first we tell CNIC and only then we count this as a completion */
11268 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11269 ctl.data.comp.cid = cid;
11270 ctl.data.comp.error = err;
11271
11272 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11273 bnx2x_cnic_sp_post(bp, 0);
11274 }
11275
11276
11277 /* Called with netif_addr_lock_bh() taken.
11278 * Sets an rx_mode config for an iSCSI ETH client.
11279 * Doesn't block.
11280 * Completion should be checked outside.
11281 */
11282 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11283 {
11284 unsigned long accept_flags = 0, ramrod_flags = 0;
11285 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11286 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11287
11288 if (start) {
11289 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11290 * because it's the only way for UIO Queue to accept
11291 * multicasts (in non-promiscuous mode only one Queue per
11292 * function will receive multicast packets (leading in our
11293 * case).
11294 */
11295 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11296 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11297 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11298 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11299
11300 /* Clear STOP_PENDING bit if START is requested */
11301 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11302
11303 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11304 } else
11305 /* Clear START_PENDING bit if STOP is requested */
11306 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11307
11308 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11309 set_bit(sched_state, &bp->sp_state);
11310 else {
11311 __set_bit(RAMROD_RX, &ramrod_flags);
11312 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11313 ramrod_flags);
11314 }
11315 }
11316
11317
11318 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11319 {
11320 struct bnx2x *bp = netdev_priv(dev);
11321 int rc = 0;
11322
11323 switch (ctl->cmd) {
11324 case DRV_CTL_CTXTBL_WR_CMD: {
11325 u32 index = ctl->data.io.offset;
11326 dma_addr_t addr = ctl->data.io.dma_addr;
11327
11328 bnx2x_ilt_wr(bp, index, addr);
11329 break;
11330 }
11331
11332 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11333 int count = ctl->data.credit.credit_count;
11334
11335 bnx2x_cnic_sp_post(bp, count);
11336 break;
11337 }
11338
11339 /* rtnl_lock is held. */
11340 case DRV_CTL_START_L2_CMD: {
11341 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11342 unsigned long sp_bits = 0;
11343
11344 /* Configure the iSCSI classification object */
11345 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11346 cp->iscsi_l2_client_id,
11347 cp->iscsi_l2_cid, BP_FUNC(bp),
11348 bnx2x_sp(bp, mac_rdata),
11349 bnx2x_sp_mapping(bp, mac_rdata),
11350 BNX2X_FILTER_MAC_PENDING,
11351 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11352 &bp->macs_pool);
11353
11354 /* Set iSCSI MAC address */
11355 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11356 if (rc)
11357 break;
11358
11359 mmiowb();
11360 barrier();
11361
11362 /* Start accepting on iSCSI L2 ring */
11363
11364 netif_addr_lock_bh(dev);
11365 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11366 netif_addr_unlock_bh(dev);
11367
11368 /* bits to wait on */
11369 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11370 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11371
11372 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11373 BNX2X_ERR("rx_mode completion timed out!\n");
11374
11375 break;
11376 }
11377
11378 /* rtnl_lock is held. */
11379 case DRV_CTL_STOP_L2_CMD: {
11380 unsigned long sp_bits = 0;
11381
11382 /* Stop accepting on iSCSI L2 ring */
11383 netif_addr_lock_bh(dev);
11384 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11385 netif_addr_unlock_bh(dev);
11386
11387 /* bits to wait on */
11388 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11389 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11390
11391 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11392 BNX2X_ERR("rx_mode completion timed out!\n");
11393
11394 mmiowb();
11395 barrier();
11396
11397 /* Unset iSCSI L2 MAC */
11398 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11399 BNX2X_ISCSI_ETH_MAC, true);
11400 break;
11401 }
11402 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11403 int count = ctl->data.credit.credit_count;
11404
11405 smp_mb__before_atomic_inc();
11406 atomic_add(count, &bp->cq_spq_left);
11407 smp_mb__after_atomic_inc();
11408 break;
11409 }
11410
11411 default:
11412 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11413 rc = -EINVAL;
11414 }
11415
11416 return rc;
11417 }
11418
11419 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11420 {
11421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11422
11423 if (bp->flags & USING_MSIX_FLAG) {
11424 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11425 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11426 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11427 } else {
11428 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11429 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11430 }
11431 if (!CHIP_IS_E1x(bp))
11432 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11433 else
11434 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11435
11436 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11437 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11438 cp->irq_arr[1].status_blk = bp->def_status_blk;
11439 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11440 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11441
11442 cp->num_irq = 2;
11443 }
11444
11445 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11446 void *data)
11447 {
11448 struct bnx2x *bp = netdev_priv(dev);
11449 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11450
11451 if (ops == NULL)
11452 return -EINVAL;
11453
11454 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11455 if (!bp->cnic_kwq)
11456 return -ENOMEM;
11457
11458 bp->cnic_kwq_cons = bp->cnic_kwq;
11459 bp->cnic_kwq_prod = bp->cnic_kwq;
11460 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11461
11462 bp->cnic_spq_pending = 0;
11463 bp->cnic_kwq_pending = 0;
11464
11465 bp->cnic_data = data;
11466
11467 cp->num_irq = 0;
11468 cp->drv_state |= CNIC_DRV_STATE_REGD;
11469 cp->iro_arr = bp->iro_arr;
11470
11471 bnx2x_setup_cnic_irq_info(bp);
11472
11473 rcu_assign_pointer(bp->cnic_ops, ops);
11474
11475 return 0;
11476 }
11477
11478 static int bnx2x_unregister_cnic(struct net_device *dev)
11479 {
11480 struct bnx2x *bp = netdev_priv(dev);
11481 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11482
11483 mutex_lock(&bp->cnic_mutex);
11484 cp->drv_state = 0;
11485 rcu_assign_pointer(bp->cnic_ops, NULL);
11486 mutex_unlock(&bp->cnic_mutex);
11487 synchronize_rcu();
11488 kfree(bp->cnic_kwq);
11489 bp->cnic_kwq = NULL;
11490
11491 return 0;
11492 }
11493
11494 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11495 {
11496 struct bnx2x *bp = netdev_priv(dev);
11497 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11498
11499 /* If both iSCSI and FCoE are disabled - return NULL in
11500 * order to indicate CNIC that it should not try to work
11501 * with this device.
11502 */
11503 if (NO_ISCSI(bp) && NO_FCOE(bp))
11504 return NULL;
11505
11506 cp->drv_owner = THIS_MODULE;
11507 cp->chip_id = CHIP_ID(bp);
11508 cp->pdev = bp->pdev;
11509 cp->io_base = bp->regview;
11510 cp->io_base2 = bp->doorbells;
11511 cp->max_kwqe_pending = 8;
11512 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11513 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11514 bnx2x_cid_ilt_lines(bp);
11515 cp->ctx_tbl_len = CNIC_ILT_LINES;
11516 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11517 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11518 cp->drv_ctl = bnx2x_drv_ctl;
11519 cp->drv_register_cnic = bnx2x_register_cnic;
11520 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11521 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11522 cp->iscsi_l2_client_id =
11523 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11524 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11525
11526 if (NO_ISCSI_OOO(bp))
11527 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11528
11529 if (NO_ISCSI(bp))
11530 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11531
11532 if (NO_FCOE(bp))
11533 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11534
11535 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11536 "starting cid %d\n",
11537 cp->ctx_blk_size,
11538 cp->ctx_tbl_offset,
11539 cp->ctx_tbl_len,
11540 cp->starting_cid);
11541 return cp;
11542 }
11543 EXPORT_SYMBOL(bnx2x_cnic_probe);
11544
11545 #endif /* BCM_CNIC */
11546
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