2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if_vlan.h>
45 #include <linux/init.h>
46 #include <linux/log2.h>
47 #include <linux/mdio.h>
48 #include <linux/module.h>
49 #include <linux/moduleparam.h>
50 #include <linux/mutex.h>
51 #include <linux/netdevice.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/sched.h>
56 #include <linux/seq_file.h>
57 #include <linux/sockios.h>
58 #include <linux/vmalloc.h>
59 #include <linux/workqueue.h>
60 #include <net/neighbour.h>
61 #include <net/netevent.h>
62 #include <asm/uaccess.h>
70 #define DRV_VERSION "1.3.0-ko"
71 #define DRV_DESC "Chelsio T4 Network Driver"
74 * Max interrupt hold-off timer value in us. Queues fall back to this value
75 * under extreme memory pressure so it's largish to give the system time to
78 #define MAX_SGE_TIMERVAL 200U
82 * Virtual Function provisioning constants. We need two extra Ingress Queues
83 * with Interrupt capability to serve as the VF's Firmware Event Queue and
84 * Forwarded Interrupt Queue (when using MSI mode) -- neither will have Free
85 * Lists associated with them). For each Ethernet/Control Egress Queue and
86 * for each Free List, we need an Egress Context.
89 VFRES_NPORTS
= 1, /* # of "ports" per VF */
90 VFRES_NQSETS
= 2, /* # of "Queue Sets" per VF */
92 VFRES_NVI
= VFRES_NPORTS
, /* # of Virtual Interfaces */
93 VFRES_NETHCTRL
= VFRES_NQSETS
, /* # of EQs used for ETH or CTRL Qs */
94 VFRES_NIQFLINT
= VFRES_NQSETS
+2,/* # of ingress Qs/w Free List(s)/intr */
95 VFRES_NIQ
= 0, /* # of non-fl/int ingress queues */
96 VFRES_NEQ
= VFRES_NQSETS
*2, /* # of egress queues */
97 VFRES_TC
= 0, /* PCI-E traffic class */
98 VFRES_NEXACTF
= 16, /* # of exact MPS filters */
100 VFRES_R_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
|FW_CMD_CAP_PORT
,
101 VFRES_WX_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
,
105 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
106 * static and likely not to be useful in the long run. We really need to
107 * implement some form of persistent configuration which the firmware
110 static unsigned int pfvfres_pmask(struct adapter
*adapter
,
111 unsigned int pf
, unsigned int vf
)
113 unsigned int portn
, portvec
;
116 * Give PF's access to all of the ports.
119 return FW_PFVF_CMD_PMASK_MASK
;
122 * For VFs, we'll assign them access to the ports based purely on the
123 * PF. We assign active ports in order, wrapping around if there are
124 * fewer active ports than PFs: e.g. active port[pf % nports].
125 * Unfortunately the adapter's port_info structs haven't been
126 * initialized yet so we have to compute this.
128 if (adapter
->params
.nports
== 0)
131 portn
= pf
% adapter
->params
.nports
;
132 portvec
= adapter
->params
.portvec
;
135 * Isolate the lowest set bit in the port vector. If we're at
136 * the port number that we want, return that as the pmask.
137 * otherwise mask that bit out of the port vector and
138 * decrement our port number ...
140 unsigned int pmask
= portvec
^ (portvec
& (portvec
-1));
151 MEMWIN0_APERTURE
= 65536,
152 MEMWIN0_BASE
= 0x30000,
153 MEMWIN1_APERTURE
= 32768,
154 MEMWIN1_BASE
= 0x28000,
155 MEMWIN2_APERTURE
= 2048,
156 MEMWIN2_BASE
= 0x1b800,
160 MAX_TXQ_ENTRIES
= 16384,
161 MAX_CTRL_TXQ_ENTRIES
= 1024,
162 MAX_RSPQ_ENTRIES
= 16384,
163 MAX_RX_BUFFERS
= 16384,
164 MIN_TXQ_ENTRIES
= 32,
165 MIN_CTRL_TXQ_ENTRIES
= 32,
166 MIN_RSPQ_ENTRIES
= 128,
170 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
171 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
172 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
174 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
176 static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl
) = {
177 CH_DEVICE(0xa000, 0), /* PE10K */
178 CH_DEVICE(0x4001, -1),
179 CH_DEVICE(0x4002, -1),
180 CH_DEVICE(0x4003, -1),
181 CH_DEVICE(0x4004, -1),
182 CH_DEVICE(0x4005, -1),
183 CH_DEVICE(0x4006, -1),
184 CH_DEVICE(0x4007, -1),
185 CH_DEVICE(0x4008, -1),
186 CH_DEVICE(0x4009, -1),
187 CH_DEVICE(0x400a, -1),
188 CH_DEVICE(0x4401, 4),
189 CH_DEVICE(0x4402, 4),
190 CH_DEVICE(0x4403, 4),
191 CH_DEVICE(0x4404, 4),
192 CH_DEVICE(0x4405, 4),
193 CH_DEVICE(0x4406, 4),
194 CH_DEVICE(0x4407, 4),
195 CH_DEVICE(0x4408, 4),
196 CH_DEVICE(0x4409, 4),
197 CH_DEVICE(0x440a, 4),
201 #define FW_FNAME "cxgb4/t4fw.bin"
203 MODULE_DESCRIPTION(DRV_DESC
);
204 MODULE_AUTHOR("Chelsio Communications");
205 MODULE_LICENSE("Dual BSD/GPL");
206 MODULE_VERSION(DRV_VERSION
);
207 MODULE_DEVICE_TABLE(pci
, cxgb4_pci_tbl
);
208 MODULE_FIRMWARE(FW_FNAME
);
210 static int dflt_msg_enable
= DFLT_MSG_ENABLE
;
212 module_param(dflt_msg_enable
, int, 0644);
213 MODULE_PARM_DESC(dflt_msg_enable
, "Chelsio T4 default message enable bitmap");
216 * The driver uses the best interrupt scheme available on a platform in the
217 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
218 * of these schemes the driver may consider as follows:
220 * msi = 2: choose from among all three options
221 * msi = 1: only consider MSI and INTx interrupts
222 * msi = 0: force INTx interrupts
226 module_param(msi
, int, 0644);
227 MODULE_PARM_DESC(msi
, "whether to use INTx (0), MSI (1) or MSI-X (2)");
230 * Queue interrupt hold-off timer values. Queues default to the first of these
233 static unsigned int intr_holdoff
[SGE_NTIMERS
- 1] = { 5, 10, 20, 50, 100 };
235 module_param_array(intr_holdoff
, uint
, NULL
, 0644);
236 MODULE_PARM_DESC(intr_holdoff
, "values for queue interrupt hold-off timers "
237 "0..4 in microseconds");
239 static unsigned int intr_cnt
[SGE_NCOUNTERS
- 1] = { 4, 8, 16 };
241 module_param_array(intr_cnt
, uint
, NULL
, 0644);
242 MODULE_PARM_DESC(intr_cnt
,
243 "thresholds 1..3 for queue interrupt packet counters");
247 #ifdef CONFIG_PCI_IOV
248 module_param(vf_acls
, bool, 0644);
249 MODULE_PARM_DESC(vf_acls
, "if set enable virtualization L2 ACL enforcement");
251 static unsigned int num_vf
[4];
253 module_param_array(num_vf
, uint
, NULL
, 0644);
254 MODULE_PARM_DESC(num_vf
, "number of VFs for each of PFs 0-3");
257 static struct dentry
*cxgb4_debugfs_root
;
259 static LIST_HEAD(adapter_list
);
260 static DEFINE_MUTEX(uld_mutex
);
261 static struct cxgb4_uld_info ulds
[CXGB4_ULD_MAX
];
262 static const char *uld_str
[] = { "RDMA", "iSCSI" };
264 static void link_report(struct net_device
*dev
)
266 if (!netif_carrier_ok(dev
))
267 netdev_info(dev
, "link down\n");
269 static const char *fc
[] = { "no", "Rx", "Tx", "Tx/Rx" };
271 const char *s
= "10Mbps";
272 const struct port_info
*p
= netdev_priv(dev
);
274 switch (p
->link_cfg
.speed
) {
286 netdev_info(dev
, "link up, %s, full-duplex, %s PAUSE\n", s
,
291 void t4_os_link_changed(struct adapter
*adapter
, int port_id
, int link_stat
)
293 struct net_device
*dev
= adapter
->port
[port_id
];
295 /* Skip changes from disabled ports. */
296 if (netif_running(dev
) && link_stat
!= netif_carrier_ok(dev
)) {
298 netif_carrier_on(dev
);
300 netif_carrier_off(dev
);
306 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
)
308 static const char *mod_str
[] = {
309 NULL
, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
312 const struct net_device
*dev
= adap
->port
[port_id
];
313 const struct port_info
*pi
= netdev_priv(dev
);
315 if (pi
->mod_type
== FW_PORT_MOD_TYPE_NONE
)
316 netdev_info(dev
, "port module unplugged\n");
317 else if (pi
->mod_type
< ARRAY_SIZE(mod_str
))
318 netdev_info(dev
, "%s module inserted\n", mod_str
[pi
->mod_type
]);
322 * Configure the exact and hash address filters to handle a port's multicast
323 * and secondary unicast MAC addresses.
325 static int set_addr_filters(const struct net_device
*dev
, bool sleep
)
333 const struct netdev_hw_addr
*ha
;
334 int uc_cnt
= netdev_uc_count(dev
);
335 int mc_cnt
= netdev_mc_count(dev
);
336 const struct port_info
*pi
= netdev_priv(dev
);
337 unsigned int mb
= pi
->adapter
->fn
;
339 /* first do the secondary unicast addresses */
340 netdev_for_each_uc_addr(ha
, dev
) {
341 addr
[naddr
++] = ha
->addr
;
342 if (--uc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
343 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
344 naddr
, addr
, filt_idx
, &uhash
, sleep
);
353 /* next set up the multicast addresses */
354 netdev_for_each_mc_addr(ha
, dev
) {
355 addr
[naddr
++] = ha
->addr
;
356 if (--mc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
357 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
358 naddr
, addr
, filt_idx
, &mhash
, sleep
);
367 return t4_set_addr_hash(pi
->adapter
, mb
, pi
->viid
, uhash
!= 0,
368 uhash
| mhash
, sleep
);
372 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
373 * If @mtu is -1 it is left unchanged.
375 static int set_rxmode(struct net_device
*dev
, int mtu
, bool sleep_ok
)
378 struct port_info
*pi
= netdev_priv(dev
);
380 ret
= set_addr_filters(dev
, sleep_ok
);
382 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, mtu
,
383 (dev
->flags
& IFF_PROMISC
) ? 1 : 0,
384 (dev
->flags
& IFF_ALLMULTI
) ? 1 : 0, 1, -1,
390 * link_start - enable a port
391 * @dev: the port to enable
393 * Performs the MAC and PHY actions needed to enable a port.
395 static int link_start(struct net_device
*dev
)
398 struct port_info
*pi
= netdev_priv(dev
);
399 unsigned int mb
= pi
->adapter
->fn
;
402 * We do not set address filters and promiscuity here, the stack does
403 * that step explicitly.
405 ret
= t4_set_rxmode(pi
->adapter
, mb
, pi
->viid
, dev
->mtu
, -1, -1, -1,
406 !!(dev
->features
& NETIF_F_HW_VLAN_RX
), true);
408 ret
= t4_change_mac(pi
->adapter
, mb
, pi
->viid
,
409 pi
->xact_addr_filt
, dev
->dev_addr
, true,
412 pi
->xact_addr_filt
= ret
;
417 ret
= t4_link_start(pi
->adapter
, mb
, pi
->tx_chan
,
420 ret
= t4_enable_vi(pi
->adapter
, mb
, pi
->viid
, true, true);
425 * Response queue handler for the FW event queue.
427 static int fwevtq_handler(struct sge_rspq
*q
, const __be64
*rsp
,
428 const struct pkt_gl
*gl
)
430 u8 opcode
= ((const struct rss_header
*)rsp
)->opcode
;
432 rsp
++; /* skip RSS header */
433 if (likely(opcode
== CPL_SGE_EGR_UPDATE
)) {
434 const struct cpl_sge_egr_update
*p
= (void *)rsp
;
435 unsigned int qid
= EGR_QID(ntohl(p
->opcode_qid
));
438 txq
= q
->adap
->sge
.egr_map
[qid
- q
->adap
->sge
.egr_start
];
440 if ((u8
*)txq
< (u8
*)q
->adap
->sge
.ofldtxq
) {
441 struct sge_eth_txq
*eq
;
443 eq
= container_of(txq
, struct sge_eth_txq
, q
);
444 netif_tx_wake_queue(eq
->txq
);
446 struct sge_ofld_txq
*oq
;
448 oq
= container_of(txq
, struct sge_ofld_txq
, q
);
449 tasklet_schedule(&oq
->qresume_tsk
);
451 } else if (opcode
== CPL_FW6_MSG
|| opcode
== CPL_FW4_MSG
) {
452 const struct cpl_fw6_msg
*p
= (void *)rsp
;
455 t4_handle_fw_rpl(q
->adap
, p
->data
);
456 } else if (opcode
== CPL_L2T_WRITE_RPL
) {
457 const struct cpl_l2t_write_rpl
*p
= (void *)rsp
;
459 do_l2t_write_rpl(q
->adap
, p
);
461 dev_err(q
->adap
->pdev_dev
,
462 "unexpected CPL %#x on FW event queue\n", opcode
);
467 * uldrx_handler - response queue handler for ULD queues
468 * @q: the response queue that received the packet
469 * @rsp: the response queue descriptor holding the offload message
470 * @gl: the gather list of packet fragments
472 * Deliver an ingress offload packet to a ULD. All processing is done by
473 * the ULD, we just maintain statistics.
475 static int uldrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
476 const struct pkt_gl
*gl
)
478 struct sge_ofld_rxq
*rxq
= container_of(q
, struct sge_ofld_rxq
, rspq
);
480 if (ulds
[q
->uld
].rx_handler(q
->adap
->uld_handle
[q
->uld
], rsp
, gl
)) {
486 else if (gl
== CXGB4_MSG_AN
)
493 static void disable_msi(struct adapter
*adapter
)
495 if (adapter
->flags
& USING_MSIX
) {
496 pci_disable_msix(adapter
->pdev
);
497 adapter
->flags
&= ~USING_MSIX
;
498 } else if (adapter
->flags
& USING_MSI
) {
499 pci_disable_msi(adapter
->pdev
);
500 adapter
->flags
&= ~USING_MSI
;
505 * Interrupt handler for non-data events used with MSI-X.
507 static irqreturn_t
t4_nondata_intr(int irq
, void *cookie
)
509 struct adapter
*adap
= cookie
;
511 u32 v
= t4_read_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
));
514 t4_write_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
), v
);
516 t4_slow_intr_handler(adap
);
521 * Name the MSI-X interrupts.
523 static void name_msix_vecs(struct adapter
*adap
)
525 int i
, j
, msi_idx
= 2, n
= sizeof(adap
->msix_info
[0].desc
);
527 /* non-data interrupts */
528 snprintf(adap
->msix_info
[0].desc
, n
, "%s", adap
->port
[0]->name
);
531 snprintf(adap
->msix_info
[1].desc
, n
, "%s-FWeventq",
532 adap
->port
[0]->name
);
534 /* Ethernet queues */
535 for_each_port(adap
, j
) {
536 struct net_device
*d
= adap
->port
[j
];
537 const struct port_info
*pi
= netdev_priv(d
);
539 for (i
= 0; i
< pi
->nqsets
; i
++, msi_idx
++)
540 snprintf(adap
->msix_info
[msi_idx
].desc
, n
, "%s-Rx%d",
545 for_each_ofldrxq(&adap
->sge
, i
)
546 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-ofld%d",
547 adap
->port
[0]->name
, i
);
549 for_each_rdmarxq(&adap
->sge
, i
)
550 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-rdma%d",
551 adap
->port
[0]->name
, i
);
554 static int request_msix_queue_irqs(struct adapter
*adap
)
556 struct sge
*s
= &adap
->sge
;
557 int err
, ethqidx
, ofldqidx
= 0, rdmaqidx
= 0, msi
= 2;
559 err
= request_irq(adap
->msix_info
[1].vec
, t4_sge_intr_msix
, 0,
560 adap
->msix_info
[1].desc
, &s
->fw_evtq
);
564 for_each_ethrxq(s
, ethqidx
) {
565 err
= request_irq(adap
->msix_info
[msi
].vec
, t4_sge_intr_msix
, 0,
566 adap
->msix_info
[msi
].desc
,
567 &s
->ethrxq
[ethqidx
].rspq
);
572 for_each_ofldrxq(s
, ofldqidx
) {
573 err
= request_irq(adap
->msix_info
[msi
].vec
, t4_sge_intr_msix
, 0,
574 adap
->msix_info
[msi
].desc
,
575 &s
->ofldrxq
[ofldqidx
].rspq
);
580 for_each_rdmarxq(s
, rdmaqidx
) {
581 err
= request_irq(adap
->msix_info
[msi
].vec
, t4_sge_intr_msix
, 0,
582 adap
->msix_info
[msi
].desc
,
583 &s
->rdmarxq
[rdmaqidx
].rspq
);
591 while (--rdmaqidx
>= 0)
592 free_irq(adap
->msix_info
[--msi
].vec
,
593 &s
->rdmarxq
[rdmaqidx
].rspq
);
594 while (--ofldqidx
>= 0)
595 free_irq(adap
->msix_info
[--msi
].vec
,
596 &s
->ofldrxq
[ofldqidx
].rspq
);
597 while (--ethqidx
>= 0)
598 free_irq(adap
->msix_info
[--msi
].vec
, &s
->ethrxq
[ethqidx
].rspq
);
599 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
603 static void free_msix_queue_irqs(struct adapter
*adap
)
606 struct sge
*s
= &adap
->sge
;
608 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
609 for_each_ethrxq(s
, i
)
610 free_irq(adap
->msix_info
[msi
++].vec
, &s
->ethrxq
[i
].rspq
);
611 for_each_ofldrxq(s
, i
)
612 free_irq(adap
->msix_info
[msi
++].vec
, &s
->ofldrxq
[i
].rspq
);
613 for_each_rdmarxq(s
, i
)
614 free_irq(adap
->msix_info
[msi
++].vec
, &s
->rdmarxq
[i
].rspq
);
618 * write_rss - write the RSS table for a given port
620 * @queues: array of queue indices for RSS
622 * Sets up the portion of the HW RSS table for the port's VI to distribute
623 * packets to the Rx queues in @queues.
625 static int write_rss(const struct port_info
*pi
, const u16
*queues
)
629 const struct sge_eth_rxq
*q
= &pi
->adapter
->sge
.ethrxq
[pi
->first_qset
];
631 rss
= kmalloc(pi
->rss_size
* sizeof(u16
), GFP_KERNEL
);
635 /* map the queue indices to queue ids */
636 for (i
= 0; i
< pi
->rss_size
; i
++, queues
++)
637 rss
[i
] = q
[*queues
].rspq
.abs_id
;
639 err
= t4_config_rss_range(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, 0,
640 pi
->rss_size
, rss
, pi
->rss_size
);
646 * setup_rss - configure RSS
649 * Sets up RSS for each port.
651 static int setup_rss(struct adapter
*adap
)
655 for_each_port(adap
, i
) {
656 const struct port_info
*pi
= adap2pinfo(adap
, i
);
658 err
= write_rss(pi
, pi
->rss
);
666 * Return the channel of the ingress queue with the given qid.
668 static unsigned int rxq_to_chan(const struct sge
*p
, unsigned int qid
)
670 qid
-= p
->ingr_start
;
671 return netdev2pinfo(p
->ingr_map
[qid
]->netdev
)->tx_chan
;
675 * Wait until all NAPI handlers are descheduled.
677 static void quiesce_rx(struct adapter
*adap
)
681 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
682 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
685 napi_disable(&q
->napi
);
690 * Enable NAPI scheduling and interrupt generation for all Rx queues.
692 static void enable_rx(struct adapter
*adap
)
696 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
697 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
702 napi_enable(&q
->napi
);
703 /* 0-increment GTS to start the timer and enable interrupts */
704 t4_write_reg(adap
, MYPF_REG(SGE_PF_GTS
),
705 SEINTARM(q
->intr_params
) |
706 INGRESSQID(q
->cntxt_id
));
711 * setup_sge_queues - configure SGE Tx/Rx/response queues
714 * Determines how many sets of SGE queues to use and initializes them.
715 * We support multiple queue sets per port if we have MSI-X, otherwise
716 * just one queue set per port.
718 static int setup_sge_queues(struct adapter
*adap
)
720 int err
, msi_idx
, i
, j
;
721 struct sge
*s
= &adap
->sge
;
723 bitmap_zero(s
->starving_fl
, MAX_EGRQ
);
724 bitmap_zero(s
->txq_maperr
, MAX_EGRQ
);
726 if (adap
->flags
& USING_MSIX
)
727 msi_idx
= 1; /* vector 0 is for non-queue interrupts */
729 err
= t4_sge_alloc_rxq(adap
, &s
->intrq
, false, adap
->port
[0], 0,
733 msi_idx
= -((int)s
->intrq
.abs_id
+ 1);
736 err
= t4_sge_alloc_rxq(adap
, &s
->fw_evtq
, true, adap
->port
[0],
737 msi_idx
, NULL
, fwevtq_handler
);
739 freeout
: t4_free_sge_resources(adap
);
743 for_each_port(adap
, i
) {
744 struct net_device
*dev
= adap
->port
[i
];
745 struct port_info
*pi
= netdev_priv(dev
);
746 struct sge_eth_rxq
*q
= &s
->ethrxq
[pi
->first_qset
];
747 struct sge_eth_txq
*t
= &s
->ethtxq
[pi
->first_qset
];
749 for (j
= 0; j
< pi
->nqsets
; j
++, q
++) {
752 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
,
758 memset(&q
->stats
, 0, sizeof(q
->stats
));
760 for (j
= 0; j
< pi
->nqsets
; j
++, t
++) {
761 err
= t4_sge_alloc_eth_txq(adap
, t
, dev
,
762 netdev_get_tx_queue(dev
, j
),
763 s
->fw_evtq
.cntxt_id
);
769 j
= s
->ofldqsets
/ adap
->params
.nports
; /* ofld queues per channel */
770 for_each_ofldrxq(s
, i
) {
771 struct sge_ofld_rxq
*q
= &s
->ofldrxq
[i
];
772 struct net_device
*dev
= adap
->port
[i
/ j
];
776 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
, msi_idx
,
777 &q
->fl
, uldrx_handler
);
780 memset(&q
->stats
, 0, sizeof(q
->stats
));
781 s
->ofld_rxq
[i
] = q
->rspq
.abs_id
;
782 err
= t4_sge_alloc_ofld_txq(adap
, &s
->ofldtxq
[i
], dev
,
783 s
->fw_evtq
.cntxt_id
);
788 for_each_rdmarxq(s
, i
) {
789 struct sge_ofld_rxq
*q
= &s
->rdmarxq
[i
];
793 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, adap
->port
[i
],
794 msi_idx
, &q
->fl
, uldrx_handler
);
797 memset(&q
->stats
, 0, sizeof(q
->stats
));
798 s
->rdma_rxq
[i
] = q
->rspq
.abs_id
;
801 for_each_port(adap
, i
) {
803 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
804 * have RDMA queues, and that's the right value.
806 err
= t4_sge_alloc_ctrl_txq(adap
, &s
->ctrlq
[i
], adap
->port
[i
],
808 s
->rdmarxq
[i
].rspq
.cntxt_id
);
813 t4_write_reg(adap
, MPS_TRC_RSS_CONTROL
,
814 RSSCONTROL(netdev2pinfo(adap
->port
[0])->tx_chan
) |
815 QUEUENUMBER(s
->ethrxq
[0].rspq
.abs_id
));
820 * Returns 0 if new FW was successfully loaded, a positive errno if a load was
821 * started but failed, and a negative errno if flash load couldn't start.
823 static int upgrade_fw(struct adapter
*adap
)
827 const struct fw_hdr
*hdr
;
828 const struct firmware
*fw
;
829 struct device
*dev
= adap
->pdev_dev
;
831 ret
= request_firmware(&fw
, FW_FNAME
, dev
);
833 dev_err(dev
, "unable to load firmware image " FW_FNAME
834 ", error %d\n", ret
);
838 hdr
= (const struct fw_hdr
*)fw
->data
;
839 vers
= ntohl(hdr
->fw_ver
);
840 if (FW_HDR_FW_VER_MAJOR_GET(vers
) != FW_VERSION_MAJOR
) {
841 ret
= -EINVAL
; /* wrong major version, won't do */
846 * If the flash FW is unusable or we found something newer, load it.
848 if (FW_HDR_FW_VER_MAJOR_GET(adap
->params
.fw_vers
) != FW_VERSION_MAJOR
||
849 vers
> adap
->params
.fw_vers
) {
850 ret
= -t4_load_fw(adap
, fw
->data
, fw
->size
);
852 dev_info(dev
, "firmware upgraded to version %pI4 from "
853 FW_FNAME
"\n", &hdr
->fw_ver
);
855 out
: release_firmware(fw
);
860 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
861 * The allocated memory is cleared.
863 void *t4_alloc_mem(size_t size
)
865 void *p
= kzalloc(size
, GFP_KERNEL
);
873 * Free memory allocated through alloc_mem().
875 static void t4_free_mem(void *addr
)
877 if (is_vmalloc_addr(addr
))
883 static inline int is_offload(const struct adapter
*adap
)
885 return adap
->params
.offload
;
889 * Implementation of ethtool operations.
892 static u32
get_msglevel(struct net_device
*dev
)
894 return netdev2adap(dev
)->msg_enable
;
897 static void set_msglevel(struct net_device
*dev
, u32 val
)
899 netdev2adap(dev
)->msg_enable
= val
;
902 static char stats_strings
[][ETH_GSTRING_LEN
] = {
905 "TxBroadcastFrames ",
906 "TxMulticastFrames ",
914 "TxFrames512To1023 ",
915 "TxFrames1024To1518 ",
916 "TxFrames1519ToMax ",
931 "RxBroadcastFrames ",
932 "RxMulticastFrames ",
946 "RxFrames512To1023 ",
947 "RxFrames1024To1518 ",
948 "RxFrames1519ToMax ",
960 "RxBG0FramesDropped ",
961 "RxBG1FramesDropped ",
962 "RxBG2FramesDropped ",
963 "RxBG3FramesDropped ",
978 static int get_sset_count(struct net_device
*dev
, int sset
)
982 return ARRAY_SIZE(stats_strings
);
988 #define T4_REGMAP_SIZE (160 * 1024)
990 static int get_regs_len(struct net_device
*dev
)
992 return T4_REGMAP_SIZE
;
995 static int get_eeprom_len(struct net_device
*dev
)
1000 static void get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1002 struct adapter
*adapter
= netdev2adap(dev
);
1004 strcpy(info
->driver
, KBUILD_MODNAME
);
1005 strcpy(info
->version
, DRV_VERSION
);
1006 strcpy(info
->bus_info
, pci_name(adapter
->pdev
));
1008 if (!adapter
->params
.fw_vers
)
1009 strcpy(info
->fw_version
, "N/A");
1011 snprintf(info
->fw_version
, sizeof(info
->fw_version
),
1012 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1013 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.fw_vers
),
1014 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.fw_vers
),
1015 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.fw_vers
),
1016 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.fw_vers
),
1017 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.tp_vers
),
1018 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.tp_vers
),
1019 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.tp_vers
),
1020 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.tp_vers
));
1023 static void get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1025 if (stringset
== ETH_SS_STATS
)
1026 memcpy(data
, stats_strings
, sizeof(stats_strings
));
1030 * port stats maintained per queue of the port. They should be in the same
1031 * order as in stats_strings above.
1033 struct queue_port_stats
{
1043 static void collect_sge_port_stats(const struct adapter
*adap
,
1044 const struct port_info
*p
, struct queue_port_stats
*s
)
1047 const struct sge_eth_txq
*tx
= &adap
->sge
.ethtxq
[p
->first_qset
];
1048 const struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[p
->first_qset
];
1050 memset(s
, 0, sizeof(*s
));
1051 for (i
= 0; i
< p
->nqsets
; i
++, rx
++, tx
++) {
1053 s
->tx_csum
+= tx
->tx_cso
;
1054 s
->rx_csum
+= rx
->stats
.rx_cso
;
1055 s
->vlan_ex
+= rx
->stats
.vlan_ex
;
1056 s
->vlan_ins
+= tx
->vlan_ins
;
1057 s
->gro_pkts
+= rx
->stats
.lro_pkts
;
1058 s
->gro_merged
+= rx
->stats
.lro_merged
;
1062 static void get_stats(struct net_device
*dev
, struct ethtool_stats
*stats
,
1065 struct port_info
*pi
= netdev_priv(dev
);
1066 struct adapter
*adapter
= pi
->adapter
;
1068 t4_get_port_stats(adapter
, pi
->tx_chan
, (struct port_stats
*)data
);
1070 data
+= sizeof(struct port_stats
) / sizeof(u64
);
1071 collect_sge_port_stats(adapter
, pi
, (struct queue_port_stats
*)data
);
1075 * Return a version number to identify the type of adapter. The scheme is:
1076 * - bits 0..9: chip version
1077 * - bits 10..15: chip revision
1078 * - bits 16..23: register dump version
1080 static inline unsigned int mk_adap_vers(const struct adapter
*ap
)
1082 return 4 | (ap
->params
.rev
<< 10) | (1 << 16);
1085 static void reg_block_dump(struct adapter
*ap
, void *buf
, unsigned int start
,
1088 u32
*p
= buf
+ start
;
1090 for ( ; start
<= end
; start
+= sizeof(u32
))
1091 *p
++ = t4_read_reg(ap
, start
);
1094 static void get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1097 static const unsigned int reg_ranges
[] = {
1318 struct adapter
*ap
= netdev2adap(dev
);
1320 regs
->version
= mk_adap_vers(ap
);
1322 memset(buf
, 0, T4_REGMAP_SIZE
);
1323 for (i
= 0; i
< ARRAY_SIZE(reg_ranges
); i
+= 2)
1324 reg_block_dump(ap
, buf
, reg_ranges
[i
], reg_ranges
[i
+ 1]);
1327 static int restart_autoneg(struct net_device
*dev
)
1329 struct port_info
*p
= netdev_priv(dev
);
1331 if (!netif_running(dev
))
1333 if (p
->link_cfg
.autoneg
!= AUTONEG_ENABLE
)
1335 t4_restart_aneg(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
);
1339 static int identify_port(struct net_device
*dev
,
1340 enum ethtool_phys_id_state state
)
1343 struct adapter
*adap
= netdev2adap(dev
);
1345 if (state
== ETHTOOL_ID_ACTIVE
)
1347 else if (state
== ETHTOOL_ID_INACTIVE
)
1352 return t4_identify_port(adap
, adap
->fn
, netdev2pinfo(dev
)->viid
, val
);
1355 static unsigned int from_fw_linkcaps(unsigned int type
, unsigned int caps
)
1359 if (type
== FW_PORT_TYPE_BT_SGMII
|| type
== FW_PORT_TYPE_BT_XFI
||
1360 type
== FW_PORT_TYPE_BT_XAUI
) {
1362 if (caps
& FW_PORT_CAP_SPEED_100M
)
1363 v
|= SUPPORTED_100baseT_Full
;
1364 if (caps
& FW_PORT_CAP_SPEED_1G
)
1365 v
|= SUPPORTED_1000baseT_Full
;
1366 if (caps
& FW_PORT_CAP_SPEED_10G
)
1367 v
|= SUPPORTED_10000baseT_Full
;
1368 } else if (type
== FW_PORT_TYPE_KX4
|| type
== FW_PORT_TYPE_KX
) {
1369 v
|= SUPPORTED_Backplane
;
1370 if (caps
& FW_PORT_CAP_SPEED_1G
)
1371 v
|= SUPPORTED_1000baseKX_Full
;
1372 if (caps
& FW_PORT_CAP_SPEED_10G
)
1373 v
|= SUPPORTED_10000baseKX4_Full
;
1374 } else if (type
== FW_PORT_TYPE_KR
)
1375 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseKR_Full
;
1376 else if (type
== FW_PORT_TYPE_BP_AP
)
1377 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
1378 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
;
1379 else if (type
== FW_PORT_TYPE_BP4_AP
)
1380 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
1381 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
|
1382 SUPPORTED_10000baseKX4_Full
;
1383 else if (type
== FW_PORT_TYPE_FIBER_XFI
||
1384 type
== FW_PORT_TYPE_FIBER_XAUI
|| type
== FW_PORT_TYPE_SFP
)
1385 v
|= SUPPORTED_FIBRE
;
1387 if (caps
& FW_PORT_CAP_ANEG
)
1388 v
|= SUPPORTED_Autoneg
;
1392 static unsigned int to_fw_linkcaps(unsigned int caps
)
1396 if (caps
& ADVERTISED_100baseT_Full
)
1397 v
|= FW_PORT_CAP_SPEED_100M
;
1398 if (caps
& ADVERTISED_1000baseT_Full
)
1399 v
|= FW_PORT_CAP_SPEED_1G
;
1400 if (caps
& ADVERTISED_10000baseT_Full
)
1401 v
|= FW_PORT_CAP_SPEED_10G
;
1405 static int get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1407 const struct port_info
*p
= netdev_priv(dev
);
1409 if (p
->port_type
== FW_PORT_TYPE_BT_SGMII
||
1410 p
->port_type
== FW_PORT_TYPE_BT_XFI
||
1411 p
->port_type
== FW_PORT_TYPE_BT_XAUI
)
1412 cmd
->port
= PORT_TP
;
1413 else if (p
->port_type
== FW_PORT_TYPE_FIBER_XFI
||
1414 p
->port_type
== FW_PORT_TYPE_FIBER_XAUI
)
1415 cmd
->port
= PORT_FIBRE
;
1416 else if (p
->port_type
== FW_PORT_TYPE_SFP
) {
1417 if (p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_PASSIVE
||
1418 p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_ACTIVE
)
1419 cmd
->port
= PORT_DA
;
1421 cmd
->port
= PORT_FIBRE
;
1423 cmd
->port
= PORT_OTHER
;
1425 if (p
->mdio_addr
>= 0) {
1426 cmd
->phy_address
= p
->mdio_addr
;
1427 cmd
->transceiver
= XCVR_EXTERNAL
;
1428 cmd
->mdio_support
= p
->port_type
== FW_PORT_TYPE_BT_SGMII
?
1429 MDIO_SUPPORTS_C22
: MDIO_SUPPORTS_C45
;
1431 cmd
->phy_address
= 0; /* not really, but no better option */
1432 cmd
->transceiver
= XCVR_INTERNAL
;
1433 cmd
->mdio_support
= 0;
1436 cmd
->supported
= from_fw_linkcaps(p
->port_type
, p
->link_cfg
.supported
);
1437 cmd
->advertising
= from_fw_linkcaps(p
->port_type
,
1438 p
->link_cfg
.advertising
);
1439 ethtool_cmd_speed_set(cmd
,
1440 netif_carrier_ok(dev
) ? p
->link_cfg
.speed
: 0);
1441 cmd
->duplex
= DUPLEX_FULL
;
1442 cmd
->autoneg
= p
->link_cfg
.autoneg
;
1448 static unsigned int speed_to_caps(int speed
)
1450 if (speed
== SPEED_100
)
1451 return FW_PORT_CAP_SPEED_100M
;
1452 if (speed
== SPEED_1000
)
1453 return FW_PORT_CAP_SPEED_1G
;
1454 if (speed
== SPEED_10000
)
1455 return FW_PORT_CAP_SPEED_10G
;
1459 static int set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1462 struct port_info
*p
= netdev_priv(dev
);
1463 struct link_config
*lc
= &p
->link_cfg
;
1464 u32 speed
= ethtool_cmd_speed(cmd
);
1466 if (cmd
->duplex
!= DUPLEX_FULL
) /* only full-duplex supported */
1469 if (!(lc
->supported
& FW_PORT_CAP_ANEG
)) {
1471 * PHY offers a single speed. See if that's what's
1474 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
1475 (lc
->supported
& speed_to_caps(speed
)))
1480 if (cmd
->autoneg
== AUTONEG_DISABLE
) {
1481 cap
= speed_to_caps(speed
);
1483 if (!(lc
->supported
& cap
) || (speed
== SPEED_1000
) ||
1484 (speed
== SPEED_10000
))
1486 lc
->requested_speed
= cap
;
1487 lc
->advertising
= 0;
1489 cap
= to_fw_linkcaps(cmd
->advertising
);
1490 if (!(lc
->supported
& cap
))
1492 lc
->requested_speed
= 0;
1493 lc
->advertising
= cap
| FW_PORT_CAP_ANEG
;
1495 lc
->autoneg
= cmd
->autoneg
;
1497 if (netif_running(dev
))
1498 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
1503 static void get_pauseparam(struct net_device
*dev
,
1504 struct ethtool_pauseparam
*epause
)
1506 struct port_info
*p
= netdev_priv(dev
);
1508 epause
->autoneg
= (p
->link_cfg
.requested_fc
& PAUSE_AUTONEG
) != 0;
1509 epause
->rx_pause
= (p
->link_cfg
.fc
& PAUSE_RX
) != 0;
1510 epause
->tx_pause
= (p
->link_cfg
.fc
& PAUSE_TX
) != 0;
1513 static int set_pauseparam(struct net_device
*dev
,
1514 struct ethtool_pauseparam
*epause
)
1516 struct port_info
*p
= netdev_priv(dev
);
1517 struct link_config
*lc
= &p
->link_cfg
;
1519 if (epause
->autoneg
== AUTONEG_DISABLE
)
1520 lc
->requested_fc
= 0;
1521 else if (lc
->supported
& FW_PORT_CAP_ANEG
)
1522 lc
->requested_fc
= PAUSE_AUTONEG
;
1526 if (epause
->rx_pause
)
1527 lc
->requested_fc
|= PAUSE_RX
;
1528 if (epause
->tx_pause
)
1529 lc
->requested_fc
|= PAUSE_TX
;
1530 if (netif_running(dev
))
1531 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
1536 static void get_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
1538 const struct port_info
*pi
= netdev_priv(dev
);
1539 const struct sge
*s
= &pi
->adapter
->sge
;
1541 e
->rx_max_pending
= MAX_RX_BUFFERS
;
1542 e
->rx_mini_max_pending
= MAX_RSPQ_ENTRIES
;
1543 e
->rx_jumbo_max_pending
= 0;
1544 e
->tx_max_pending
= MAX_TXQ_ENTRIES
;
1546 e
->rx_pending
= s
->ethrxq
[pi
->first_qset
].fl
.size
- 8;
1547 e
->rx_mini_pending
= s
->ethrxq
[pi
->first_qset
].rspq
.size
;
1548 e
->rx_jumbo_pending
= 0;
1549 e
->tx_pending
= s
->ethtxq
[pi
->first_qset
].q
.size
;
1552 static int set_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
1555 const struct port_info
*pi
= netdev_priv(dev
);
1556 struct adapter
*adapter
= pi
->adapter
;
1557 struct sge
*s
= &adapter
->sge
;
1559 if (e
->rx_pending
> MAX_RX_BUFFERS
|| e
->rx_jumbo_pending
||
1560 e
->tx_pending
> MAX_TXQ_ENTRIES
||
1561 e
->rx_mini_pending
> MAX_RSPQ_ENTRIES
||
1562 e
->rx_mini_pending
< MIN_RSPQ_ENTRIES
||
1563 e
->rx_pending
< MIN_FL_ENTRIES
|| e
->tx_pending
< MIN_TXQ_ENTRIES
)
1566 if (adapter
->flags
& FULL_INIT_DONE
)
1569 for (i
= 0; i
< pi
->nqsets
; ++i
) {
1570 s
->ethtxq
[pi
->first_qset
+ i
].q
.size
= e
->tx_pending
;
1571 s
->ethrxq
[pi
->first_qset
+ i
].fl
.size
= e
->rx_pending
+ 8;
1572 s
->ethrxq
[pi
->first_qset
+ i
].rspq
.size
= e
->rx_mini_pending
;
1577 static int closest_timer(const struct sge
*s
, int time
)
1579 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
1581 for (i
= 0; i
< ARRAY_SIZE(s
->timer_val
); i
++) {
1582 delta
= time
- s
->timer_val
[i
];
1585 if (delta
< min_delta
) {
1593 static int closest_thres(const struct sge
*s
, int thres
)
1595 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
1597 for (i
= 0; i
< ARRAY_SIZE(s
->counter_val
); i
++) {
1598 delta
= thres
- s
->counter_val
[i
];
1601 if (delta
< min_delta
) {
1610 * Return a queue's interrupt hold-off time in us. 0 means no timer.
1612 static unsigned int qtimer_val(const struct adapter
*adap
,
1613 const struct sge_rspq
*q
)
1615 unsigned int idx
= q
->intr_params
>> 1;
1617 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
1621 * set_rxq_intr_params - set a queue's interrupt holdoff parameters
1622 * @adap: the adapter
1624 * @us: the hold-off time in us, or 0 to disable timer
1625 * @cnt: the hold-off packet count, or 0 to disable counter
1627 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1628 * one of the two needs to be enabled for the queue to generate interrupts.
1630 static int set_rxq_intr_params(struct adapter
*adap
, struct sge_rspq
*q
,
1631 unsigned int us
, unsigned int cnt
)
1633 if ((us
| cnt
) == 0)
1640 new_idx
= closest_thres(&adap
->sge
, cnt
);
1641 if (q
->desc
&& q
->pktcnt_idx
!= new_idx
) {
1642 /* the queue has already been created, update it */
1643 v
= FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ
) |
1644 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
) |
1645 FW_PARAMS_PARAM_YZ(q
->cntxt_id
);
1646 err
= t4_set_params(adap
, adap
->fn
, adap
->fn
, 0, 1, &v
,
1651 q
->pktcnt_idx
= new_idx
;
1654 us
= us
== 0 ? 6 : closest_timer(&adap
->sge
, us
);
1655 q
->intr_params
= QINTR_TIMER_IDX(us
) | (cnt
> 0 ? QINTR_CNT_EN
: 0);
1659 static int set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
1661 const struct port_info
*pi
= netdev_priv(dev
);
1662 struct adapter
*adap
= pi
->adapter
;
1664 return set_rxq_intr_params(adap
, &adap
->sge
.ethrxq
[pi
->first_qset
].rspq
,
1665 c
->rx_coalesce_usecs
, c
->rx_max_coalesced_frames
);
1668 static int get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
1670 const struct port_info
*pi
= netdev_priv(dev
);
1671 const struct adapter
*adap
= pi
->adapter
;
1672 const struct sge_rspq
*rq
= &adap
->sge
.ethrxq
[pi
->first_qset
].rspq
;
1674 c
->rx_coalesce_usecs
= qtimer_val(adap
, rq
);
1675 c
->rx_max_coalesced_frames
= (rq
->intr_params
& QINTR_CNT_EN
) ?
1676 adap
->sge
.counter_val
[rq
->pktcnt_idx
] : 0;
1681 * eeprom_ptov - translate a physical EEPROM address to virtual
1682 * @phys_addr: the physical EEPROM address
1683 * @fn: the PCI function number
1684 * @sz: size of function-specific area
1686 * Translate a physical EEPROM address to virtual. The first 1K is
1687 * accessed through virtual addresses starting at 31K, the rest is
1688 * accessed through virtual addresses starting at 0.
1690 * The mapping is as follows:
1691 * [0..1K) -> [31K..32K)
1692 * [1K..1K+A) -> [31K-A..31K)
1693 * [1K+A..ES) -> [0..ES-A-1K)
1695 * where A = @fn * @sz, and ES = EEPROM size.
1697 static int eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
1700 if (phys_addr
< 1024)
1701 return phys_addr
+ (31 << 10);
1702 if (phys_addr
< 1024 + fn
)
1703 return 31744 - fn
+ phys_addr
- 1024;
1704 if (phys_addr
< EEPROMSIZE
)
1705 return phys_addr
- 1024 - fn
;
1710 * The next two routines implement eeprom read/write from physical addresses.
1712 static int eeprom_rd_phys(struct adapter
*adap
, unsigned int phys_addr
, u32
*v
)
1714 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
1717 vaddr
= pci_read_vpd(adap
->pdev
, vaddr
, sizeof(u32
), v
);
1718 return vaddr
< 0 ? vaddr
: 0;
1721 static int eeprom_wr_phys(struct adapter
*adap
, unsigned int phys_addr
, u32 v
)
1723 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
1726 vaddr
= pci_write_vpd(adap
->pdev
, vaddr
, sizeof(u32
), &v
);
1727 return vaddr
< 0 ? vaddr
: 0;
1730 #define EEPROM_MAGIC 0x38E2F10C
1732 static int get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*e
,
1736 struct adapter
*adapter
= netdev2adap(dev
);
1738 u8
*buf
= kmalloc(EEPROMSIZE
, GFP_KERNEL
);
1742 e
->magic
= EEPROM_MAGIC
;
1743 for (i
= e
->offset
& ~3; !err
&& i
< e
->offset
+ e
->len
; i
+= 4)
1744 err
= eeprom_rd_phys(adapter
, i
, (u32
*)&buf
[i
]);
1747 memcpy(data
, buf
+ e
->offset
, e
->len
);
1752 static int set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
1757 u32 aligned_offset
, aligned_len
, *p
;
1758 struct adapter
*adapter
= netdev2adap(dev
);
1760 if (eeprom
->magic
!= EEPROM_MAGIC
)
1763 aligned_offset
= eeprom
->offset
& ~3;
1764 aligned_len
= (eeprom
->len
+ (eeprom
->offset
& 3) + 3) & ~3;
1766 if (adapter
->fn
> 0) {
1767 u32 start
= 1024 + adapter
->fn
* EEPROMPFSIZE
;
1769 if (aligned_offset
< start
||
1770 aligned_offset
+ aligned_len
> start
+ EEPROMPFSIZE
)
1774 if (aligned_offset
!= eeprom
->offset
|| aligned_len
!= eeprom
->len
) {
1776 * RMW possibly needed for first or last words.
1778 buf
= kmalloc(aligned_len
, GFP_KERNEL
);
1781 err
= eeprom_rd_phys(adapter
, aligned_offset
, (u32
*)buf
);
1782 if (!err
&& aligned_len
> 4)
1783 err
= eeprom_rd_phys(adapter
,
1784 aligned_offset
+ aligned_len
- 4,
1785 (u32
*)&buf
[aligned_len
- 4]);
1788 memcpy(buf
+ (eeprom
->offset
& 3), data
, eeprom
->len
);
1792 err
= t4_seeprom_wp(adapter
, false);
1796 for (p
= (u32
*)buf
; !err
&& aligned_len
; aligned_len
-= 4, p
++) {
1797 err
= eeprom_wr_phys(adapter
, aligned_offset
, *p
);
1798 aligned_offset
+= 4;
1802 err
= t4_seeprom_wp(adapter
, true);
1809 static int set_flash(struct net_device
*netdev
, struct ethtool_flash
*ef
)
1812 const struct firmware
*fw
;
1813 struct adapter
*adap
= netdev2adap(netdev
);
1815 ef
->data
[sizeof(ef
->data
) - 1] = '\0';
1816 ret
= request_firmware(&fw
, ef
->data
, adap
->pdev_dev
);
1820 ret
= t4_load_fw(adap
, fw
->data
, fw
->size
);
1821 release_firmware(fw
);
1823 dev_info(adap
->pdev_dev
, "loaded firmware %s\n", ef
->data
);
1827 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
1828 #define BCAST_CRC 0xa0ccc1a6
1830 static void get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1832 wol
->supported
= WAKE_BCAST
| WAKE_MAGIC
;
1833 wol
->wolopts
= netdev2adap(dev
)->wol
;
1834 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1837 static int set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1840 struct port_info
*pi
= netdev_priv(dev
);
1842 if (wol
->wolopts
& ~WOL_SUPPORTED
)
1844 t4_wol_magic_enable(pi
->adapter
, pi
->tx_chan
,
1845 (wol
->wolopts
& WAKE_MAGIC
) ? dev
->dev_addr
: NULL
);
1846 if (wol
->wolopts
& WAKE_BCAST
) {
1847 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0xfe, ~0ULL,
1850 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 1,
1851 ~6ULL, ~0ULL, BCAST_CRC
, true);
1853 t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0, 0, 0, 0, false);
1857 static int cxgb_set_features(struct net_device
*dev
, u32 features
)
1859 const struct port_info
*pi
= netdev_priv(dev
);
1860 u32 changed
= dev
->features
^ features
;
1863 if (!(changed
& NETIF_F_HW_VLAN_RX
))
1866 err
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, -1,
1868 !!(features
& NETIF_F_HW_VLAN_RX
), true);
1870 dev
->features
= features
^ NETIF_F_HW_VLAN_RX
;
1874 static int get_rss_table(struct net_device
*dev
, struct ethtool_rxfh_indir
*p
)
1876 const struct port_info
*pi
= netdev_priv(dev
);
1877 unsigned int n
= min_t(unsigned int, p
->size
, pi
->rss_size
);
1879 p
->size
= pi
->rss_size
;
1881 p
->ring_index
[n
] = pi
->rss
[n
];
1885 static int set_rss_table(struct net_device
*dev
,
1886 const struct ethtool_rxfh_indir
*p
)
1889 struct port_info
*pi
= netdev_priv(dev
);
1891 if (p
->size
!= pi
->rss_size
)
1893 for (i
= 0; i
< p
->size
; i
++)
1894 if (p
->ring_index
[i
] >= pi
->nqsets
)
1896 for (i
= 0; i
< p
->size
; i
++)
1897 pi
->rss
[i
] = p
->ring_index
[i
];
1898 if (pi
->adapter
->flags
& FULL_INIT_DONE
)
1899 return write_rss(pi
, pi
->rss
);
1903 static int get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
1906 const struct port_info
*pi
= netdev_priv(dev
);
1908 switch (info
->cmd
) {
1909 case ETHTOOL_GRXFH
: {
1910 unsigned int v
= pi
->rss_mode
;
1913 switch (info
->flow_type
) {
1915 if (v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
)
1916 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
1917 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
1918 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
1919 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1922 if ((v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
) &&
1923 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
1924 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
1925 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
1926 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
1927 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1930 case AH_ESP_V4_FLOW
:
1932 if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
1933 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1936 if (v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
)
1937 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
1938 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
1939 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
1940 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1943 if ((v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
) &&
1944 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
1945 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
1946 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
1947 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
1948 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1951 case AH_ESP_V6_FLOW
:
1953 if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
1954 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
1959 case ETHTOOL_GRXRINGS
:
1960 info
->data
= pi
->nqsets
;
1966 static struct ethtool_ops cxgb_ethtool_ops
= {
1967 .get_settings
= get_settings
,
1968 .set_settings
= set_settings
,
1969 .get_drvinfo
= get_drvinfo
,
1970 .get_msglevel
= get_msglevel
,
1971 .set_msglevel
= set_msglevel
,
1972 .get_ringparam
= get_sge_param
,
1973 .set_ringparam
= set_sge_param
,
1974 .get_coalesce
= get_coalesce
,
1975 .set_coalesce
= set_coalesce
,
1976 .get_eeprom_len
= get_eeprom_len
,
1977 .get_eeprom
= get_eeprom
,
1978 .set_eeprom
= set_eeprom
,
1979 .get_pauseparam
= get_pauseparam
,
1980 .set_pauseparam
= set_pauseparam
,
1981 .get_link
= ethtool_op_get_link
,
1982 .get_strings
= get_strings
,
1983 .set_phys_id
= identify_port
,
1984 .nway_reset
= restart_autoneg
,
1985 .get_sset_count
= get_sset_count
,
1986 .get_ethtool_stats
= get_stats
,
1987 .get_regs_len
= get_regs_len
,
1988 .get_regs
= get_regs
,
1991 .get_rxnfc
= get_rxnfc
,
1992 .get_rxfh_indir
= get_rss_table
,
1993 .set_rxfh_indir
= set_rss_table
,
1994 .flash_device
= set_flash
,
2001 static int mem_open(struct inode
*inode
, struct file
*file
)
2003 file
->private_data
= inode
->i_private
;
2007 static ssize_t
mem_read(struct file
*file
, char __user
*buf
, size_t count
,
2011 loff_t avail
= file
->f_path
.dentry
->d_inode
->i_size
;
2012 unsigned int mem
= (uintptr_t)file
->private_data
& 3;
2013 struct adapter
*adap
= file
->private_data
- mem
;
2019 if (count
> avail
- pos
)
2020 count
= avail
- pos
;
2028 ret
= t4_mc_read(adap
, pos
, data
, NULL
);
2030 ret
= t4_edc_read(adap
, mem
, pos
, data
, NULL
);
2034 ofst
= pos
% sizeof(data
);
2035 len
= min(count
, sizeof(data
) - ofst
);
2036 if (copy_to_user(buf
, (u8
*)data
+ ofst
, len
))
2043 count
= pos
- *ppos
;
2048 static const struct file_operations mem_debugfs_fops
= {
2049 .owner
= THIS_MODULE
,
2052 .llseek
= default_llseek
,
2055 static void __devinit
add_debugfs_mem(struct adapter
*adap
, const char *name
,
2056 unsigned int idx
, unsigned int size_mb
)
2060 de
= debugfs_create_file(name
, S_IRUSR
, adap
->debugfs_root
,
2061 (void *)adap
+ idx
, &mem_debugfs_fops
);
2062 if (de
&& de
->d_inode
)
2063 de
->d_inode
->i_size
= size_mb
<< 20;
2066 static int __devinit
setup_debugfs(struct adapter
*adap
)
2070 if (IS_ERR_OR_NULL(adap
->debugfs_root
))
2073 i
= t4_read_reg(adap
, MA_TARGET_MEM_ENABLE
);
2074 if (i
& EDRAM0_ENABLE
)
2075 add_debugfs_mem(adap
, "edc0", MEM_EDC0
, 5);
2076 if (i
& EDRAM1_ENABLE
)
2077 add_debugfs_mem(adap
, "edc1", MEM_EDC1
, 5);
2078 if (i
& EXT_MEM_ENABLE
)
2079 add_debugfs_mem(adap
, "mc", MEM_MC
,
2080 EXT_MEM_SIZE_GET(t4_read_reg(adap
, MA_EXT_MEMORY_BAR
)));
2082 debugfs_create_file("l2t", S_IRUSR
, adap
->debugfs_root
, adap
,
2088 * upper-layer driver support
2092 * Allocate an active-open TID and set it to the supplied value.
2094 int cxgb4_alloc_atid(struct tid_info
*t
, void *data
)
2098 spin_lock_bh(&t
->atid_lock
);
2100 union aopen_entry
*p
= t
->afree
;
2102 atid
= p
- t
->atid_tab
;
2107 spin_unlock_bh(&t
->atid_lock
);
2110 EXPORT_SYMBOL(cxgb4_alloc_atid
);
2113 * Release an active-open TID.
2115 void cxgb4_free_atid(struct tid_info
*t
, unsigned int atid
)
2117 union aopen_entry
*p
= &t
->atid_tab
[atid
];
2119 spin_lock_bh(&t
->atid_lock
);
2123 spin_unlock_bh(&t
->atid_lock
);
2125 EXPORT_SYMBOL(cxgb4_free_atid
);
2128 * Allocate a server TID and set it to the supplied value.
2130 int cxgb4_alloc_stid(struct tid_info
*t
, int family
, void *data
)
2134 spin_lock_bh(&t
->stid_lock
);
2135 if (family
== PF_INET
) {
2136 stid
= find_first_zero_bit(t
->stid_bmap
, t
->nstids
);
2137 if (stid
< t
->nstids
)
2138 __set_bit(stid
, t
->stid_bmap
);
2142 stid
= bitmap_find_free_region(t
->stid_bmap
, t
->nstids
, 2);
2147 t
->stid_tab
[stid
].data
= data
;
2148 stid
+= t
->stid_base
;
2151 spin_unlock_bh(&t
->stid_lock
);
2154 EXPORT_SYMBOL(cxgb4_alloc_stid
);
2157 * Release a server TID.
2159 void cxgb4_free_stid(struct tid_info
*t
, unsigned int stid
, int family
)
2161 stid
-= t
->stid_base
;
2162 spin_lock_bh(&t
->stid_lock
);
2163 if (family
== PF_INET
)
2164 __clear_bit(stid
, t
->stid_bmap
);
2166 bitmap_release_region(t
->stid_bmap
, stid
, 2);
2167 t
->stid_tab
[stid
].data
= NULL
;
2169 spin_unlock_bh(&t
->stid_lock
);
2171 EXPORT_SYMBOL(cxgb4_free_stid
);
2174 * Populate a TID_RELEASE WR. Caller must properly size the skb.
2176 static void mk_tid_release(struct sk_buff
*skb
, unsigned int chan
,
2179 struct cpl_tid_release
*req
;
2181 set_wr_txq(skb
, CPL_PRIORITY_SETUP
, chan
);
2182 req
= (struct cpl_tid_release
*)__skb_put(skb
, sizeof(*req
));
2183 INIT_TP_WR(req
, tid
);
2184 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE
, tid
));
2188 * Queue a TID release request and if necessary schedule a work queue to
2191 static void cxgb4_queue_tid_release(struct tid_info
*t
, unsigned int chan
,
2194 void **p
= &t
->tid_tab
[tid
];
2195 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
2197 spin_lock_bh(&adap
->tid_release_lock
);
2198 *p
= adap
->tid_release_head
;
2199 /* Low 2 bits encode the Tx channel number */
2200 adap
->tid_release_head
= (void **)((uintptr_t)p
| chan
);
2201 if (!adap
->tid_release_task_busy
) {
2202 adap
->tid_release_task_busy
= true;
2203 schedule_work(&adap
->tid_release_task
);
2205 spin_unlock_bh(&adap
->tid_release_lock
);
2209 * Process the list of pending TID release requests.
2211 static void process_tid_release_list(struct work_struct
*work
)
2213 struct sk_buff
*skb
;
2214 struct adapter
*adap
;
2216 adap
= container_of(work
, struct adapter
, tid_release_task
);
2218 spin_lock_bh(&adap
->tid_release_lock
);
2219 while (adap
->tid_release_head
) {
2220 void **p
= adap
->tid_release_head
;
2221 unsigned int chan
= (uintptr_t)p
& 3;
2222 p
= (void *)p
- chan
;
2224 adap
->tid_release_head
= *p
;
2226 spin_unlock_bh(&adap
->tid_release_lock
);
2228 while (!(skb
= alloc_skb(sizeof(struct cpl_tid_release
),
2230 schedule_timeout_uninterruptible(1);
2232 mk_tid_release(skb
, chan
, p
- adap
->tids
.tid_tab
);
2233 t4_ofld_send(adap
, skb
);
2234 spin_lock_bh(&adap
->tid_release_lock
);
2236 adap
->tid_release_task_busy
= false;
2237 spin_unlock_bh(&adap
->tid_release_lock
);
2241 * Release a TID and inform HW. If we are unable to allocate the release
2242 * message we defer to a work queue.
2244 void cxgb4_remove_tid(struct tid_info
*t
, unsigned int chan
, unsigned int tid
)
2247 struct sk_buff
*skb
;
2248 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
2250 old
= t
->tid_tab
[tid
];
2251 skb
= alloc_skb(sizeof(struct cpl_tid_release
), GFP_ATOMIC
);
2253 t
->tid_tab
[tid
] = NULL
;
2254 mk_tid_release(skb
, chan
, tid
);
2255 t4_ofld_send(adap
, skb
);
2257 cxgb4_queue_tid_release(t
, chan
, tid
);
2259 atomic_dec(&t
->tids_in_use
);
2261 EXPORT_SYMBOL(cxgb4_remove_tid
);
2264 * Allocate and initialize the TID tables. Returns 0 on success.
2266 static int tid_init(struct tid_info
*t
)
2269 unsigned int natids
= t
->natids
;
2271 size
= t
->ntids
* sizeof(*t
->tid_tab
) + natids
* sizeof(*t
->atid_tab
) +
2272 t
->nstids
* sizeof(*t
->stid_tab
) +
2273 BITS_TO_LONGS(t
->nstids
) * sizeof(long);
2274 t
->tid_tab
= t4_alloc_mem(size
);
2278 t
->atid_tab
= (union aopen_entry
*)&t
->tid_tab
[t
->ntids
];
2279 t
->stid_tab
= (struct serv_entry
*)&t
->atid_tab
[natids
];
2280 t
->stid_bmap
= (unsigned long *)&t
->stid_tab
[t
->nstids
];
2281 spin_lock_init(&t
->stid_lock
);
2282 spin_lock_init(&t
->atid_lock
);
2284 t
->stids_in_use
= 0;
2286 t
->atids_in_use
= 0;
2287 atomic_set(&t
->tids_in_use
, 0);
2289 /* Setup the free list for atid_tab and clear the stid bitmap. */
2292 t
->atid_tab
[natids
- 1].next
= &t
->atid_tab
[natids
];
2293 t
->afree
= t
->atid_tab
;
2295 bitmap_zero(t
->stid_bmap
, t
->nstids
);
2300 * cxgb4_create_server - create an IP server
2302 * @stid: the server TID
2303 * @sip: local IP address to bind server to
2304 * @sport: the server's TCP port
2305 * @queue: queue to direct messages from this server to
2307 * Create an IP server for the given port and address.
2308 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2310 int cxgb4_create_server(const struct net_device
*dev
, unsigned int stid
,
2311 __be32 sip
, __be16 sport
, unsigned int queue
)
2314 struct sk_buff
*skb
;
2315 struct adapter
*adap
;
2316 struct cpl_pass_open_req
*req
;
2318 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
2322 adap
= netdev2adap(dev
);
2323 req
= (struct cpl_pass_open_req
*)__skb_put(skb
, sizeof(*req
));
2325 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ
, stid
));
2326 req
->local_port
= sport
;
2327 req
->peer_port
= htons(0);
2328 req
->local_ip
= sip
;
2329 req
->peer_ip
= htonl(0);
2330 chan
= rxq_to_chan(&adap
->sge
, queue
);
2331 req
->opt0
= cpu_to_be64(TX_CHAN(chan
));
2332 req
->opt1
= cpu_to_be64(CONN_POLICY_ASK
|
2333 SYN_RSS_ENABLE
| SYN_RSS_QUEUE(queue
));
2334 return t4_mgmt_tx(adap
, skb
);
2336 EXPORT_SYMBOL(cxgb4_create_server
);
2339 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
2340 * @mtus: the HW MTU table
2341 * @mtu: the target MTU
2342 * @idx: index of selected entry in the MTU table
2344 * Returns the index and the value in the HW MTU table that is closest to
2345 * but does not exceed @mtu, unless @mtu is smaller than any value in the
2346 * table, in which case that smallest available value is selected.
2348 unsigned int cxgb4_best_mtu(const unsigned short *mtus
, unsigned short mtu
,
2353 while (i
< NMTUS
- 1 && mtus
[i
+ 1] <= mtu
)
2359 EXPORT_SYMBOL(cxgb4_best_mtu
);
2362 * cxgb4_port_chan - get the HW channel of a port
2363 * @dev: the net device for the port
2365 * Return the HW Tx channel of the given port.
2367 unsigned int cxgb4_port_chan(const struct net_device
*dev
)
2369 return netdev2pinfo(dev
)->tx_chan
;
2371 EXPORT_SYMBOL(cxgb4_port_chan
);
2374 * cxgb4_port_viid - get the VI id of a port
2375 * @dev: the net device for the port
2377 * Return the VI id of the given port.
2379 unsigned int cxgb4_port_viid(const struct net_device
*dev
)
2381 return netdev2pinfo(dev
)->viid
;
2383 EXPORT_SYMBOL(cxgb4_port_viid
);
2386 * cxgb4_port_idx - get the index of a port
2387 * @dev: the net device for the port
2389 * Return the index of the given port.
2391 unsigned int cxgb4_port_idx(const struct net_device
*dev
)
2393 return netdev2pinfo(dev
)->port_id
;
2395 EXPORT_SYMBOL(cxgb4_port_idx
);
2397 void cxgb4_get_tcp_stats(struct pci_dev
*pdev
, struct tp_tcp_stats
*v4
,
2398 struct tp_tcp_stats
*v6
)
2400 struct adapter
*adap
= pci_get_drvdata(pdev
);
2402 spin_lock(&adap
->stats_lock
);
2403 t4_tp_get_tcp_stats(adap
, v4
, v6
);
2404 spin_unlock(&adap
->stats_lock
);
2406 EXPORT_SYMBOL(cxgb4_get_tcp_stats
);
2408 void cxgb4_iscsi_init(struct net_device
*dev
, unsigned int tag_mask
,
2409 const unsigned int *pgsz_order
)
2411 struct adapter
*adap
= netdev2adap(dev
);
2413 t4_write_reg(adap
, ULP_RX_ISCSI_TAGMASK
, tag_mask
);
2414 t4_write_reg(adap
, ULP_RX_ISCSI_PSZ
, HPZ0(pgsz_order
[0]) |
2415 HPZ1(pgsz_order
[1]) | HPZ2(pgsz_order
[2]) |
2416 HPZ3(pgsz_order
[3]));
2418 EXPORT_SYMBOL(cxgb4_iscsi_init
);
2420 static struct pci_driver cxgb4_driver
;
2422 static void check_neigh_update(struct neighbour
*neigh
)
2424 const struct device
*parent
;
2425 const struct net_device
*netdev
= neigh
->dev
;
2427 if (netdev
->priv_flags
& IFF_802_1Q_VLAN
)
2428 netdev
= vlan_dev_real_dev(netdev
);
2429 parent
= netdev
->dev
.parent
;
2430 if (parent
&& parent
->driver
== &cxgb4_driver
.driver
)
2431 t4_l2t_update(dev_get_drvdata(parent
), neigh
);
2434 static int netevent_cb(struct notifier_block
*nb
, unsigned long event
,
2438 case NETEVENT_NEIGH_UPDATE
:
2439 check_neigh_update(data
);
2441 case NETEVENT_REDIRECT
:
2448 static bool netevent_registered
;
2449 static struct notifier_block cxgb4_netevent_nb
= {
2450 .notifier_call
= netevent_cb
2453 static void uld_attach(struct adapter
*adap
, unsigned int uld
)
2456 struct cxgb4_lld_info lli
;
2458 lli
.pdev
= adap
->pdev
;
2459 lli
.l2t
= adap
->l2t
;
2460 lli
.tids
= &adap
->tids
;
2461 lli
.ports
= adap
->port
;
2462 lli
.vr
= &adap
->vres
;
2463 lli
.mtus
= adap
->params
.mtus
;
2464 if (uld
== CXGB4_ULD_RDMA
) {
2465 lli
.rxq_ids
= adap
->sge
.rdma_rxq
;
2466 lli
.nrxq
= adap
->sge
.rdmaqs
;
2467 } else if (uld
== CXGB4_ULD_ISCSI
) {
2468 lli
.rxq_ids
= adap
->sge
.ofld_rxq
;
2469 lli
.nrxq
= adap
->sge
.ofldqsets
;
2471 lli
.ntxq
= adap
->sge
.ofldqsets
;
2472 lli
.nchan
= adap
->params
.nports
;
2473 lli
.nports
= adap
->params
.nports
;
2474 lli
.wr_cred
= adap
->params
.ofldq_wr_cred
;
2475 lli
.adapter_type
= adap
->params
.rev
;
2476 lli
.iscsi_iolen
= MAXRXDATA_GET(t4_read_reg(adap
, TP_PARA_REG2
));
2477 lli
.udb_density
= 1 << QUEUESPERPAGEPF0_GET(
2478 t4_read_reg(adap
, SGE_EGRESS_QUEUES_PER_PAGE_PF
) >>
2480 lli
.ucq_density
= 1 << QUEUESPERPAGEPF0_GET(
2481 t4_read_reg(adap
, SGE_INGRESS_QUEUES_PER_PAGE_PF
) >>
2483 lli
.gts_reg
= adap
->regs
+ MYPF_REG(SGE_PF_GTS
);
2484 lli
.db_reg
= adap
->regs
+ MYPF_REG(SGE_PF_KDOORBELL
);
2485 lli
.fw_vers
= adap
->params
.fw_vers
;
2487 handle
= ulds
[uld
].add(&lli
);
2488 if (IS_ERR(handle
)) {
2489 dev_warn(adap
->pdev_dev
,
2490 "could not attach to the %s driver, error %ld\n",
2491 uld_str
[uld
], PTR_ERR(handle
));
2495 adap
->uld_handle
[uld
] = handle
;
2497 if (!netevent_registered
) {
2498 register_netevent_notifier(&cxgb4_netevent_nb
);
2499 netevent_registered
= true;
2502 if (adap
->flags
& FULL_INIT_DONE
)
2503 ulds
[uld
].state_change(handle
, CXGB4_STATE_UP
);
2506 static void attach_ulds(struct adapter
*adap
)
2510 mutex_lock(&uld_mutex
);
2511 list_add_tail(&adap
->list_node
, &adapter_list
);
2512 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
2514 uld_attach(adap
, i
);
2515 mutex_unlock(&uld_mutex
);
2518 static void detach_ulds(struct adapter
*adap
)
2522 mutex_lock(&uld_mutex
);
2523 list_del(&adap
->list_node
);
2524 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
2525 if (adap
->uld_handle
[i
]) {
2526 ulds
[i
].state_change(adap
->uld_handle
[i
],
2527 CXGB4_STATE_DETACH
);
2528 adap
->uld_handle
[i
] = NULL
;
2530 if (netevent_registered
&& list_empty(&adapter_list
)) {
2531 unregister_netevent_notifier(&cxgb4_netevent_nb
);
2532 netevent_registered
= false;
2534 mutex_unlock(&uld_mutex
);
2537 static void notify_ulds(struct adapter
*adap
, enum cxgb4_state new_state
)
2541 mutex_lock(&uld_mutex
);
2542 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
2543 if (adap
->uld_handle
[i
])
2544 ulds
[i
].state_change(adap
->uld_handle
[i
], new_state
);
2545 mutex_unlock(&uld_mutex
);
2549 * cxgb4_register_uld - register an upper-layer driver
2550 * @type: the ULD type
2551 * @p: the ULD methods
2553 * Registers an upper-layer driver with this driver and notifies the ULD
2554 * about any presently available devices that support its type. Returns
2555 * %-EBUSY if a ULD of the same type is already registered.
2557 int cxgb4_register_uld(enum cxgb4_uld type
, const struct cxgb4_uld_info
*p
)
2560 struct adapter
*adap
;
2562 if (type
>= CXGB4_ULD_MAX
)
2564 mutex_lock(&uld_mutex
);
2565 if (ulds
[type
].add
) {
2570 list_for_each_entry(adap
, &adapter_list
, list_node
)
2571 uld_attach(adap
, type
);
2572 out
: mutex_unlock(&uld_mutex
);
2575 EXPORT_SYMBOL(cxgb4_register_uld
);
2578 * cxgb4_unregister_uld - unregister an upper-layer driver
2579 * @type: the ULD type
2581 * Unregisters an existing upper-layer driver.
2583 int cxgb4_unregister_uld(enum cxgb4_uld type
)
2585 struct adapter
*adap
;
2587 if (type
>= CXGB4_ULD_MAX
)
2589 mutex_lock(&uld_mutex
);
2590 list_for_each_entry(adap
, &adapter_list
, list_node
)
2591 adap
->uld_handle
[type
] = NULL
;
2592 ulds
[type
].add
= NULL
;
2593 mutex_unlock(&uld_mutex
);
2596 EXPORT_SYMBOL(cxgb4_unregister_uld
);
2599 * cxgb_up - enable the adapter
2600 * @adap: adapter being enabled
2602 * Called when the first port is enabled, this function performs the
2603 * actions necessary to make an adapter operational, such as completing
2604 * the initialization of HW modules, and enabling interrupts.
2606 * Must be called with the rtnl lock held.
2608 static int cxgb_up(struct adapter
*adap
)
2612 err
= setup_sge_queues(adap
);
2615 err
= setup_rss(adap
);
2619 if (adap
->flags
& USING_MSIX
) {
2620 name_msix_vecs(adap
);
2621 err
= request_irq(adap
->msix_info
[0].vec
, t4_nondata_intr
, 0,
2622 adap
->msix_info
[0].desc
, adap
);
2626 err
= request_msix_queue_irqs(adap
);
2628 free_irq(adap
->msix_info
[0].vec
, adap
);
2632 err
= request_irq(adap
->pdev
->irq
, t4_intr_handler(adap
),
2633 (adap
->flags
& USING_MSI
) ? 0 : IRQF_SHARED
,
2634 adap
->port
[0]->name
, adap
);
2640 t4_intr_enable(adap
);
2641 adap
->flags
|= FULL_INIT_DONE
;
2642 notify_ulds(adap
, CXGB4_STATE_UP
);
2646 dev_err(adap
->pdev_dev
, "request_irq failed, err %d\n", err
);
2648 t4_free_sge_resources(adap
);
2652 static void cxgb_down(struct adapter
*adapter
)
2654 t4_intr_disable(adapter
);
2655 cancel_work_sync(&adapter
->tid_release_task
);
2656 adapter
->tid_release_task_busy
= false;
2657 adapter
->tid_release_head
= NULL
;
2659 if (adapter
->flags
& USING_MSIX
) {
2660 free_msix_queue_irqs(adapter
);
2661 free_irq(adapter
->msix_info
[0].vec
, adapter
);
2663 free_irq(adapter
->pdev
->irq
, adapter
);
2664 quiesce_rx(adapter
);
2665 t4_sge_stop(adapter
);
2666 t4_free_sge_resources(adapter
);
2667 adapter
->flags
&= ~FULL_INIT_DONE
;
2671 * net_device operations
2673 static int cxgb_open(struct net_device
*dev
)
2676 struct port_info
*pi
= netdev_priv(dev
);
2677 struct adapter
*adapter
= pi
->adapter
;
2679 netif_carrier_off(dev
);
2681 if (!(adapter
->flags
& FULL_INIT_DONE
)) {
2682 err
= cxgb_up(adapter
);
2687 err
= link_start(dev
);
2689 netif_tx_start_all_queues(dev
);
2693 static int cxgb_close(struct net_device
*dev
)
2695 struct port_info
*pi
= netdev_priv(dev
);
2696 struct adapter
*adapter
= pi
->adapter
;
2698 netif_tx_stop_all_queues(dev
);
2699 netif_carrier_off(dev
);
2700 return t4_enable_vi(adapter
, adapter
->fn
, pi
->viid
, false, false);
2703 static struct rtnl_link_stats64
*cxgb_get_stats(struct net_device
*dev
,
2704 struct rtnl_link_stats64
*ns
)
2706 struct port_stats stats
;
2707 struct port_info
*p
= netdev_priv(dev
);
2708 struct adapter
*adapter
= p
->adapter
;
2710 spin_lock(&adapter
->stats_lock
);
2711 t4_get_port_stats(adapter
, p
->tx_chan
, &stats
);
2712 spin_unlock(&adapter
->stats_lock
);
2714 ns
->tx_bytes
= stats
.tx_octets
;
2715 ns
->tx_packets
= stats
.tx_frames
;
2716 ns
->rx_bytes
= stats
.rx_octets
;
2717 ns
->rx_packets
= stats
.rx_frames
;
2718 ns
->multicast
= stats
.rx_mcast_frames
;
2720 /* detailed rx_errors */
2721 ns
->rx_length_errors
= stats
.rx_jabber
+ stats
.rx_too_long
+
2723 ns
->rx_over_errors
= 0;
2724 ns
->rx_crc_errors
= stats
.rx_fcs_err
;
2725 ns
->rx_frame_errors
= stats
.rx_symbol_err
;
2726 ns
->rx_fifo_errors
= stats
.rx_ovflow0
+ stats
.rx_ovflow1
+
2727 stats
.rx_ovflow2
+ stats
.rx_ovflow3
+
2728 stats
.rx_trunc0
+ stats
.rx_trunc1
+
2729 stats
.rx_trunc2
+ stats
.rx_trunc3
;
2730 ns
->rx_missed_errors
= 0;
2732 /* detailed tx_errors */
2733 ns
->tx_aborted_errors
= 0;
2734 ns
->tx_carrier_errors
= 0;
2735 ns
->tx_fifo_errors
= 0;
2736 ns
->tx_heartbeat_errors
= 0;
2737 ns
->tx_window_errors
= 0;
2739 ns
->tx_errors
= stats
.tx_error_frames
;
2740 ns
->rx_errors
= stats
.rx_symbol_err
+ stats
.rx_fcs_err
+
2741 ns
->rx_length_errors
+ stats
.rx_len_err
+ ns
->rx_fifo_errors
;
2745 static int cxgb_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
2748 int ret
= 0, prtad
, devad
;
2749 struct port_info
*pi
= netdev_priv(dev
);
2750 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*)&req
->ifr_data
;
2754 if (pi
->mdio_addr
< 0)
2756 data
->phy_id
= pi
->mdio_addr
;
2760 if (mdio_phy_id_is_c45(data
->phy_id
)) {
2761 prtad
= mdio_phy_id_prtad(data
->phy_id
);
2762 devad
= mdio_phy_id_devad(data
->phy_id
);
2763 } else if (data
->phy_id
< 32) {
2764 prtad
= data
->phy_id
;
2766 data
->reg_num
&= 0x1f;
2770 mbox
= pi
->adapter
->fn
;
2771 if (cmd
== SIOCGMIIREG
)
2772 ret
= t4_mdio_rd(pi
->adapter
, mbox
, prtad
, devad
,
2773 data
->reg_num
, &data
->val_out
);
2775 ret
= t4_mdio_wr(pi
->adapter
, mbox
, prtad
, devad
,
2776 data
->reg_num
, data
->val_in
);
2784 static void cxgb_set_rxmode(struct net_device
*dev
)
2786 /* unfortunately we can't return errors to the stack */
2787 set_rxmode(dev
, -1, false);
2790 static int cxgb_change_mtu(struct net_device
*dev
, int new_mtu
)
2793 struct port_info
*pi
= netdev_priv(dev
);
2795 if (new_mtu
< 81 || new_mtu
> MAX_MTU
) /* accommodate SACK */
2797 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, new_mtu
, -1,
2804 static int cxgb_set_mac_addr(struct net_device
*dev
, void *p
)
2807 struct sockaddr
*addr
= p
;
2808 struct port_info
*pi
= netdev_priv(dev
);
2810 if (!is_valid_ether_addr(addr
->sa_data
))
2813 ret
= t4_change_mac(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
,
2814 pi
->xact_addr_filt
, addr
->sa_data
, true, true);
2818 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2819 pi
->xact_addr_filt
= ret
;
2823 #ifdef CONFIG_NET_POLL_CONTROLLER
2824 static void cxgb_netpoll(struct net_device
*dev
)
2826 struct port_info
*pi
= netdev_priv(dev
);
2827 struct adapter
*adap
= pi
->adapter
;
2829 if (adap
->flags
& USING_MSIX
) {
2831 struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[pi
->first_qset
];
2833 for (i
= pi
->nqsets
; i
; i
--, rx
++)
2834 t4_sge_intr_msix(0, &rx
->rspq
);
2836 t4_intr_handler(adap
)(0, adap
);
2840 static const struct net_device_ops cxgb4_netdev_ops
= {
2841 .ndo_open
= cxgb_open
,
2842 .ndo_stop
= cxgb_close
,
2843 .ndo_start_xmit
= t4_eth_xmit
,
2844 .ndo_get_stats64
= cxgb_get_stats
,
2845 .ndo_set_rx_mode
= cxgb_set_rxmode
,
2846 .ndo_set_mac_address
= cxgb_set_mac_addr
,
2847 .ndo_set_features
= cxgb_set_features
,
2848 .ndo_validate_addr
= eth_validate_addr
,
2849 .ndo_do_ioctl
= cxgb_ioctl
,
2850 .ndo_change_mtu
= cxgb_change_mtu
,
2851 #ifdef CONFIG_NET_POLL_CONTROLLER
2852 .ndo_poll_controller
= cxgb_netpoll
,
2856 void t4_fatal_err(struct adapter
*adap
)
2858 t4_set_reg_field(adap
, SGE_CONTROL
, GLOBALENABLE
, 0);
2859 t4_intr_disable(adap
);
2860 dev_alert(adap
->pdev_dev
, "encountered fatal error, adapter stopped\n");
2863 static void setup_memwin(struct adapter
*adap
)
2867 bar0
= pci_resource_start(adap
->pdev
, 0); /* truncation intentional */
2868 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 0),
2869 (bar0
+ MEMWIN0_BASE
) | BIR(0) |
2870 WINDOW(ilog2(MEMWIN0_APERTURE
) - 10));
2871 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 1),
2872 (bar0
+ MEMWIN1_BASE
) | BIR(0) |
2873 WINDOW(ilog2(MEMWIN1_APERTURE
) - 10));
2874 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 2),
2875 (bar0
+ MEMWIN2_BASE
) | BIR(0) |
2876 WINDOW(ilog2(MEMWIN2_APERTURE
) - 10));
2877 if (adap
->vres
.ocq
.size
) {
2878 unsigned int start
, sz_kb
;
2880 start
= pci_resource_start(adap
->pdev
, 2) +
2881 OCQ_WIN_OFFSET(adap
->pdev
, &adap
->vres
);
2882 sz_kb
= roundup_pow_of_two(adap
->vres
.ocq
.size
) >> 10;
2884 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 3),
2885 start
| BIR(1) | WINDOW(ilog2(sz_kb
)));
2887 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3),
2888 adap
->vres
.ocq
.start
);
2890 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3));
2894 static int adap_init1(struct adapter
*adap
, struct fw_caps_config_cmd
*c
)
2899 /* get device capabilities */
2900 memset(c
, 0, sizeof(*c
));
2901 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
2902 FW_CMD_REQUEST
| FW_CMD_READ
);
2903 c
->retval_len16
= htonl(FW_LEN16(*c
));
2904 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), c
);
2908 /* select capabilities we'll be using */
2909 if (c
->niccaps
& htons(FW_CAPS_CONFIG_NIC_VM
)) {
2911 c
->niccaps
^= htons(FW_CAPS_CONFIG_NIC_VM
);
2913 c
->niccaps
= htons(FW_CAPS_CONFIG_NIC_VM
);
2914 } else if (vf_acls
) {
2915 dev_err(adap
->pdev_dev
, "virtualization ACLs not supported");
2918 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
2919 FW_CMD_REQUEST
| FW_CMD_WRITE
);
2920 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), NULL
);
2924 ret
= t4_config_glbl_rss(adap
, adap
->fn
,
2925 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
,
2926 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN
|
2927 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP
);
2931 ret
= t4_cfg_pfvf(adap
, adap
->fn
, adap
->fn
, 0, MAX_EGRQ
, 64, MAX_INGQ
,
2932 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF
, FW_CMD_CAP_PF
);
2938 /* tweak some settings */
2939 t4_write_reg(adap
, TP_SHIFT_CNT
, 0x64f8849);
2940 t4_write_reg(adap
, ULP_RX_TDDP_PSZ
, HPZ0(PAGE_SHIFT
- 12));
2941 t4_write_reg(adap
, TP_PIO_ADDR
, TP_INGRESS_CONFIG
);
2942 v
= t4_read_reg(adap
, TP_PIO_DATA
);
2943 t4_write_reg(adap
, TP_PIO_DATA
, v
& ~CSUM_HAS_PSEUDO_HDR
);
2945 /* get basic stuff going */
2946 return t4_early_init(adap
, adap
->fn
);
2950 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
2952 #define MAX_ATIDS 8192U
2955 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
2957 static int adap_init0(struct adapter
*adap
)
2961 enum dev_state state
;
2962 u32 params
[7], val
[7];
2963 struct fw_caps_config_cmd c
;
2965 ret
= t4_check_fw_version(adap
);
2966 if (ret
== -EINVAL
|| ret
> 0) {
2967 if (upgrade_fw(adap
) >= 0) /* recache FW version */
2968 ret
= t4_check_fw_version(adap
);
2973 /* contact FW, request master */
2974 ret
= t4_fw_hello(adap
, adap
->fn
, adap
->fn
, MASTER_MUST
, &state
);
2976 dev_err(adap
->pdev_dev
, "could not connect to FW, error %d\n",
2982 ret
= t4_fw_reset(adap
, adap
->fn
, PIORSTMODE
| PIORST
);
2986 for (v
= 0; v
< SGE_NTIMERS
- 1; v
++)
2987 adap
->sge
.timer_val
[v
] = min(intr_holdoff
[v
], MAX_SGE_TIMERVAL
);
2988 adap
->sge
.timer_val
[SGE_NTIMERS
- 1] = MAX_SGE_TIMERVAL
;
2989 adap
->sge
.counter_val
[0] = 1;
2990 for (v
= 1; v
< SGE_NCOUNTERS
; v
++)
2991 adap
->sge
.counter_val
[v
] = min(intr_cnt
[v
- 1],
2993 #define FW_PARAM_DEV(param) \
2994 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2995 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2997 params
[0] = FW_PARAM_DEV(CCLK
);
2998 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 1, params
, val
);
3001 adap
->params
.vpd
.cclk
= val
[0];
3003 ret
= adap_init1(adap
, &c
);
3007 #define FW_PARAM_PFVF(param) \
3008 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3009 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
3010 FW_PARAMS_PARAM_Y(adap->fn))
3012 params
[0] = FW_PARAM_DEV(PORTVEC
);
3013 params
[1] = FW_PARAM_PFVF(L2T_START
);
3014 params
[2] = FW_PARAM_PFVF(L2T_END
);
3015 params
[3] = FW_PARAM_PFVF(FILTER_START
);
3016 params
[4] = FW_PARAM_PFVF(FILTER_END
);
3017 params
[5] = FW_PARAM_PFVF(IQFLINT_START
);
3018 params
[6] = FW_PARAM_PFVF(EQ_START
);
3019 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 7, params
, val
);
3023 adap
->tids
.ftid_base
= val
[3];
3024 adap
->tids
.nftids
= val
[4] - val
[3] + 1;
3025 adap
->sge
.ingr_start
= val
[5];
3026 adap
->sge
.egr_start
= val
[6];
3029 /* query offload-related parameters */
3030 params
[0] = FW_PARAM_DEV(NTID
);
3031 params
[1] = FW_PARAM_PFVF(SERVER_START
);
3032 params
[2] = FW_PARAM_PFVF(SERVER_END
);
3033 params
[3] = FW_PARAM_PFVF(TDDP_START
);
3034 params
[4] = FW_PARAM_PFVF(TDDP_END
);
3035 params
[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ
);
3036 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 6, params
,
3040 adap
->tids
.ntids
= val
[0];
3041 adap
->tids
.natids
= min(adap
->tids
.ntids
/ 2, MAX_ATIDS
);
3042 adap
->tids
.stid_base
= val
[1];
3043 adap
->tids
.nstids
= val
[2] - val
[1] + 1;
3044 adap
->vres
.ddp
.start
= val
[3];
3045 adap
->vres
.ddp
.size
= val
[4] - val
[3] + 1;
3046 adap
->params
.ofldq_wr_cred
= val
[5];
3047 adap
->params
.offload
= 1;
3050 params
[0] = FW_PARAM_PFVF(STAG_START
);
3051 params
[1] = FW_PARAM_PFVF(STAG_END
);
3052 params
[2] = FW_PARAM_PFVF(RQ_START
);
3053 params
[3] = FW_PARAM_PFVF(RQ_END
);
3054 params
[4] = FW_PARAM_PFVF(PBL_START
);
3055 params
[5] = FW_PARAM_PFVF(PBL_END
);
3056 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 6, params
,
3060 adap
->vres
.stag
.start
= val
[0];
3061 adap
->vres
.stag
.size
= val
[1] - val
[0] + 1;
3062 adap
->vres
.rq
.start
= val
[2];
3063 adap
->vres
.rq
.size
= val
[3] - val
[2] + 1;
3064 adap
->vres
.pbl
.start
= val
[4];
3065 adap
->vres
.pbl
.size
= val
[5] - val
[4] + 1;
3067 params
[0] = FW_PARAM_PFVF(SQRQ_START
);
3068 params
[1] = FW_PARAM_PFVF(SQRQ_END
);
3069 params
[2] = FW_PARAM_PFVF(CQ_START
);
3070 params
[3] = FW_PARAM_PFVF(CQ_END
);
3071 params
[4] = FW_PARAM_PFVF(OCQ_START
);
3072 params
[5] = FW_PARAM_PFVF(OCQ_END
);
3073 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 6, params
,
3077 adap
->vres
.qp
.start
= val
[0];
3078 adap
->vres
.qp
.size
= val
[1] - val
[0] + 1;
3079 adap
->vres
.cq
.start
= val
[2];
3080 adap
->vres
.cq
.size
= val
[3] - val
[2] + 1;
3081 adap
->vres
.ocq
.start
= val
[4];
3082 adap
->vres
.ocq
.size
= val
[5] - val
[4] + 1;
3085 params
[0] = FW_PARAM_PFVF(ISCSI_START
);
3086 params
[1] = FW_PARAM_PFVF(ISCSI_END
);
3087 ret
= t4_query_params(adap
, adap
->fn
, adap
->fn
, 0, 2, params
,
3091 adap
->vres
.iscsi
.start
= val
[0];
3092 adap
->vres
.iscsi
.size
= val
[1] - val
[0] + 1;
3094 #undef FW_PARAM_PFVF
3097 adap
->params
.nports
= hweight32(port_vec
);
3098 adap
->params
.portvec
= port_vec
;
3099 adap
->flags
|= FW_OK
;
3101 /* These are finalized by FW initialization, load their values now */
3102 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION
);
3103 adap
->params
.tp
.tre
= TIMERRESOLUTION_GET(v
);
3104 t4_read_mtu_tbl(adap
, adap
->params
.mtus
, NULL
);
3105 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
3106 adap
->params
.b_wnd
);
3108 #ifdef CONFIG_PCI_IOV
3110 * Provision resource limits for Virtual Functions. We currently
3111 * grant them all the same static resource limits except for the Port
3112 * Access Rights Mask which we're assigning based on the PF. All of
3113 * the static provisioning stuff for both the PF and VF really needs
3114 * to be managed in a persistent manner for each device which the
3115 * firmware controls.
3120 for (pf
= 0; pf
< ARRAY_SIZE(num_vf
); pf
++) {
3121 if (num_vf
[pf
] <= 0)
3124 /* VF numbering starts at 1! */
3125 for (vf
= 1; vf
<= num_vf
[pf
]; vf
++) {
3126 ret
= t4_cfg_pfvf(adap
, adap
->fn
, pf
, vf
,
3127 VFRES_NEQ
, VFRES_NETHCTRL
,
3128 VFRES_NIQFLINT
, VFRES_NIQ
,
3129 VFRES_TC
, VFRES_NVI
,
3130 FW_PFVF_CMD_CMASK_MASK
,
3131 pfvfres_pmask(adap
, pf
, vf
),
3133 VFRES_R_CAPS
, VFRES_WX_CAPS
);
3135 dev_warn(adap
->pdev_dev
, "failed to "
3136 "provision pf/vf=%d/%d; "
3137 "err=%d\n", pf
, vf
, ret
);
3147 * If a command timed out or failed with EIO FW does not operate within
3148 * its spec or something catastrophic happened to HW/FW, stop issuing
3151 bye
: if (ret
!= -ETIMEDOUT
&& ret
!= -EIO
)
3152 t4_fw_bye(adap
, adap
->fn
);
3158 static pci_ers_result_t
eeh_err_detected(struct pci_dev
*pdev
,
3159 pci_channel_state_t state
)
3162 struct adapter
*adap
= pci_get_drvdata(pdev
);
3168 adap
->flags
&= ~FW_OK
;
3169 notify_ulds(adap
, CXGB4_STATE_START_RECOVERY
);
3170 for_each_port(adap
, i
) {
3171 struct net_device
*dev
= adap
->port
[i
];
3173 netif_device_detach(dev
);
3174 netif_carrier_off(dev
);
3176 if (adap
->flags
& FULL_INIT_DONE
)
3179 pci_disable_device(pdev
);
3180 out
: return state
== pci_channel_io_perm_failure
?
3181 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
3184 static pci_ers_result_t
eeh_slot_reset(struct pci_dev
*pdev
)
3187 struct fw_caps_config_cmd c
;
3188 struct adapter
*adap
= pci_get_drvdata(pdev
);
3191 pci_restore_state(pdev
);
3192 pci_save_state(pdev
);
3193 return PCI_ERS_RESULT_RECOVERED
;
3196 if (pci_enable_device(pdev
)) {
3197 dev_err(&pdev
->dev
, "cannot reenable PCI device after reset\n");
3198 return PCI_ERS_RESULT_DISCONNECT
;
3201 pci_set_master(pdev
);
3202 pci_restore_state(pdev
);
3203 pci_save_state(pdev
);
3204 pci_cleanup_aer_uncorrect_error_status(pdev
);
3206 if (t4_wait_dev_ready(adap
) < 0)
3207 return PCI_ERS_RESULT_DISCONNECT
;
3208 if (t4_fw_hello(adap
, adap
->fn
, adap
->fn
, MASTER_MUST
, NULL
))
3209 return PCI_ERS_RESULT_DISCONNECT
;
3210 adap
->flags
|= FW_OK
;
3211 if (adap_init1(adap
, &c
))
3212 return PCI_ERS_RESULT_DISCONNECT
;
3214 for_each_port(adap
, i
) {
3215 struct port_info
*p
= adap2pinfo(adap
, i
);
3217 ret
= t4_alloc_vi(adap
, adap
->fn
, p
->tx_chan
, adap
->fn
, 0, 1,
3220 return PCI_ERS_RESULT_DISCONNECT
;
3222 p
->xact_addr_filt
= -1;
3225 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
3226 adap
->params
.b_wnd
);
3229 return PCI_ERS_RESULT_DISCONNECT
;
3230 return PCI_ERS_RESULT_RECOVERED
;
3233 static void eeh_resume(struct pci_dev
*pdev
)
3236 struct adapter
*adap
= pci_get_drvdata(pdev
);
3242 for_each_port(adap
, i
) {
3243 struct net_device
*dev
= adap
->port
[i
];
3245 if (netif_running(dev
)) {
3247 cxgb_set_rxmode(dev
);
3249 netif_device_attach(dev
);
3254 static struct pci_error_handlers cxgb4_eeh
= {
3255 .error_detected
= eeh_err_detected
,
3256 .slot_reset
= eeh_slot_reset
,
3257 .resume
= eeh_resume
,
3260 static inline bool is_10g_port(const struct link_config
*lc
)
3262 return (lc
->supported
& FW_PORT_CAP_SPEED_10G
) != 0;
3265 static inline void init_rspq(struct sge_rspq
*q
, u8 timer_idx
, u8 pkt_cnt_idx
,
3266 unsigned int size
, unsigned int iqe_size
)
3268 q
->intr_params
= QINTR_TIMER_IDX(timer_idx
) |
3269 (pkt_cnt_idx
< SGE_NCOUNTERS
? QINTR_CNT_EN
: 0);
3270 q
->pktcnt_idx
= pkt_cnt_idx
< SGE_NCOUNTERS
? pkt_cnt_idx
: 0;
3271 q
->iqe_len
= iqe_size
;
3276 * Perform default configuration of DMA queues depending on the number and type
3277 * of ports we found and the number of available CPUs. Most settings can be
3278 * modified by the admin prior to actual use.
3280 static void __devinit
cfg_queues(struct adapter
*adap
)
3282 struct sge
*s
= &adap
->sge
;
3283 int i
, q10g
= 0, n10g
= 0, qidx
= 0;
3285 for_each_port(adap
, i
)
3286 n10g
+= is_10g_port(&adap2pinfo(adap
, i
)->link_cfg
);
3289 * We default to 1 queue per non-10G port and up to # of cores queues
3293 q10g
= (MAX_ETH_QSETS
- (adap
->params
.nports
- n10g
)) / n10g
;
3294 if (q10g
> num_online_cpus())
3295 q10g
= num_online_cpus();
3297 for_each_port(adap
, i
) {
3298 struct port_info
*pi
= adap2pinfo(adap
, i
);
3300 pi
->first_qset
= qidx
;
3301 pi
->nqsets
= is_10g_port(&pi
->link_cfg
) ? q10g
: 1;
3306 s
->max_ethqsets
= qidx
; /* MSI-X may lower it later */
3308 if (is_offload(adap
)) {
3310 * For offload we use 1 queue/channel if all ports are up to 1G,
3311 * otherwise we divide all available queues amongst the channels
3312 * capped by the number of available cores.
3315 i
= min_t(int, ARRAY_SIZE(s
->ofldrxq
),
3317 s
->ofldqsets
= roundup(i
, adap
->params
.nports
);
3319 s
->ofldqsets
= adap
->params
.nports
;
3320 /* For RDMA one Rx queue per channel suffices */
3321 s
->rdmaqs
= adap
->params
.nports
;
3324 for (i
= 0; i
< ARRAY_SIZE(s
->ethrxq
); i
++) {
3325 struct sge_eth_rxq
*r
= &s
->ethrxq
[i
];
3327 init_rspq(&r
->rspq
, 0, 0, 1024, 64);
3331 for (i
= 0; i
< ARRAY_SIZE(s
->ethtxq
); i
++)
3332 s
->ethtxq
[i
].q
.size
= 1024;
3334 for (i
= 0; i
< ARRAY_SIZE(s
->ctrlq
); i
++)
3335 s
->ctrlq
[i
].q
.size
= 512;
3337 for (i
= 0; i
< ARRAY_SIZE(s
->ofldtxq
); i
++)
3338 s
->ofldtxq
[i
].q
.size
= 1024;
3340 for (i
= 0; i
< ARRAY_SIZE(s
->ofldrxq
); i
++) {
3341 struct sge_ofld_rxq
*r
= &s
->ofldrxq
[i
];
3343 init_rspq(&r
->rspq
, 0, 0, 1024, 64);
3344 r
->rspq
.uld
= CXGB4_ULD_ISCSI
;
3348 for (i
= 0; i
< ARRAY_SIZE(s
->rdmarxq
); i
++) {
3349 struct sge_ofld_rxq
*r
= &s
->rdmarxq
[i
];
3351 init_rspq(&r
->rspq
, 0, 0, 511, 64);
3352 r
->rspq
.uld
= CXGB4_ULD_RDMA
;
3356 init_rspq(&s
->fw_evtq
, 6, 0, 512, 64);
3357 init_rspq(&s
->intrq
, 6, 0, 2 * MAX_INGQ
, 64);
3361 * Reduce the number of Ethernet queues across all ports to at most n.
3362 * n provides at least one queue per port.
3364 static void __devinit
reduce_ethqs(struct adapter
*adap
, int n
)
3367 struct port_info
*pi
;
3369 while (n
< adap
->sge
.ethqsets
)
3370 for_each_port(adap
, i
) {
3371 pi
= adap2pinfo(adap
, i
);
3372 if (pi
->nqsets
> 1) {
3374 adap
->sge
.ethqsets
--;
3375 if (adap
->sge
.ethqsets
<= n
)
3381 for_each_port(adap
, i
) {
3382 pi
= adap2pinfo(adap
, i
);
3388 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
3389 #define EXTRA_VECS 2
3391 static int __devinit
enable_msix(struct adapter
*adap
)
3394 int i
, err
, want
, need
;
3395 struct sge
*s
= &adap
->sge
;
3396 unsigned int nchan
= adap
->params
.nports
;
3397 struct msix_entry entries
[MAX_INGQ
+ 1];
3399 for (i
= 0; i
< ARRAY_SIZE(entries
); ++i
)
3400 entries
[i
].entry
= i
;
3402 want
= s
->max_ethqsets
+ EXTRA_VECS
;
3403 if (is_offload(adap
)) {
3404 want
+= s
->rdmaqs
+ s
->ofldqsets
;
3405 /* need nchan for each possible ULD */
3406 ofld_need
= 2 * nchan
;
3408 need
= adap
->params
.nports
+ EXTRA_VECS
+ ofld_need
;
3410 while ((err
= pci_enable_msix(adap
->pdev
, entries
, want
)) >= need
)
3415 * Distribute available vectors to the various queue groups.
3416 * Every group gets its minimum requirement and NIC gets top
3417 * priority for leftovers.
3419 i
= want
- EXTRA_VECS
- ofld_need
;
3420 if (i
< s
->max_ethqsets
) {
3421 s
->max_ethqsets
= i
;
3422 if (i
< s
->ethqsets
)
3423 reduce_ethqs(adap
, i
);
3425 if (is_offload(adap
)) {
3426 i
= want
- EXTRA_VECS
- s
->max_ethqsets
;
3427 i
-= ofld_need
- nchan
;
3428 s
->ofldqsets
= (i
/ nchan
) * nchan
; /* round down */
3430 for (i
= 0; i
< want
; ++i
)
3431 adap
->msix_info
[i
].vec
= entries
[i
].vector
;
3433 dev_info(adap
->pdev_dev
,
3434 "only %d MSI-X vectors left, not using MSI-X\n", err
);
3440 static int __devinit
init_rss(struct adapter
*adap
)
3444 for_each_port(adap
, i
) {
3445 struct port_info
*pi
= adap2pinfo(adap
, i
);
3447 pi
->rss
= kcalloc(pi
->rss_size
, sizeof(u16
), GFP_KERNEL
);
3450 for (j
= 0; j
< pi
->rss_size
; j
++)
3451 pi
->rss
[j
] = j
% pi
->nqsets
;
3456 static void __devinit
print_port_info(const struct net_device
*dev
)
3458 static const char *base
[] = {
3459 "R XFI", "R XAUI", "T SGMII", "T XFI", "T XAUI", "KX4", "CX4",
3460 "KX", "KR", "R SFP+", "KR/KX", "KR/KX/KX4"
3465 const char *spd
= "";
3466 const struct port_info
*pi
= netdev_priv(dev
);
3467 const struct adapter
*adap
= pi
->adapter
;
3469 if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_2_5GB
)
3471 else if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_5_0GB
)
3474 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_100M
)
3475 bufp
+= sprintf(bufp
, "100/");
3476 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_1G
)
3477 bufp
+= sprintf(bufp
, "1000/");
3478 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_10G
)
3479 bufp
+= sprintf(bufp
, "10G/");
3482 sprintf(bufp
, "BASE-%s", base
[pi
->port_type
]);
3484 netdev_info(dev
, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
3485 adap
->params
.vpd
.id
, adap
->params
.rev
, buf
,
3486 is_offload(adap
) ? "R" : "", adap
->params
.pci
.width
, spd
,
3487 (adap
->flags
& USING_MSIX
) ? " MSI-X" :
3488 (adap
->flags
& USING_MSI
) ? " MSI" : "");
3489 netdev_info(dev
, "S/N: %s, E/C: %s\n",
3490 adap
->params
.vpd
.sn
, adap
->params
.vpd
.ec
);
3493 static void __devinit
enable_pcie_relaxed_ordering(struct pci_dev
*dev
)
3498 pos
= pci_pcie_cap(dev
);
3500 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &v
);
3501 v
|= PCI_EXP_DEVCTL_RELAX_EN
;
3502 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, v
);
3507 * Free the following resources:
3508 * - memory used for tables
3511 * - resources FW is holding for us
3513 static void free_some_resources(struct adapter
*adapter
)
3517 t4_free_mem(adapter
->l2t
);
3518 t4_free_mem(adapter
->tids
.tid_tab
);
3519 disable_msi(adapter
);
3521 for_each_port(adapter
, i
)
3522 if (adapter
->port
[i
]) {
3523 kfree(adap2pinfo(adapter
, i
)->rss
);
3524 free_netdev(adapter
->port
[i
]);
3526 if (adapter
->flags
& FW_OK
)
3527 t4_fw_bye(adapter
, adapter
->fn
);
3530 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
3531 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
3532 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
3534 static int __devinit
init_one(struct pci_dev
*pdev
,
3535 const struct pci_device_id
*ent
)
3538 struct port_info
*pi
;
3539 unsigned int highdma
= 0;
3540 struct adapter
*adapter
= NULL
;
3542 printk_once(KERN_INFO
"%s - version %s\n", DRV_DESC
, DRV_VERSION
);
3544 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
3546 /* Just info, some other driver may have claimed the device. */
3547 dev_info(&pdev
->dev
, "cannot obtain PCI resources\n");
3551 /* We control everything through one PF */
3552 func
= PCI_FUNC(pdev
->devfn
);
3553 if (func
!= ent
->driver_data
) {
3554 pci_save_state(pdev
); /* to restore SR-IOV later */
3558 err
= pci_enable_device(pdev
);
3560 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3561 goto out_release_regions
;
3564 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
3565 highdma
= NETIF_F_HIGHDMA
;
3566 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
3568 dev_err(&pdev
->dev
, "unable to obtain 64-bit DMA for "
3569 "coherent allocations\n");
3570 goto out_disable_device
;
3573 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3575 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3576 goto out_disable_device
;
3580 pci_enable_pcie_error_reporting(pdev
);
3581 enable_pcie_relaxed_ordering(pdev
);
3582 pci_set_master(pdev
);
3583 pci_save_state(pdev
);
3585 adapter
= kzalloc(sizeof(*adapter
), GFP_KERNEL
);
3588 goto out_disable_device
;
3591 adapter
->regs
= pci_ioremap_bar(pdev
, 0);
3592 if (!adapter
->regs
) {
3593 dev_err(&pdev
->dev
, "cannot map device registers\n");
3595 goto out_free_adapter
;
3598 adapter
->pdev
= pdev
;
3599 adapter
->pdev_dev
= &pdev
->dev
;
3601 adapter
->msg_enable
= dflt_msg_enable
;
3602 memset(adapter
->chan_map
, 0xff, sizeof(adapter
->chan_map
));
3604 spin_lock_init(&adapter
->stats_lock
);
3605 spin_lock_init(&adapter
->tid_release_lock
);
3607 INIT_WORK(&adapter
->tid_release_task
, process_tid_release_list
);
3609 err
= t4_prep_adapter(adapter
);
3612 err
= adap_init0(adapter
);
3616 for_each_port(adapter
, i
) {
3617 struct net_device
*netdev
;
3619 netdev
= alloc_etherdev_mq(sizeof(struct port_info
),
3626 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3628 adapter
->port
[i
] = netdev
;
3629 pi
= netdev_priv(netdev
);
3630 pi
->adapter
= adapter
;
3631 pi
->xact_addr_filt
= -1;
3633 netdev
->irq
= pdev
->irq
;
3635 netdev
->hw_features
= NETIF_F_SG
| TSO_FLAGS
|
3636 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3637 NETIF_F_RXCSUM
| NETIF_F_RXHASH
|
3638 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3639 netdev
->features
|= netdev
->hw_features
| highdma
;
3640 netdev
->vlan_features
= netdev
->features
& VLAN_FEAT
;
3642 netdev
->netdev_ops
= &cxgb4_netdev_ops
;
3643 SET_ETHTOOL_OPS(netdev
, &cxgb_ethtool_ops
);
3646 pci_set_drvdata(pdev
, adapter
);
3648 if (adapter
->flags
& FW_OK
) {
3649 err
= t4_port_init(adapter
, func
, func
, 0);
3655 * Configure queues and allocate tables now, they can be needed as
3656 * soon as the first register_netdev completes.
3658 cfg_queues(adapter
);
3660 adapter
->l2t
= t4_init_l2t();
3661 if (!adapter
->l2t
) {
3662 /* We tolerate a lack of L2T, giving up some functionality */
3663 dev_warn(&pdev
->dev
, "could not allocate L2T, continuing\n");
3664 adapter
->params
.offload
= 0;
3667 if (is_offload(adapter
) && tid_init(&adapter
->tids
) < 0) {
3668 dev_warn(&pdev
->dev
, "could not allocate TID table, "
3670 adapter
->params
.offload
= 0;
3673 /* See what interrupts we'll be using */
3674 if (msi
> 1 && enable_msix(adapter
) == 0)
3675 adapter
->flags
|= USING_MSIX
;
3676 else if (msi
> 0 && pci_enable_msi(pdev
) == 0)
3677 adapter
->flags
|= USING_MSI
;
3679 err
= init_rss(adapter
);
3684 * The card is now ready to go. If any errors occur during device
3685 * registration we do not fail the whole card but rather proceed only
3686 * with the ports we manage to register successfully. However we must
3687 * register at least one net device.
3689 for_each_port(adapter
, i
) {
3690 pi
= adap2pinfo(adapter
, i
);
3691 netif_set_real_num_tx_queues(adapter
->port
[i
], pi
->nqsets
);
3692 netif_set_real_num_rx_queues(adapter
->port
[i
], pi
->nqsets
);
3694 err
= register_netdev(adapter
->port
[i
]);
3697 adapter
->chan_map
[pi
->tx_chan
] = i
;
3698 print_port_info(adapter
->port
[i
]);
3701 dev_err(&pdev
->dev
, "could not register any net devices\n");
3705 dev_warn(&pdev
->dev
, "only %d net devices registered\n", i
);
3709 if (cxgb4_debugfs_root
) {
3710 adapter
->debugfs_root
= debugfs_create_dir(pci_name(pdev
),
3711 cxgb4_debugfs_root
);
3712 setup_debugfs(adapter
);
3715 if (is_offload(adapter
))
3716 attach_ulds(adapter
);
3719 #ifdef CONFIG_PCI_IOV
3720 if (func
< ARRAY_SIZE(num_vf
) && num_vf
[func
] > 0)
3721 if (pci_enable_sriov(pdev
, num_vf
[func
]) == 0)
3722 dev_info(&pdev
->dev
,
3723 "instantiated %u virtual functions\n",
3729 free_some_resources(adapter
);
3731 iounmap(adapter
->regs
);
3735 pci_disable_pcie_error_reporting(pdev
);
3736 pci_disable_device(pdev
);
3737 out_release_regions
:
3738 pci_release_regions(pdev
);
3739 pci_set_drvdata(pdev
, NULL
);
3743 static void __devexit
remove_one(struct pci_dev
*pdev
)
3745 struct adapter
*adapter
= pci_get_drvdata(pdev
);
3747 pci_disable_sriov(pdev
);
3752 if (is_offload(adapter
))
3753 detach_ulds(adapter
);
3755 for_each_port(adapter
, i
)
3756 if (adapter
->port
[i
]->reg_state
== NETREG_REGISTERED
)
3757 unregister_netdev(adapter
->port
[i
]);
3759 if (adapter
->debugfs_root
)
3760 debugfs_remove_recursive(adapter
->debugfs_root
);
3762 if (adapter
->flags
& FULL_INIT_DONE
)
3765 free_some_resources(adapter
);
3766 iounmap(adapter
->regs
);
3768 pci_disable_pcie_error_reporting(pdev
);
3769 pci_disable_device(pdev
);
3770 pci_release_regions(pdev
);
3771 pci_set_drvdata(pdev
, NULL
);
3773 pci_release_regions(pdev
);
3776 static struct pci_driver cxgb4_driver
= {
3777 .name
= KBUILD_MODNAME
,
3778 .id_table
= cxgb4_pci_tbl
,
3780 .remove
= __devexit_p(remove_one
),
3781 .err_handler
= &cxgb4_eeh
,
3784 static int __init
cxgb4_init_module(void)
3788 /* Debugfs support is optional, just warn if this fails */
3789 cxgb4_debugfs_root
= debugfs_create_dir(KBUILD_MODNAME
, NULL
);
3790 if (!cxgb4_debugfs_root
)
3791 pr_warning("could not create debugfs entry, continuing\n");
3793 ret
= pci_register_driver(&cxgb4_driver
);
3795 debugfs_remove(cxgb4_debugfs_root
);
3799 static void __exit
cxgb4_cleanup_module(void)
3801 pci_unregister_driver(&cxgb4_driver
);
3802 debugfs_remove(cxgb4_debugfs_root
); /* NULL ok */
3805 module_init(cxgb4_init_module
);
3806 module_exit(cxgb4_cleanup_module
);