2 * Driver for ICPlus PHYs
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/errno.h>
15 #include <linux/unistd.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/netdevice.h>
20 #include <linux/etherdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/spinlock.h>
24 #include <linux/module.h>
25 #include <linux/mii.h>
26 #include <linux/ethtool.h>
27 #include <linux/phy.h>
31 #include <asm/uaccess.h>
33 MODULE_DESCRIPTION("ICPlus IP175C/IC1001 PHY drivers");
34 MODULE_AUTHOR("Michael Barkowski");
35 MODULE_LICENSE("GPL");
37 static int ip175c_config_init(struct phy_device
*phydev
)
40 static int full_reset_performed
= 0;
42 if (full_reset_performed
== 0) {
45 err
= phydev
->bus
->write(phydev
->bus
, 30, 0, 0x175c);
49 /* ensure no bus delays overlap reset period */
50 err
= phydev
->bus
->read(phydev
->bus
, 30, 0);
52 /* data sheet specifies reset period is 2 msec */
55 /* enable IP175C mode */
56 err
= phydev
->bus
->write(phydev
->bus
, 29, 31, 0x175c);
60 /* Set MII0 speed and duplex (in PHY mode) */
61 err
= phydev
->bus
->write(phydev
->bus
, 29, 22, 0x420);
65 /* reset switch ports */
66 for (i
= 0; i
< 5; i
++) {
67 err
= phydev
->bus
->write(phydev
->bus
, i
,
68 MII_BMCR
, BMCR_RESET
);
73 for (i
= 0; i
< 5; i
++)
74 err
= phydev
->bus
->read(phydev
->bus
, i
, MII_BMCR
);
78 full_reset_performed
= 1;
81 if (phydev
->addr
!= 4) {
82 phydev
->state
= PHY_RUNNING
;
83 phydev
->speed
= SPEED_100
;
84 phydev
->duplex
= DUPLEX_FULL
;
86 netif_carrier_on(phydev
->attached_dev
);
92 static int ip1001_config_init(struct phy_device
*phydev
)
96 /* Software Reset PHY */
97 value
= phy_read(phydev
, MII_BMCR
);
99 err
= phy_write(phydev
, MII_BMCR
, value
);
104 value
= phy_read(phydev
, MII_BMCR
);
105 } while (value
& BMCR_RESET
);
107 /* Additional delay (2ns) used to adjust RX clock phase
108 * at GMII/ RGMII interface */
109 value
= phy_read(phydev
, 16);
112 return phy_write(phydev
, 16, value
);
115 static int ip175c_read_status(struct phy_device
*phydev
)
117 if (phydev
->addr
== 4) /* WAN port */
118 genphy_read_status(phydev
);
120 /* Don't need to read status for switch ports */
121 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
126 static int ip175c_config_aneg(struct phy_device
*phydev
)
128 if (phydev
->addr
== 4) /* WAN port */
129 genphy_config_aneg(phydev
);
134 static struct phy_driver ip175c_driver
= {
135 .phy_id
= 0x02430d80,
136 .name
= "ICPlus IP175C",
137 .phy_id_mask
= 0x0ffffff0,
138 .features
= PHY_BASIC_FEATURES
,
139 .config_init
= &ip175c_config_init
,
140 .config_aneg
= &ip175c_config_aneg
,
141 .read_status
= &ip175c_read_status
,
142 .suspend
= genphy_suspend
,
143 .resume
= genphy_resume
,
144 .driver
= { .owner
= THIS_MODULE
,},
147 static struct phy_driver ip1001_driver
= {
148 .phy_id
= 0x02430d90,
149 .name
= "ICPlus IP1001",
150 .phy_id_mask
= 0x0ffffff0,
151 .features
= PHY_GBIT_FEATURES
| SUPPORTED_Pause
|
152 SUPPORTED_Asym_Pause
,
153 .config_init
= &ip1001_config_init
,
154 .config_aneg
= &genphy_config_aneg
,
155 .read_status
= &genphy_read_status
,
156 .suspend
= genphy_suspend
,
157 .resume
= genphy_resume
,
158 .driver
= { .owner
= THIS_MODULE
,},
161 static int __init
icplus_init(void)
165 ret
= phy_driver_register(&ip1001_driver
);
169 return phy_driver_register(&ip175c_driver
);
172 static void __exit
icplus_exit(void)
174 phy_driver_unregister(&ip1001_driver
);
175 phy_driver_unregister(&ip175c_driver
);
178 module_init(icplus_init
);
179 module_exit(icplus_exit
);
181 static struct mdio_device_id __maybe_unused icplus_tbl
[] = {
182 { 0x02430d80, 0x0ffffff0 },
183 { 0x02430d90, 0x0ffffff0 },
187 MODULE_DEVICE_TABLE(mdio
, icplus_tbl
);