1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
28 #include "workarounds.h"
30 /* Hardware control for SFC4000 (aka Falcon). */
32 static const unsigned int
33 /* "Large" EEPROM device: Atmel AT25640 or similar
34 * 8 KB, 16-bit address, 32 B write block */
35 large_eeprom_type
= ((13 << SPI_DEV_TYPE_SIZE_LBN
)
36 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
37 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
)),
38 /* Default flash device: Atmel AT25F1024
39 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
40 default_flash_type
= ((17 << SPI_DEV_TYPE_SIZE_LBN
)
41 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
42 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN
)
43 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN
)
44 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
));
46 /**************************************************************************
48 * I2C bus - this is a bit-bashing interface using GPIO pins
49 * Note that it uses the output enables to tristate the outputs
50 * SDA is the data pin and SCL is the clock
52 **************************************************************************
54 static void falcon_setsda(void *data
, int state
)
56 struct efx_nic
*efx
= (struct efx_nic
*)data
;
59 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
60 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO3_OEN
, !state
);
61 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
64 static void falcon_setscl(void *data
, int state
)
66 struct efx_nic
*efx
= (struct efx_nic
*)data
;
69 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
70 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO0_OEN
, !state
);
71 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
74 static int falcon_getsda(void *data
)
76 struct efx_nic
*efx
= (struct efx_nic
*)data
;
79 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
80 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO3_IN
);
83 static int falcon_getscl(void *data
)
85 struct efx_nic
*efx
= (struct efx_nic
*)data
;
88 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
89 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO0_IN
);
92 static struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
93 .setsda
= falcon_setsda
,
94 .setscl
= falcon_setscl
,
95 .getsda
= falcon_getsda
,
96 .getscl
= falcon_getscl
,
98 /* Wait up to 50 ms for slave to let us pull SCL high */
99 .timeout
= DIV_ROUND_UP(HZ
, 20),
102 static void falcon_push_irq_moderation(struct efx_channel
*channel
)
104 efx_dword_t timer_cmd
;
105 struct efx_nic
*efx
= channel
->efx
;
107 /* Set timer register */
108 if (channel
->irq_moderation
) {
109 EFX_POPULATE_DWORD_2(timer_cmd
,
110 FRF_AB_TC_TIMER_MODE
,
111 FFE_BB_TIMER_MODE_INT_HLDOFF
,
113 channel
->irq_moderation
- 1);
115 EFX_POPULATE_DWORD_2(timer_cmd
,
116 FRF_AB_TC_TIMER_MODE
,
117 FFE_BB_TIMER_MODE_DIS
,
118 FRF_AB_TC_TIMER_VAL
, 0);
120 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER
!= FR_BZ_TIMER_COMMAND_P0
);
121 efx_writed_page_locked(efx
, &timer_cmd
, FR_BZ_TIMER_COMMAND_P0
,
125 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
);
127 static void falcon_prepare_flush(struct efx_nic
*efx
)
129 falcon_deconfigure_mac_wrapper(efx
);
131 /* Wait for the tx and rx fifo's to get to the next packet boundary
132 * (~1ms without back-pressure), then to drain the remainder of the
133 * fifo's at data path speeds (negligible), with a healthy margin. */
137 /* Acknowledge a legacy interrupt from Falcon
139 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
141 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
142 * BIU. Interrupt acknowledge is read sensitive so must write instead
143 * (then read to ensure the BIU collector is flushed)
145 * NB most hardware supports MSI interrupts
147 inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
151 EFX_POPULATE_DWORD_1(reg
, FRF_AA_INT_ACK_KER_FIELD
, 0xb7eb7e);
152 efx_writed(efx
, ®
, FR_AA_INT_ACK_KER
);
153 efx_readd(efx
, ®
, FR_AA_WORK_AROUND_BROKEN_PCI_READS
);
157 irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
159 struct efx_nic
*efx
= dev_id
;
160 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
164 /* Check to see if this is our interrupt. If it isn't, we
165 * exit without having touched the hardware.
167 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
168 netif_vdbg(efx
, intr
, efx
->net_dev
,
169 "IRQ %d on CPU %d not for me\n", irq
,
170 raw_smp_processor_id());
173 efx
->last_irq_cpu
= raw_smp_processor_id();
174 netif_vdbg(efx
, intr
, efx
->net_dev
,
175 "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
176 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
178 /* Determine interrupting queues, clear interrupt status
179 * register and acknowledge the device interrupt.
181 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH
> EFX_MAX_CHANNELS
);
182 queues
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_INT_Q
);
184 /* Check to see if we have a serious error condition */
185 if (queues
& (1U << efx
->fatal_irq_level
)) {
186 syserr
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_FATAL_INT
);
187 if (unlikely(syserr
))
188 return efx_nic_fatal_interrupt(efx
);
191 EFX_ZERO_OWORD(*int_ker
);
192 wmb(); /* Ensure the vector is cleared before interrupt ack */
193 falcon_irq_ack_a1(efx
);
196 efx_schedule_channel(efx_get_channel(efx
, 0));
198 efx_schedule_channel(efx_get_channel(efx
, 1));
201 /**************************************************************************
205 **************************************************************************
208 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
210 static int falcon_spi_poll(struct efx_nic
*efx
)
213 efx_reado(efx
, ®
, FR_AB_EE_SPI_HCMD
);
214 return EFX_OWORD_FIELD(reg
, FRF_AB_EE_SPI_HCMD_CMD_EN
) ? -EBUSY
: 0;
217 /* Wait for SPI command completion */
218 static int falcon_spi_wait(struct efx_nic
*efx
)
220 /* Most commands will finish quickly, so we start polling at
221 * very short intervals. Sometimes the command may have to
222 * wait for VPD or expansion ROM access outside of our
223 * control, so we allow up to 100 ms. */
224 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 10);
227 for (i
= 0; i
< 10; i
++) {
228 if (!falcon_spi_poll(efx
))
234 if (!falcon_spi_poll(efx
))
236 if (time_after_eq(jiffies
, timeout
)) {
237 netif_err(efx
, hw
, efx
->net_dev
,
238 "timed out waiting for SPI\n");
241 schedule_timeout_uninterruptible(1);
245 int falcon_spi_cmd(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
246 unsigned int command
, int address
,
247 const void *in
, void *out
, size_t len
)
249 bool addressed
= (address
>= 0);
250 bool reading
= (out
!= NULL
);
254 /* Input validation */
255 if (len
> FALCON_SPI_MAX_LEN
)
258 /* Check that previous command is not still running */
259 rc
= falcon_spi_poll(efx
);
263 /* Program address register, if we have an address */
265 EFX_POPULATE_OWORD_1(reg
, FRF_AB_EE_SPI_HADR_ADR
, address
);
266 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HADR
);
269 /* Program data register, if we have data */
271 memcpy(®
, in
, len
);
272 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HDATA
);
275 /* Issue read/write command */
276 EFX_POPULATE_OWORD_7(reg
,
277 FRF_AB_EE_SPI_HCMD_CMD_EN
, 1,
278 FRF_AB_EE_SPI_HCMD_SF_SEL
, spi
->device_id
,
279 FRF_AB_EE_SPI_HCMD_DABCNT
, len
,
280 FRF_AB_EE_SPI_HCMD_READ
, reading
,
281 FRF_AB_EE_SPI_HCMD_DUBCNT
, 0,
282 FRF_AB_EE_SPI_HCMD_ADBCNT
,
283 (addressed
? spi
->addr_len
: 0),
284 FRF_AB_EE_SPI_HCMD_ENC
, command
);
285 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HCMD
);
287 /* Wait for read/write to complete */
288 rc
= falcon_spi_wait(efx
);
294 efx_reado(efx
, ®
, FR_AB_EE_SPI_HDATA
);
295 memcpy(out
, ®
, len
);
302 falcon_spi_write_limit(const struct efx_spi_device
*spi
, size_t start
)
304 return min(FALCON_SPI_MAX_LEN
,
305 (spi
->block_size
- (start
& (spi
->block_size
- 1))));
309 efx_spi_munge_command(const struct efx_spi_device
*spi
,
310 const u8 command
, const unsigned int address
)
312 return command
| (((address
>> 8) & spi
->munge_address
) << 3);
315 /* Wait up to 10 ms for buffered write completion */
317 falcon_spi_wait_write(struct efx_nic
*efx
, const struct efx_spi_device
*spi
)
319 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 100);
324 rc
= falcon_spi_cmd(efx
, spi
, SPI_RDSR
, -1, NULL
,
325 &status
, sizeof(status
));
328 if (!(status
& SPI_STATUS_NRDY
))
330 if (time_after_eq(jiffies
, timeout
)) {
331 netif_err(efx
, hw
, efx
->net_dev
,
332 "SPI write timeout on device %d"
333 " last status=0x%02x\n",
334 spi
->device_id
, status
);
337 schedule_timeout_uninterruptible(1);
341 int falcon_spi_read(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
342 loff_t start
, size_t len
, size_t *retlen
, u8
*buffer
)
344 size_t block_len
, pos
= 0;
345 unsigned int command
;
349 block_len
= min(len
- pos
, FALCON_SPI_MAX_LEN
);
351 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
352 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
, NULL
,
353 buffer
+ pos
, block_len
);
358 /* Avoid locking up the system */
360 if (signal_pending(current
)) {
372 falcon_spi_write(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
373 loff_t start
, size_t len
, size_t *retlen
, const u8
*buffer
)
375 u8 verify_buffer
[FALCON_SPI_MAX_LEN
];
376 size_t block_len
, pos
= 0;
377 unsigned int command
;
381 rc
= falcon_spi_cmd(efx
, spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
385 block_len
= min(len
- pos
,
386 falcon_spi_write_limit(spi
, start
+ pos
));
387 command
= efx_spi_munge_command(spi
, SPI_WRITE
, start
+ pos
);
388 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
389 buffer
+ pos
, NULL
, block_len
);
393 rc
= falcon_spi_wait_write(efx
, spi
);
397 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
398 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
399 NULL
, verify_buffer
, block_len
);
400 if (memcmp(verify_buffer
, buffer
+ pos
, block_len
)) {
407 /* Avoid locking up the system */
409 if (signal_pending(current
)) {
420 /**************************************************************************
424 **************************************************************************
427 static void falcon_push_multicast_hash(struct efx_nic
*efx
)
429 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
431 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
433 efx_writeo(efx
, &mc_hash
->oword
[0], FR_AB_MAC_MC_HASH_REG0
);
434 efx_writeo(efx
, &mc_hash
->oword
[1], FR_AB_MAC_MC_HASH_REG1
);
437 static void falcon_reset_macs(struct efx_nic
*efx
)
439 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
440 efx_oword_t reg
, mac_ctrl
;
443 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) {
444 /* It's not safe to use GLB_CTL_REG to reset the
445 * macs, so instead use the internal MAC resets
447 EFX_POPULATE_OWORD_1(reg
, FRF_AB_XM_CORE_RST
, 1);
448 efx_writeo(efx
, ®
, FR_AB_XM_GLB_CFG
);
450 for (count
= 0; count
< 10000; count
++) {
451 efx_reado(efx
, ®
, FR_AB_XM_GLB_CFG
);
452 if (EFX_OWORD_FIELD(reg
, FRF_AB_XM_CORE_RST
) ==
458 netif_err(efx
, hw
, efx
->net_dev
,
459 "timed out waiting for XMAC core reset\n");
462 /* Mac stats will fail whist the TX fifo is draining */
463 WARN_ON(nic_data
->stats_disable_count
== 0);
465 efx_reado(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
466 EFX_SET_OWORD_FIELD(mac_ctrl
, FRF_BB_TXFIFO_DRAIN_EN
, 1);
467 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
469 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
470 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
, 1);
471 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
, 1);
472 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_EM
, 1);
473 efx_writeo(efx
, ®
, FR_AB_GLB_CTL
);
477 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
478 if (!EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
) &&
479 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
) &&
480 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_EM
)) {
481 netif_dbg(efx
, hw
, efx
->net_dev
,
482 "Completed MAC reset after %d loops\n",
487 netif_err(efx
, hw
, efx
->net_dev
, "MAC reset failed\n");
494 /* Ensure the correct MAC is selected before statistics
495 * are re-enabled by the caller */
496 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
498 falcon_setup_xaui(efx
);
501 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
505 if ((efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) ||
506 (efx
->loopback_mode
!= LOOPBACK_NONE
))
509 efx_reado(efx
, ®
, FR_AB_MAC_CTRL
);
510 /* There is no point in draining more than once */
511 if (EFX_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
))
514 falcon_reset_macs(efx
);
517 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
521 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
)
524 /* Isolate the MAC -> RX */
525 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
526 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 0);
527 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
529 /* Isolate TX -> MAC */
530 falcon_drain_tx_fifo(efx
);
533 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
535 struct efx_link_state
*link_state
= &efx
->link_state
;
537 int link_speed
, isolate
;
539 isolate
= !!ACCESS_ONCE(efx
->reset_pending
);
541 switch (link_state
->speed
) {
542 case 10000: link_speed
= 3; break;
543 case 1000: link_speed
= 2; break;
544 case 100: link_speed
= 1; break;
545 default: link_speed
= 0; break;
547 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
548 * as advertised. Disable to ensure packets are not
549 * indefinitely held and TX queue can be flushed at any point
550 * while the link is down. */
551 EFX_POPULATE_OWORD_5(reg
,
552 FRF_AB_MAC_XOFF_VAL
, 0xffff /* max pause time */,
553 FRF_AB_MAC_BCAD_ACPT
, 1,
554 FRF_AB_MAC_UC_PROM
, efx
->promiscuous
,
555 FRF_AB_MAC_LINK_STATUS
, 1, /* always set */
556 FRF_AB_MAC_SPEED
, link_speed
);
557 /* On B0, MAC backpressure can be disabled and packets get
559 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
560 EFX_SET_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
,
561 !link_state
->up
|| isolate
);
564 efx_writeo(efx
, ®
, FR_AB_MAC_CTRL
);
566 /* Restore the multicast hash registers. */
567 falcon_push_multicast_hash(efx
);
569 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
570 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
571 * initialisation but it may read back as 0) */
572 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
573 /* Unisolate the MAC -> RX */
574 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
575 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, !isolate
);
576 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
579 static void falcon_stats_request(struct efx_nic
*efx
)
581 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
584 WARN_ON(nic_data
->stats_pending
);
585 WARN_ON(nic_data
->stats_disable_count
);
587 if (nic_data
->stats_dma_done
== NULL
)
588 return; /* no mac selected */
590 *nic_data
->stats_dma_done
= FALCON_STATS_NOT_DONE
;
591 nic_data
->stats_pending
= true;
592 wmb(); /* ensure done flag is clear */
594 /* Initiate DMA transfer of stats */
595 EFX_POPULATE_OWORD_2(reg
,
596 FRF_AB_MAC_STAT_DMA_CMD
, 1,
597 FRF_AB_MAC_STAT_DMA_ADR
,
598 efx
->stats_buffer
.dma_addr
);
599 efx_writeo(efx
, ®
, FR_AB_MAC_STAT_DMA
);
601 mod_timer(&nic_data
->stats_timer
, round_jiffies_up(jiffies
+ HZ
/ 2));
604 static void falcon_stats_complete(struct efx_nic
*efx
)
606 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
608 if (!nic_data
->stats_pending
)
611 nic_data
->stats_pending
= 0;
612 if (*nic_data
->stats_dma_done
== FALCON_STATS_DONE
) {
613 rmb(); /* read the done flag before the stats */
614 efx
->mac_op
->update_stats(efx
);
616 netif_err(efx
, hw
, efx
->net_dev
,
617 "timed out waiting for statistics\n");
621 static void falcon_stats_timer_func(unsigned long context
)
623 struct efx_nic
*efx
= (struct efx_nic
*)context
;
624 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
626 spin_lock(&efx
->stats_lock
);
628 falcon_stats_complete(efx
);
629 if (nic_data
->stats_disable_count
== 0)
630 falcon_stats_request(efx
);
632 spin_unlock(&efx
->stats_lock
);
635 static bool falcon_loopback_link_poll(struct efx_nic
*efx
)
637 struct efx_link_state old_state
= efx
->link_state
;
639 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
640 WARN_ON(!LOOPBACK_INTERNAL(efx
));
642 efx
->link_state
.fd
= true;
643 efx
->link_state
.fc
= efx
->wanted_fc
;
644 efx
->link_state
.up
= true;
645 efx
->link_state
.speed
= 10000;
647 return !efx_link_state_equal(&efx
->link_state
, &old_state
);
650 static int falcon_reconfigure_port(struct efx_nic
*efx
)
654 WARN_ON(efx_nic_rev(efx
) > EFX_REV_FALCON_B0
);
656 /* Poll the PHY link state *before* reconfiguring it. This means we
657 * will pick up the correct speed (in loopback) to select the correct
660 if (LOOPBACK_INTERNAL(efx
))
661 falcon_loopback_link_poll(efx
);
663 efx
->phy_op
->poll(efx
);
665 falcon_stop_nic_stats(efx
);
666 falcon_deconfigure_mac_wrapper(efx
);
668 falcon_reset_macs(efx
);
670 efx
->phy_op
->reconfigure(efx
);
671 rc
= efx
->mac_op
->reconfigure(efx
);
674 falcon_start_nic_stats(efx
);
676 /* Synchronise efx->link_state with the kernel */
677 efx_link_status_changed(efx
);
682 /**************************************************************************
684 * PHY access via GMII
686 **************************************************************************
689 /* Wait for GMII access to complete */
690 static int falcon_gmii_wait(struct efx_nic
*efx
)
695 /* wait up to 50ms - taken max from datasheet */
696 for (count
= 0; count
< 5000; count
++) {
697 efx_reado(efx
, &md_stat
, FR_AB_MD_STAT
);
698 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSY
) == 0) {
699 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_LNFL
) != 0 ||
700 EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSERR
) != 0) {
701 netif_err(efx
, hw
, efx
->net_dev
,
702 "error from GMII access "
704 EFX_OWORD_VAL(md_stat
));
711 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for GMII\n");
715 /* Write an MDIO register of a PHY connected to Falcon. */
716 static int falcon_mdio_write(struct net_device
*net_dev
,
717 int prtad
, int devad
, u16 addr
, u16 value
)
719 struct efx_nic
*efx
= netdev_priv(net_dev
);
720 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
724 netif_vdbg(efx
, hw
, efx
->net_dev
,
725 "writing MDIO %d register %d.%d with 0x%04x\n",
726 prtad
, devad
, addr
, value
);
728 mutex_lock(&nic_data
->mdio_lock
);
730 /* Check MDIO not currently being accessed */
731 rc
= falcon_gmii_wait(efx
);
735 /* Write the address/ID register */
736 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
737 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
739 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
740 FRF_AB_MD_DEV_ADR
, devad
);
741 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
744 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_TXD
, value
);
745 efx_writeo(efx
, ®
, FR_AB_MD_TXD
);
747 EFX_POPULATE_OWORD_2(reg
,
750 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
752 /* Wait for data to be written */
753 rc
= falcon_gmii_wait(efx
);
755 /* Abort the write operation */
756 EFX_POPULATE_OWORD_2(reg
,
759 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
764 mutex_unlock(&nic_data
->mdio_lock
);
768 /* Read an MDIO register of a PHY connected to Falcon. */
769 static int falcon_mdio_read(struct net_device
*net_dev
,
770 int prtad
, int devad
, u16 addr
)
772 struct efx_nic
*efx
= netdev_priv(net_dev
);
773 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
777 mutex_lock(&nic_data
->mdio_lock
);
779 /* Check MDIO not currently being accessed */
780 rc
= falcon_gmii_wait(efx
);
784 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
785 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
787 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
788 FRF_AB_MD_DEV_ADR
, devad
);
789 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
791 /* Request data to be read */
792 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_RDC
, 1, FRF_AB_MD_GC
, 0);
793 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
795 /* Wait for data to become available */
796 rc
= falcon_gmii_wait(efx
);
798 efx_reado(efx
, ®
, FR_AB_MD_RXD
);
799 rc
= EFX_OWORD_FIELD(reg
, FRF_AB_MD_RXD
);
800 netif_vdbg(efx
, hw
, efx
->net_dev
,
801 "read from MDIO %d register %d.%d, got %04x\n",
802 prtad
, devad
, addr
, rc
);
804 /* Abort the read operation */
805 EFX_POPULATE_OWORD_2(reg
,
808 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
810 netif_dbg(efx
, hw
, efx
->net_dev
,
811 "read from MDIO %d register %d.%d, got error %d\n",
812 prtad
, devad
, addr
, rc
);
816 mutex_unlock(&nic_data
->mdio_lock
);
820 /* This call is responsible for hooking in the MAC and PHY operations */
821 static int falcon_probe_port(struct efx_nic
*efx
)
823 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
826 switch (efx
->phy_type
) {
827 case PHY_TYPE_SFX7101
:
828 efx
->phy_op
= &falcon_sfx7101_phy_ops
;
830 case PHY_TYPE_QT2022C2
:
831 case PHY_TYPE_QT2025C
:
832 efx
->phy_op
= &falcon_qt202x_phy_ops
;
834 case PHY_TYPE_TXC43128
:
835 efx
->phy_op
= &falcon_txc_phy_ops
;
838 netif_err(efx
, probe
, efx
->net_dev
, "Unknown PHY type %d\n",
843 /* Fill out MDIO structure and loopback modes */
844 mutex_init(&nic_data
->mdio_lock
);
845 efx
->mdio
.mdio_read
= falcon_mdio_read
;
846 efx
->mdio
.mdio_write
= falcon_mdio_write
;
847 rc
= efx
->phy_op
->probe(efx
);
851 /* Initial assumption */
852 efx
->link_state
.speed
= 10000;
853 efx
->link_state
.fd
= true;
855 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
856 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
857 efx
->wanted_fc
= EFX_FC_RX
| EFX_FC_TX
;
859 efx
->wanted_fc
= EFX_FC_RX
;
860 if (efx
->mdio
.mmds
& MDIO_DEVS_AN
)
861 efx
->wanted_fc
|= EFX_FC_AUTO
;
863 /* Allocate buffer for stats */
864 rc
= efx_nic_alloc_buffer(efx
, &efx
->stats_buffer
,
865 FALCON_MAC_STATS_SIZE
);
868 netif_dbg(efx
, probe
, efx
->net_dev
,
869 "stats buffer at %llx (virt %p phys %llx)\n",
870 (u64
)efx
->stats_buffer
.dma_addr
,
871 efx
->stats_buffer
.addr
,
872 (u64
)virt_to_phys(efx
->stats_buffer
.addr
));
873 nic_data
->stats_dma_done
= efx
->stats_buffer
.addr
+ XgDmaDone_offset
;
878 static void falcon_remove_port(struct efx_nic
*efx
)
880 efx
->phy_op
->remove(efx
);
881 efx_nic_free_buffer(efx
, &efx
->stats_buffer
);
884 /* Global events are basically PHY events */
886 falcon_handle_global_event(struct efx_channel
*channel
, efx_qword_t
*event
)
888 struct efx_nic
*efx
= channel
->efx
;
889 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
891 if (EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_G_PHY0_INTR
) ||
892 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XG_PHY0_INTR
) ||
893 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XFP_PHY0_INTR
))
897 if ((efx_nic_rev(efx
) == EFX_REV_FALCON_B0
) &&
898 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_XG_MGT_INTR
)) {
899 nic_data
->xmac_poll_required
= true;
903 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
?
904 EFX_QWORD_FIELD(*event
, FSF_AA_GLB_EV_RX_RECOVERY
) :
905 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_RX_RECOVERY
)) {
906 netif_err(efx
, rx_err
, efx
->net_dev
,
907 "channel %d seen global RX_RESET event. Resetting.\n",
910 atomic_inc(&efx
->rx_reset
);
911 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
912 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
919 /**************************************************************************
923 **************************************************************************/
926 falcon_read_nvram(struct efx_nic
*efx
, struct falcon_nvconfig
*nvconfig_out
)
928 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
929 struct falcon_nvconfig
*nvconfig
;
930 struct efx_spi_device
*spi
;
932 int rc
, magic_num
, struct_ver
;
933 __le16
*word
, *limit
;
936 if (efx_spi_present(&nic_data
->spi_flash
))
937 spi
= &nic_data
->spi_flash
;
938 else if (efx_spi_present(&nic_data
->spi_eeprom
))
939 spi
= &nic_data
->spi_eeprom
;
943 region
= kmalloc(FALCON_NVCONFIG_END
, GFP_KERNEL
);
946 nvconfig
= region
+ FALCON_NVCONFIG_OFFSET
;
948 mutex_lock(&nic_data
->spi_lock
);
949 rc
= falcon_spi_read(efx
, spi
, 0, FALCON_NVCONFIG_END
, NULL
, region
);
950 mutex_unlock(&nic_data
->spi_lock
);
952 netif_err(efx
, hw
, efx
->net_dev
, "Failed to read %s\n",
953 efx_spi_present(&nic_data
->spi_flash
) ?
959 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
960 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
963 if (magic_num
!= FALCON_NVCONFIG_BOARD_MAGIC_NUM
) {
964 netif_err(efx
, hw
, efx
->net_dev
,
965 "NVRAM bad magic 0x%x\n", magic_num
);
968 if (struct_ver
< 2) {
969 netif_err(efx
, hw
, efx
->net_dev
,
970 "NVRAM has ancient version 0x%x\n", struct_ver
);
972 } else if (struct_ver
< 4) {
973 word
= &nvconfig
->board_magic_num
;
974 limit
= (__le16
*) (nvconfig
+ 1);
977 limit
= region
+ FALCON_NVCONFIG_END
;
979 for (csum
= 0; word
< limit
; ++word
)
980 csum
+= le16_to_cpu(*word
);
982 if (~csum
& 0xffff) {
983 netif_err(efx
, hw
, efx
->net_dev
,
984 "NVRAM has incorrect checksum\n");
990 memcpy(nvconfig_out
, nvconfig
, sizeof(*nvconfig
));
997 static int falcon_test_nvram(struct efx_nic
*efx
)
999 return falcon_read_nvram(efx
, NULL
);
1002 static const struct efx_nic_register_test falcon_b0_register_tests
[] = {
1004 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1006 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1008 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1009 { FR_AZ_TX_RESERVED
,
1010 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1012 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1013 { FR_AZ_SRM_TX_DC_CFG
,
1014 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1016 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1017 { FR_AZ_RX_DC_PF_WM
,
1018 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1020 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1022 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1024 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1026 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1028 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1030 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1031 { FR_AB_XM_RX_PARAM
,
1032 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1034 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1036 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1038 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1041 static int falcon_b0_test_registers(struct efx_nic
*efx
)
1043 return efx_nic_test_registers(efx
, falcon_b0_register_tests
,
1044 ARRAY_SIZE(falcon_b0_register_tests
));
1047 /**************************************************************************
1051 **************************************************************************
1054 static enum reset_type
falcon_map_reset_reason(enum reset_type reason
)
1057 case RESET_TYPE_RX_RECOVERY
:
1058 case RESET_TYPE_RX_DESC_FETCH
:
1059 case RESET_TYPE_TX_DESC_FETCH
:
1060 case RESET_TYPE_TX_SKIP
:
1061 /* These can occasionally occur due to hardware bugs.
1062 * We try to reset without disrupting the link.
1064 return RESET_TYPE_INVISIBLE
;
1066 return RESET_TYPE_ALL
;
1070 static int falcon_map_reset_flags(u32
*flags
)
1073 FALCON_RESET_INVISIBLE
= (ETH_RESET_DMA
| ETH_RESET_FILTER
|
1074 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
),
1075 FALCON_RESET_ALL
= FALCON_RESET_INVISIBLE
| ETH_RESET_PHY
,
1076 FALCON_RESET_WORLD
= FALCON_RESET_ALL
| ETH_RESET_IRQ
,
1079 if ((*flags
& FALCON_RESET_WORLD
) == FALCON_RESET_WORLD
) {
1080 *flags
&= ~FALCON_RESET_WORLD
;
1081 return RESET_TYPE_WORLD
;
1084 if ((*flags
& FALCON_RESET_ALL
) == FALCON_RESET_ALL
) {
1085 *flags
&= ~FALCON_RESET_ALL
;
1086 return RESET_TYPE_ALL
;
1089 if ((*flags
& FALCON_RESET_INVISIBLE
) == FALCON_RESET_INVISIBLE
) {
1090 *flags
&= ~FALCON_RESET_INVISIBLE
;
1091 return RESET_TYPE_INVISIBLE
;
1097 /* Resets NIC to known state. This routine must be called in process
1098 * context and is allowed to sleep. */
1099 static int __falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
1101 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1102 efx_oword_t glb_ctl_reg_ker
;
1105 netif_dbg(efx
, hw
, efx
->net_dev
, "performing %s hardware reset\n",
1106 RESET_TYPE(method
));
1108 /* Initiate device reset */
1109 if (method
== RESET_TYPE_WORLD
) {
1110 rc
= pci_save_state(efx
->pci_dev
);
1112 netif_err(efx
, drv
, efx
->net_dev
,
1113 "failed to backup PCI state of primary "
1114 "function prior to hardware reset\n");
1117 if (efx_nic_is_dual_func(efx
)) {
1118 rc
= pci_save_state(nic_data
->pci_dev2
);
1120 netif_err(efx
, drv
, efx
->net_dev
,
1121 "failed to backup PCI state of "
1122 "secondary function prior to "
1123 "hardware reset\n");
1128 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
1129 FRF_AB_EXT_PHY_RST_DUR
,
1130 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1133 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
1134 /* exclude PHY from "invisible" reset */
1135 FRF_AB_EXT_PHY_RST_CTL
,
1136 method
== RESET_TYPE_INVISIBLE
,
1137 /* exclude EEPROM/flash and PCIe */
1138 FRF_AB_PCIE_CORE_RST_CTL
, 1,
1139 FRF_AB_PCIE_NSTKY_RST_CTL
, 1,
1140 FRF_AB_PCIE_SD_RST_CTL
, 1,
1141 FRF_AB_EE_RST_CTL
, 1,
1142 FRF_AB_EXT_PHY_RST_DUR
,
1143 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1146 efx_writeo(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1148 netif_dbg(efx
, hw
, efx
->net_dev
, "waiting for hardware reset\n");
1149 schedule_timeout_uninterruptible(HZ
/ 20);
1151 /* Restore PCI configuration if needed */
1152 if (method
== RESET_TYPE_WORLD
) {
1153 if (efx_nic_is_dual_func(efx
))
1154 pci_restore_state(nic_data
->pci_dev2
);
1155 pci_restore_state(efx
->pci_dev
);
1156 netif_dbg(efx
, drv
, efx
->net_dev
,
1157 "successfully restored PCI config\n");
1160 /* Assert that reset complete */
1161 efx_reado(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1162 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, FRF_AB_SWRST
) != 0) {
1164 netif_err(efx
, hw
, efx
->net_dev
,
1165 "timed out waiting for hardware reset\n");
1168 netif_dbg(efx
, hw
, efx
->net_dev
, "hardware reset complete\n");
1172 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1174 pci_restore_state(efx
->pci_dev
);
1180 static int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
1182 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1185 mutex_lock(&nic_data
->spi_lock
);
1186 rc
= __falcon_reset_hw(efx
, method
);
1187 mutex_unlock(&nic_data
->spi_lock
);
1192 static void falcon_monitor(struct efx_nic
*efx
)
1197 BUG_ON(!mutex_is_locked(&efx
->mac_lock
));
1199 rc
= falcon_board(efx
)->type
->monitor(efx
);
1201 netif_err(efx
, hw
, efx
->net_dev
,
1202 "Board sensor %s; shutting down PHY\n",
1203 (rc
== -ERANGE
) ? "reported fault" : "failed");
1204 efx
->phy_mode
|= PHY_MODE_LOW_POWER
;
1205 rc
= __efx_reconfigure_port(efx
);
1209 if (LOOPBACK_INTERNAL(efx
))
1210 link_changed
= falcon_loopback_link_poll(efx
);
1212 link_changed
= efx
->phy_op
->poll(efx
);
1215 falcon_stop_nic_stats(efx
);
1216 falcon_deconfigure_mac_wrapper(efx
);
1218 falcon_reset_macs(efx
);
1219 rc
= efx
->mac_op
->reconfigure(efx
);
1222 falcon_start_nic_stats(efx
);
1224 efx_link_status_changed(efx
);
1227 falcon_poll_xmac(efx
);
1230 /* Zeroes out the SRAM contents. This routine must be called in
1231 * process context and is allowed to sleep.
1233 static int falcon_reset_sram(struct efx_nic
*efx
)
1235 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
1238 /* Set the SRAM wake/sleep GPIO appropriately. */
1239 efx_reado(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
1240 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OEN
, 1);
1241 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OUT
, 1);
1242 efx_writeo(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
1244 /* Initiate SRAM reset */
1245 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
1246 FRF_AZ_SRM_INIT_EN
, 1,
1247 FRF_AZ_SRM_NB_SZ
, 0);
1248 efx_writeo(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
1250 /* Wait for SRAM reset to complete */
1253 netif_dbg(efx
, hw
, efx
->net_dev
,
1254 "waiting for SRAM reset (attempt %d)...\n", count
);
1256 /* SRAM reset is slow; expect around 16ms */
1257 schedule_timeout_uninterruptible(HZ
/ 50);
1259 /* Check for reset complete */
1260 efx_reado(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
1261 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, FRF_AZ_SRM_INIT_EN
)) {
1262 netif_dbg(efx
, hw
, efx
->net_dev
,
1263 "SRAM reset complete\n");
1267 } while (++count
< 20); /* wait up to 0.4 sec */
1269 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for SRAM reset\n");
1273 static void falcon_spi_device_init(struct efx_nic
*efx
,
1274 struct efx_spi_device
*spi_device
,
1275 unsigned int device_id
, u32 device_type
)
1277 if (device_type
!= 0) {
1278 spi_device
->device_id
= device_id
;
1280 1 << SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_SIZE
);
1281 spi_device
->addr_len
=
1282 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ADDR_LEN
);
1283 spi_device
->munge_address
= (spi_device
->size
== 1 << 9 &&
1284 spi_device
->addr_len
== 1);
1285 spi_device
->erase_command
=
1286 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ERASE_CMD
);
1287 spi_device
->erase_size
=
1288 1 << SPI_DEV_TYPE_FIELD(device_type
,
1289 SPI_DEV_TYPE_ERASE_SIZE
);
1290 spi_device
->block_size
=
1291 1 << SPI_DEV_TYPE_FIELD(device_type
,
1292 SPI_DEV_TYPE_BLOCK_SIZE
);
1294 spi_device
->size
= 0;
1298 /* Extract non-volatile configuration */
1299 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
1301 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1302 struct falcon_nvconfig
*nvconfig
;
1305 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
1309 rc
= falcon_read_nvram(efx
, nvconfig
);
1313 efx
->phy_type
= nvconfig
->board_v2
.port0_phy_type
;
1314 efx
->mdio
.prtad
= nvconfig
->board_v2
.port0_phy_addr
;
1316 if (le16_to_cpu(nvconfig
->board_struct_ver
) >= 3) {
1317 falcon_spi_device_init(
1318 efx
, &nic_data
->spi_flash
, FFE_AB_SPI_DEVICE_FLASH
,
1319 le32_to_cpu(nvconfig
->board_v3
1320 .spi_device_type
[FFE_AB_SPI_DEVICE_FLASH
]));
1321 falcon_spi_device_init(
1322 efx
, &nic_data
->spi_eeprom
, FFE_AB_SPI_DEVICE_EEPROM
,
1323 le32_to_cpu(nvconfig
->board_v3
1324 .spi_device_type
[FFE_AB_SPI_DEVICE_EEPROM
]));
1327 /* Read the MAC addresses */
1328 memcpy(efx
->net_dev
->perm_addr
, nvconfig
->mac_address
[0], ETH_ALEN
);
1330 netif_dbg(efx
, probe
, efx
->net_dev
, "PHY is %d phy_id %d\n",
1331 efx
->phy_type
, efx
->mdio
.prtad
);
1333 rc
= falcon_probe_board(efx
,
1334 le16_to_cpu(nvconfig
->board_v2
.board_revision
));
1340 /* Probe all SPI devices on the NIC */
1341 static void falcon_probe_spi_devices(struct efx_nic
*efx
)
1343 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1344 efx_oword_t nic_stat
, gpio_ctl
, ee_vpd_cfg
;
1347 efx_reado(efx
, &gpio_ctl
, FR_AB_GPIO_CTL
);
1348 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
1349 efx_reado(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
1351 if (EFX_OWORD_FIELD(gpio_ctl
, FRF_AB_GPIO3_PWRUP_VALUE
)) {
1352 boot_dev
= (EFX_OWORD_FIELD(nic_stat
, FRF_AB_SF_PRST
) ?
1353 FFE_AB_SPI_DEVICE_FLASH
: FFE_AB_SPI_DEVICE_EEPROM
);
1354 netif_dbg(efx
, probe
, efx
->net_dev
, "Booted from %s\n",
1355 boot_dev
== FFE_AB_SPI_DEVICE_FLASH
?
1356 "flash" : "EEPROM");
1358 /* Disable VPD and set clock dividers to safe
1359 * values for initial programming. */
1361 netif_dbg(efx
, probe
, efx
->net_dev
,
1362 "Booted from internal ASIC settings;"
1363 " setting SPI config\n");
1364 EFX_POPULATE_OWORD_3(ee_vpd_cfg
, FRF_AB_EE_VPD_EN
, 0,
1365 /* 125 MHz / 7 ~= 20 MHz */
1366 FRF_AB_EE_SF_CLOCK_DIV
, 7,
1367 /* 125 MHz / 63 ~= 2 MHz */
1368 FRF_AB_EE_EE_CLOCK_DIV
, 63);
1369 efx_writeo(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
1372 mutex_init(&nic_data
->spi_lock
);
1374 if (boot_dev
== FFE_AB_SPI_DEVICE_FLASH
)
1375 falcon_spi_device_init(efx
, &nic_data
->spi_flash
,
1376 FFE_AB_SPI_DEVICE_FLASH
,
1377 default_flash_type
);
1378 if (boot_dev
== FFE_AB_SPI_DEVICE_EEPROM
)
1379 falcon_spi_device_init(efx
, &nic_data
->spi_eeprom
,
1380 FFE_AB_SPI_DEVICE_EEPROM
,
1384 static int falcon_probe_nic(struct efx_nic
*efx
)
1386 struct falcon_nic_data
*nic_data
;
1387 struct falcon_board
*board
;
1390 /* Allocate storage for hardware specific data */
1391 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
1394 efx
->nic_data
= nic_data
;
1398 if (efx_nic_fpga_ver(efx
) != 0) {
1399 netif_err(efx
, probe
, efx
->net_dev
,
1400 "Falcon FPGA not supported\n");
1404 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
1405 efx_oword_t nic_stat
;
1406 struct pci_dev
*dev
;
1407 u8 pci_rev
= efx
->pci_dev
->revision
;
1409 if ((pci_rev
== 0xff) || (pci_rev
== 0)) {
1410 netif_err(efx
, probe
, efx
->net_dev
,
1411 "Falcon rev A0 not supported\n");
1414 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
1415 if (EFX_OWORD_FIELD(nic_stat
, FRF_AB_STRAP_10G
) == 0) {
1416 netif_err(efx
, probe
, efx
->net_dev
,
1417 "Falcon rev A1 1G not supported\n");
1420 if (EFX_OWORD_FIELD(nic_stat
, FRF_AA_STRAP_PCIE
) == 0) {
1421 netif_err(efx
, probe
, efx
->net_dev
,
1422 "Falcon rev A1 PCI-X not supported\n");
1426 dev
= pci_dev_get(efx
->pci_dev
);
1427 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
1429 if (dev
->bus
== efx
->pci_dev
->bus
&&
1430 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
1431 nic_data
->pci_dev2
= dev
;
1435 if (!nic_data
->pci_dev2
) {
1436 netif_err(efx
, probe
, efx
->net_dev
,
1437 "failed to find secondary function\n");
1443 /* Now we can reset the NIC */
1444 rc
= __falcon_reset_hw(efx
, RESET_TYPE_ALL
);
1446 netif_err(efx
, probe
, efx
->net_dev
, "failed to reset NIC\n");
1450 /* Allocate memory for INT_KER */
1451 rc
= efx_nic_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
1454 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
1456 netif_dbg(efx
, probe
, efx
->net_dev
,
1457 "INT_KER at %llx (virt %p phys %llx)\n",
1458 (u64
)efx
->irq_status
.dma_addr
,
1459 efx
->irq_status
.addr
,
1460 (u64
)virt_to_phys(efx
->irq_status
.addr
));
1462 falcon_probe_spi_devices(efx
);
1464 /* Read in the non-volatile configuration */
1465 rc
= falcon_probe_nvconfig(efx
);
1468 netif_err(efx
, probe
, efx
->net_dev
, "NVRAM is invalid\n");
1472 /* Initialise I2C adapter */
1473 board
= falcon_board(efx
);
1474 board
->i2c_adap
.owner
= THIS_MODULE
;
1475 board
->i2c_data
= falcon_i2c_bit_operations
;
1476 board
->i2c_data
.data
= efx
;
1477 board
->i2c_adap
.algo_data
= &board
->i2c_data
;
1478 board
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
1479 strlcpy(board
->i2c_adap
.name
, "SFC4000 GPIO",
1480 sizeof(board
->i2c_adap
.name
));
1481 rc
= i2c_bit_add_bus(&board
->i2c_adap
);
1485 rc
= falcon_board(efx
)->type
->init(efx
);
1487 netif_err(efx
, probe
, efx
->net_dev
,
1488 "failed to initialise board\n");
1492 nic_data
->stats_disable_count
= 1;
1493 setup_timer(&nic_data
->stats_timer
, &falcon_stats_timer_func
,
1494 (unsigned long)efx
);
1499 BUG_ON(i2c_del_adapter(&board
->i2c_adap
));
1500 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
1502 efx_nic_free_buffer(efx
, &efx
->irq_status
);
1505 if (nic_data
->pci_dev2
) {
1506 pci_dev_put(nic_data
->pci_dev2
);
1507 nic_data
->pci_dev2
= NULL
;
1511 kfree(efx
->nic_data
);
1515 static void falcon_init_rx_cfg(struct efx_nic
*efx
)
1517 /* Prior to Siena the RX DMA engine will split each frame at
1518 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1519 * be so large that that never happens. */
1520 const unsigned huge_buf_size
= (3 * 4096) >> 5;
1521 /* RX control FIFO thresholds (32 entries) */
1522 const unsigned ctrl_xon_thr
= 20;
1523 const unsigned ctrl_xoff_thr
= 25;
1526 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
1527 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
1528 /* Data FIFO size is 5.5K */
1529 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_DESC_PUSH_EN
, 0);
1530 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_USR_BUF_SIZE
,
1532 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_MAC_TH
, 512 >> 8);
1533 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_MAC_TH
, 2048 >> 8);
1534 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_TX_TH
, ctrl_xon_thr
);
1535 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
1537 /* Data FIFO size is 80K; register fields moved */
1538 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_DESC_PUSH_EN
, 0);
1539 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_USR_BUF_SIZE
,
1541 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
1542 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_MAC_TH
, 27648 >> 8);
1543 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_MAC_TH
, 54272 >> 8);
1544 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_TX_TH
, ctrl_xon_thr
);
1545 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
1546 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 1);
1548 /* Enable hash insertion. This is broken for the
1549 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1551 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_INSRT_HDR
, 1);
1552 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_ALG
, 1);
1553 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_IP_HASH
, 1);
1555 /* Always enable XOFF signal from RX FIFO. We enable
1556 * or disable transmission of pause frames at the MAC. */
1557 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
1558 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
1561 /* This call performs hardware-specific global initialisation, such as
1562 * defining the descriptor cache sizes and number of RSS channels.
1563 * It does not set up any buffers, descriptor rings or event queues.
1565 static int falcon_init_nic(struct efx_nic
*efx
)
1570 /* Use on-chip SRAM */
1571 efx_reado(efx
, &temp
, FR_AB_NIC_STAT
);
1572 EFX_SET_OWORD_FIELD(temp
, FRF_AB_ONCHIP_SRAM
, 1);
1573 efx_writeo(efx
, &temp
, FR_AB_NIC_STAT
);
1575 rc
= falcon_reset_sram(efx
);
1579 /* Clear the parity enables on the TX data fifos as
1580 * they produce false parity errors because of timing issues
1582 if (EFX_WORKAROUND_5129(efx
)) {
1583 efx_reado(efx
, &temp
, FR_AZ_CSR_SPARE
);
1584 EFX_SET_OWORD_FIELD(temp
, FRF_AB_MEM_PERR_EN_TX_DATA
, 0);
1585 efx_writeo(efx
, &temp
, FR_AZ_CSR_SPARE
);
1588 if (EFX_WORKAROUND_7244(efx
)) {
1589 efx_reado(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
1590 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_FULL_SRCH_LIMIT
, 8);
1591 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_WILD_SRCH_LIMIT
, 8);
1592 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_FULL_SRCH_LIMIT
, 8);
1593 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_WILD_SRCH_LIMIT
, 8);
1594 efx_writeo(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
1597 /* XXX This is documented only for Falcon A0/A1 */
1598 /* Setup RX. Wait for descriptor is broken and must
1599 * be disabled. RXDP recovery shouldn't be needed, but is.
1601 efx_reado(efx
, &temp
, FR_AA_RX_SELF_RST
);
1602 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_NODESC_WAIT_DIS
, 1);
1603 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_SELF_RST_EN
, 1);
1604 if (EFX_WORKAROUND_5583(efx
))
1605 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_ISCSI_DIS
, 1);
1606 efx_writeo(efx
, &temp
, FR_AA_RX_SELF_RST
);
1608 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1609 * descriptors (which is bad).
1611 efx_reado(efx
, &temp
, FR_AZ_TX_CFG
);
1612 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_NO_EOP_DISC_EN
, 0);
1613 efx_writeo(efx
, &temp
, FR_AZ_TX_CFG
);
1615 falcon_init_rx_cfg(efx
);
1617 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
1618 /* Set hash key for IPv4 */
1619 memcpy(&temp
, efx
->rx_hash_key
, sizeof(temp
));
1620 efx_writeo(efx
, &temp
, FR_BZ_RX_RSS_TKEY
);
1622 /* Set destination of both TX and RX Flush events */
1623 EFX_POPULATE_OWORD_1(temp
, FRF_BZ_FLS_EVQ_ID
, 0);
1624 efx_writeo(efx
, &temp
, FR_BZ_DP_CTRL
);
1627 efx_nic_init_common(efx
);
1632 static void falcon_remove_nic(struct efx_nic
*efx
)
1634 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1635 struct falcon_board
*board
= falcon_board(efx
);
1638 board
->type
->fini(efx
);
1640 /* Remove I2C adapter and clear it in preparation for a retry */
1641 rc
= i2c_del_adapter(&board
->i2c_adap
);
1643 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
1645 efx_nic_free_buffer(efx
, &efx
->irq_status
);
1647 __falcon_reset_hw(efx
, RESET_TYPE_ALL
);
1649 /* Release the second function after the reset */
1650 if (nic_data
->pci_dev2
) {
1651 pci_dev_put(nic_data
->pci_dev2
);
1652 nic_data
->pci_dev2
= NULL
;
1655 /* Tear down the private nic state */
1656 kfree(efx
->nic_data
);
1657 efx
->nic_data
= NULL
;
1660 static void falcon_update_nic_stats(struct efx_nic
*efx
)
1662 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1665 if (nic_data
->stats_disable_count
)
1668 efx_reado(efx
, &cnt
, FR_AZ_RX_NODESC_DROP
);
1669 efx
->n_rx_nodesc_drop_cnt
+=
1670 EFX_OWORD_FIELD(cnt
, FRF_AB_RX_NODESC_DROP_CNT
);
1672 if (nic_data
->stats_pending
&&
1673 *nic_data
->stats_dma_done
== FALCON_STATS_DONE
) {
1674 nic_data
->stats_pending
= false;
1675 rmb(); /* read the done flag before the stats */
1676 efx
->mac_op
->update_stats(efx
);
1680 void falcon_start_nic_stats(struct efx_nic
*efx
)
1682 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1684 spin_lock_bh(&efx
->stats_lock
);
1685 if (--nic_data
->stats_disable_count
== 0)
1686 falcon_stats_request(efx
);
1687 spin_unlock_bh(&efx
->stats_lock
);
1690 void falcon_stop_nic_stats(struct efx_nic
*efx
)
1692 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1697 spin_lock_bh(&efx
->stats_lock
);
1698 ++nic_data
->stats_disable_count
;
1699 spin_unlock_bh(&efx
->stats_lock
);
1701 del_timer_sync(&nic_data
->stats_timer
);
1703 /* Wait enough time for the most recent transfer to
1705 for (i
= 0; i
< 4 && nic_data
->stats_pending
; i
++) {
1706 if (*nic_data
->stats_dma_done
== FALCON_STATS_DONE
)
1711 spin_lock_bh(&efx
->stats_lock
);
1712 falcon_stats_complete(efx
);
1713 spin_unlock_bh(&efx
->stats_lock
);
1716 static void falcon_set_id_led(struct efx_nic
*efx
, enum efx_led_mode mode
)
1718 falcon_board(efx
)->type
->set_id_led(efx
, mode
);
1721 /**************************************************************************
1725 **************************************************************************
1728 static void falcon_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1732 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1735 static int falcon_set_wol(struct efx_nic
*efx
, u32 type
)
1742 /**************************************************************************
1744 * Revision-dependent attributes used by efx.c and nic.c
1746 **************************************************************************
1749 const struct efx_nic_type falcon_a1_nic_type
= {
1750 .probe
= falcon_probe_nic
,
1751 .remove
= falcon_remove_nic
,
1752 .init
= falcon_init_nic
,
1753 .fini
= efx_port_dummy_op_void
,
1754 .monitor
= falcon_monitor
,
1755 .map_reset_reason
= falcon_map_reset_reason
,
1756 .map_reset_flags
= falcon_map_reset_flags
,
1757 .reset
= falcon_reset_hw
,
1758 .probe_port
= falcon_probe_port
,
1759 .remove_port
= falcon_remove_port
,
1760 .handle_global_event
= falcon_handle_global_event
,
1761 .prepare_flush
= falcon_prepare_flush
,
1762 .update_stats
= falcon_update_nic_stats
,
1763 .start_stats
= falcon_start_nic_stats
,
1764 .stop_stats
= falcon_stop_nic_stats
,
1765 .set_id_led
= falcon_set_id_led
,
1766 .push_irq_moderation
= falcon_push_irq_moderation
,
1767 .push_multicast_hash
= falcon_push_multicast_hash
,
1768 .reconfigure_port
= falcon_reconfigure_port
,
1769 .get_wol
= falcon_get_wol
,
1770 .set_wol
= falcon_set_wol
,
1771 .resume_wol
= efx_port_dummy_op_void
,
1772 .test_nvram
= falcon_test_nvram
,
1773 .default_mac_ops
= &falcon_xmac_operations
,
1775 .revision
= EFX_REV_FALCON_A1
,
1776 .mem_map_size
= 0x20000,
1777 .txd_ptr_tbl_base
= FR_AA_TX_DESC_PTR_TBL_KER
,
1778 .rxd_ptr_tbl_base
= FR_AA_RX_DESC_PTR_TBL_KER
,
1779 .buf_tbl_base
= FR_AA_BUF_FULL_TBL_KER
,
1780 .evq_ptr_tbl_base
= FR_AA_EVQ_PTR_TBL_KER
,
1781 .evq_rptr_tbl_base
= FR_AA_EVQ_RPTR_KER
,
1782 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
1783 .rx_buffer_padding
= 0x24,
1784 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
1785 .phys_addr_channels
= 4,
1786 .tx_dc_base
= 0x130000,
1787 .rx_dc_base
= 0x100000,
1788 .offload_features
= NETIF_F_IP_CSUM
,
1791 const struct efx_nic_type falcon_b0_nic_type
= {
1792 .probe
= falcon_probe_nic
,
1793 .remove
= falcon_remove_nic
,
1794 .init
= falcon_init_nic
,
1795 .fini
= efx_port_dummy_op_void
,
1796 .monitor
= falcon_monitor
,
1797 .map_reset_reason
= falcon_map_reset_reason
,
1798 .map_reset_flags
= falcon_map_reset_flags
,
1799 .reset
= falcon_reset_hw
,
1800 .probe_port
= falcon_probe_port
,
1801 .remove_port
= falcon_remove_port
,
1802 .handle_global_event
= falcon_handle_global_event
,
1803 .prepare_flush
= falcon_prepare_flush
,
1804 .update_stats
= falcon_update_nic_stats
,
1805 .start_stats
= falcon_start_nic_stats
,
1806 .stop_stats
= falcon_stop_nic_stats
,
1807 .set_id_led
= falcon_set_id_led
,
1808 .push_irq_moderation
= falcon_push_irq_moderation
,
1809 .push_multicast_hash
= falcon_push_multicast_hash
,
1810 .reconfigure_port
= falcon_reconfigure_port
,
1811 .get_wol
= falcon_get_wol
,
1812 .set_wol
= falcon_set_wol
,
1813 .resume_wol
= efx_port_dummy_op_void
,
1814 .test_registers
= falcon_b0_test_registers
,
1815 .test_nvram
= falcon_test_nvram
,
1816 .default_mac_ops
= &falcon_xmac_operations
,
1818 .revision
= EFX_REV_FALCON_B0
,
1819 /* Map everything up to and including the RSS indirection
1820 * table. Don't map MSI-X table, MSI-X PBA since Linux
1821 * requires that they not be mapped. */
1822 .mem_map_size
= (FR_BZ_RX_INDIRECTION_TBL
+
1823 FR_BZ_RX_INDIRECTION_TBL_STEP
*
1824 FR_BZ_RX_INDIRECTION_TBL_ROWS
),
1825 .txd_ptr_tbl_base
= FR_BZ_TX_DESC_PTR_TBL
,
1826 .rxd_ptr_tbl_base
= FR_BZ_RX_DESC_PTR_TBL
,
1827 .buf_tbl_base
= FR_BZ_BUF_FULL_TBL
,
1828 .evq_ptr_tbl_base
= FR_BZ_EVQ_PTR_TBL
,
1829 .evq_rptr_tbl_base
= FR_BZ_EVQ_RPTR
,
1830 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
1831 .rx_buffer_hash_size
= 0x10,
1832 .rx_buffer_padding
= 0,
1833 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
1834 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
1835 * interrupt handler only supports 32
1837 .tx_dc_base
= 0x130000,
1838 .rx_dc_base
= 0x100000,
1839 .offload_features
= NETIF_F_IP_CSUM
| NETIF_F_RXHASH
| NETIF_F_NTUPLE
,