1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
33 #include <linux/pci.h>
38 #define RTL_PCI_RX_MPDU_QUEUE 0
39 #define RTL_PCI_RX_CMD_QUEUE 1
40 #define RTL_PCI_MAX_RX_QUEUE 2
42 #define RTL_PCI_MAX_RX_COUNT 64
43 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9
45 #define RT_TXDESC_NUM 128
46 #define RT_TXDESC_NUM_BE_QUEUE 256
52 #define BEACON_QUEUE 4
58 #define RTL_PCI_DEVICE(vend, dev, cfg) \
61 .subvendor = PCI_ANY_ID, \
62 .subdevice = PCI_ANY_ID,\
63 .driver_data = (kernel_ulong_t)&(cfg)
65 #define PCI_MAX_BRIDGE_NUMBER 255
66 #define PCI_MAX_DEVICES 32
67 #define PCI_MAX_FUNCTION 8
69 #define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
70 #define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
72 #define U1DONTCARE 0xFF
73 #define U2DONTCARE 0xFFFF
74 #define U4DONTCARE 0xFFFFFFFF
76 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
77 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
78 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */
79 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
80 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
81 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
82 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
83 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
84 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
85 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
86 #define RTL_PCI_700F_DID 0x700F
87 #define RTL_PCI_701F_DID 0x701F
88 #define RTL_PCI_DLINK_DID 0x3304
89 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
90 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
91 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
92 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
93 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
94 #define RTL_PCI_8192DE_DID 0x8193 /*8192de */
95 #define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
97 /*8192 support 16 pages of IO registers*/
98 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
99 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
100 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
101 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
102 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
104 #define RTL_PCI_REVISION_ID_8190PCI 0x00
105 #define RTL_PCI_REVISION_ID_8192PCIE 0x01
106 #define RTL_PCI_REVISION_ID_8192SE 0x10
107 #define RTL_PCI_REVISION_ID_8192CE 0x1
108 #define RTL_PCI_REVISION_ID_8192DE 0x0
110 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
112 enum pci_bridge_vendor
{
113 PCI_BRIDGE_VENDOR_INTEL
= 0x0, /*0b'0000,0001 */
114 PCI_BRIDGE_VENDOR_ATI
, /*0b'0000,0010*/
115 PCI_BRIDGE_VENDOR_AMD
, /*0b'0000,0100*/
116 PCI_BRIDGE_VENDOR_SIS
, /*0b'0000,1000*/
117 PCI_BRIDGE_VENDOR_UNKNOWN
, /*0b'0100,0000*/
118 PCI_BRIDGE_VENDOR_MAX
,
121 struct rtl_pci_capabilities_header
{
134 struct rtl_tx_cmd_desc
{
138 struct rtl8192_tx_ring
{
139 struct rtl_tx_desc
*desc
;
142 unsigned int entries
;
143 struct sk_buff_head queue
;
146 struct rtl8192_rx_ring
{
147 struct rtl_rx_desc
*desc
;
150 struct sk_buff
*rx_buf
[RTL_PCI_MAX_RX_COUNT
];
154 struct pci_dev
*pdev
;
156 bool driver_is_goingto_unload
;
159 bool being_init_adapter
;
163 struct rtl8192_tx_ring tx_ring
[RTL_PCI_MAX_TX_QUEUE_COUNT
];
164 int txringcount
[RTL_PCI_MAX_TX_QUEUE_COUNT
];
168 struct rtl8192_rx_ring rx_ring
[RTL_PCI_MAX_RX_QUEUE
];
177 /*Bcn control register setting */
178 u32 reg_bcn_ctrl_val
;
180 /*ASPM*/ u8 const_pci_aspm
;
181 u8 const_amdpci_aspm
;
182 u8 const_hwsw_rfoff_d3
;
183 u8 const_support_pciaspm
;
185 u8 const_hostpci_aspm_setting
;
187 u8 const_devicepci_aspm_setting
;
188 /*If it supports ASPM, Offset[560h] = 0x40,
189 otherwise Offset[560h] = 0x00. */
191 bool support_backdoor
;
194 enum acm_method acm_method
;
196 u16 shortretry_limit
;
209 u8 pcibridge_funcnum
;
212 u16 pcibridge_vendorid
;
213 u16 pcibridge_deviceid
;
218 u8 pcibridge_pciehdr_offset
;
219 u8 pcibridge_linkctrlreg
;
224 struct rtl_pci_priv
{
226 struct mp_adapter ndis_adapter
;
227 struct rtl_led_ctl ledctl
;
228 struct bt_coexist_info bt_coexist
;
231 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
232 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
234 int rtl_pci_reset_trx_ring(struct ieee80211_hw
*hw
);
236 extern struct rtl_intf_ops rtl_pci_ops
;
238 int __devinit
rtl_pci_probe(struct pci_dev
*pdev
,
239 const struct pci_device_id
*id
);
240 void rtl_pci_disconnect(struct pci_dev
*pdev
);
241 int rtl_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
);
242 int rtl_pci_resume(struct pci_dev
*pdev
);
244 static inline u8
pci_read8_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
246 return readb((u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
249 static inline u16
pci_read16_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
251 return readw((u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
254 static inline u32
pci_read32_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
256 return readl((u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
259 static inline void pci_write8_async(struct rtl_priv
*rtlpriv
, u32 addr
, u8 val
)
261 writeb(val
, (u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
264 static inline void pci_write16_async(struct rtl_priv
*rtlpriv
,
267 writew(val
, (u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
270 static inline void pci_write32_async(struct rtl_priv
*rtlpriv
,
273 writel(val
, (u8 __iomem
*) rtlpriv
->io
.pci_mem_start
+ addr
);
276 static inline void rtl_pci_raw_write_port_ulong(u32 port
, u32 val
)
281 static inline void rtl_pci_raw_write_port_uchar(u32 port
, u8 val
)
286 static inline void rtl_pci_raw_read_port_uchar(u32 port
, u8
*pval
)
291 static inline void rtl_pci_raw_read_port_ushort(u32 port
, u16
*pval
)
296 static inline void rtl_pci_raw_read_port_ulong(u32 port
, u32
*pval
)