drivers/net/wireless/rtlwifi/rtl8192de/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL92D_DEF_H__
  31 #define __RTL92D_DEF_H__
  32
  33 /* Min Spacing related settings. */
  34 #define MAX_MSS_DENSITY_2T                              0x13
  35 #define MAX_MSS_DENSITY_1T                              0x0A
  36
  37 #define RF6052_MAX_TX_PWR                               0x3F
  38 #define RF6052_MAX_REG                                  0x3F
  39 #define RF6052_MAX_PATH                                 2
  40
  41 #define HAL_RETRY_LIMIT_INFRA                           48
  42 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
  43
  44 #define PHY_RSSI_SLID_WIN_MAX                           100
  45 #define PHY_LINKQUALITY_SLID_WIN_MAX                    20
  46 #define PHY_BEACON_RSSI_SLID_WIN_MAX                    10
  47
  48 #define RESET_DELAY_8185                                20
  49
  50 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
  51 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
  52
  53 #define NUM_OF_FIRMWARE_QUEUE                           10
  54 #define NUM_OF_PAGES_IN_FW                              0x100
  55 #define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
  56 #define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
  57 #define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
  58 #define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
  59 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                    0x0
  60 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
  61 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                    0x02
  62 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                    0x02
  63 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
  64 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
  65
  66 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                  0x026
  67 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                  0x048
  68 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                  0x048
  69 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                  0x026
  70 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                 0x00
  71
  72 #define MAX_LINES_HWCONFIG_TXT                          1000
  73 #define MAX_BYTES_LINE_HWCONFIG_TXT                     256
  74
  75 #define SW_THREE_WIRE                                   0
  76 #define HW_THREE_WIRE                                   2
  77
  78 #define BT_DEMO_BOARD                                   0
  79 #define BT_QA_BOARD                                     1
  80 #define BT_FPGA                                         2
  81
  82 #define RX_SMOOTH_FACTOR                                20
  83
  84 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
  85 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
  86 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
  87
  88 #define MAX_H2C_QUEUE_NUM                               10
  89
  90 #define RX_MPDU_QUEUE                                   0
  91 #define RX_CMD_QUEUE                                    1
  92 #define RX_MAX_QUEUE                                    2
  93
  94 #define C2H_RX_CMD_HDR_LEN                              8
  95 #define GET_C2H_CMD_CMD_LEN(__prxhdr)                   \
  96         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
  97 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)                \
  98         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
  99 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)                   \
 100         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
 101 #define GET_C2H_CMD_CONTINUE(__prxhdr)                  \
 102         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
 103 #define GET_C2H_CMD_CONTENT(__prxhdr)                   \
 104         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
 105
 106 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 107         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 108 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
 109         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 110 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 111         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 112 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 113         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 114 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
 115         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 116 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 117         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 118 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
 119         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 120 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
 121         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 122 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
 123         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 124
 125 /*
 126  * 92D chip ver:
 127  * BIT8: IS 92D
 128  * BIT9: single phy
 129  * BIT10: C-cut
 130  * BIT11: D-cut
 131  */
 132
 133 /* Chip specific */
 134 #define CHIP_92C                        BIT(0)
 135 #define CHIP_92C_1T2R                   BIT(1)
 136 #define CHIP_8723                       BIT(2) /* RTL8723 With BT feature */
 137 #define CHIP_8723_DRV_REV               BIT(3) /* RTL8723 Driver Revised */
 138 #define NORMAL_CHIP                     BIT(4)
 139 #define CHIP_VENDOR_UMC                 BIT(5)
 140 #define CHIP_VENDOR_UMC_B_CUT           BIT(6) /* Chip version for ECO */
 141
 142 /* for 92D */
 143 #define CHIP_92D                        BIT(8)
 144 #define CHIP_92D_SINGLEPHY              BIT(9)
 145 #define CHIP_92D_C_CUT                  BIT(10)
 146 #define CHIP_92D_D_CUT                  BIT(11)
 147
 148 enum version_8192d {
 149         VERSION_TEST_CHIP_88C = 0x00,
 150         VERSION_TEST_CHIP_92C = 0x01,
 151         VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
 152         VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
 153         VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
 154         VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
 155         VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
 156         VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
 157         VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
 158         VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
 159         VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
 160         VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
 161         VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
 162         VERSION_TEST_CHIP_92D_SINGLEPHY = 0x300,
 163         VERSION_TEST_CHIP_92D_DUALPHY = 0x100,
 164         VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x310,
 165         VERSION_NORMAL_CHIP_92D_DUALPHY = 0x110,
 166         VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x710,
 167         VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x510,
 168         VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0xB10,
 169         VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x910,
 170 };
 171
 172 #define IS_92D_SINGLEPHY(version)               \
 173         ((version & CHIP_92D_SINGLEPHY) ? true : false)
 174 #define IS_92D_C_CUT(version)                   \
 175         ((version & CHIP_92D_C_CUT) ? true : false)
 176 #define IS_92D_D_CUT(version)                   \
 177         ((version & CHIP_92D_D_CUT) ? true : false)
 178
 179 enum rf_optype {
 180         RF_OP_BY_SW_3WIRE = 0,
 181         RF_OP_BY_FW,
 182         RF_OP_MAX
 183 };
 184
 185 enum rtl_desc_qsel {
 186         QSLT_BK = 0x2,
 187         QSLT_BE = 0x0,
 188         QSLT_VI = 0x5,
 189         QSLT_VO = 0x7,
 190         QSLT_BEACON = 0x10,
 191         QSLT_HIGH = 0x11,
 192         QSLT_MGNT = 0x12,
 193         QSLT_CMD = 0x13,
 194 };
 195
 196 enum rtl_desc92d_rate {
 197         DESC92D_RATE1M = 0x00,
 198         DESC92D_RATE2M = 0x01,
 199         DESC92D_RATE5_5M = 0x02,
 200         DESC92D_RATE11M = 0x03,
 201
 202         DESC92D_RATE6M = 0x04,
 203         DESC92D_RATE9M = 0x05,
 204         DESC92D_RATE12M = 0x06,
 205         DESC92D_RATE18M = 0x07,
 206         DESC92D_RATE24M = 0x08,
 207         DESC92D_RATE36M = 0x09,
 208         DESC92D_RATE48M = 0x0a,
 209         DESC92D_RATE54M = 0x0b,
 210
 211         DESC92D_RATEMCS0 = 0x0c,
 212         DESC92D_RATEMCS1 = 0x0d,
 213         DESC92D_RATEMCS2 = 0x0e,
 214         DESC92D_RATEMCS3 = 0x0f,
 215         DESC92D_RATEMCS4 = 0x10,
 216         DESC92D_RATEMCS5 = 0x11,
 217         DESC92D_RATEMCS6 = 0x12,
 218         DESC92D_RATEMCS7 = 0x13,
 219         DESC92D_RATEMCS8 = 0x14,
 220         DESC92D_RATEMCS9 = 0x15,
 221         DESC92D_RATEMCS10 = 0x16,
 222         DESC92D_RATEMCS11 = 0x17,
 223         DESC92D_RATEMCS12 = 0x18,
 224         DESC92D_RATEMCS13 = 0x19,
 225         DESC92D_RATEMCS14 = 0x1a,
 226         DESC92D_RATEMCS15 = 0x1b,
 227         DESC92D_RATEMCS15_SG = 0x1c,
 228         DESC92D_RATEMCS32 = 0x20,
 229 };
 230
 231 enum channel_plan {
 232         CHPL_FCC        = 0,
 233         CHPL_IC         = 1,
 234         CHPL_ETSI       = 2,
 235         CHPL_SPAIN      = 3,
 236         CHPL_FRANCE     = 4,
 237         CHPL_MKK        = 5,
 238         CHPL_MKK1       = 6,
 239         CHPL_ISRAEL     = 7,
 240         CHPL_TELEC      = 8,
 241         CHPL_GLOBAL     = 9,
 242         CHPL_WORLD      = 10,
 243 };
 244
 245 struct phy_sts_cck_8192d {
 246         u8 adc_pwdb_X[4];
 247         u8 sq_rpt;
 248         u8 cck_agc_rpt;
 249 };
 250
 251 struct h2c_cmd_8192c {
 252         u8 element_id;
 253         u32 cmd_len;
 254         u8 *p_cmdbuffer;
 255 };
 256
 257 struct txpower_info {
 258         u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 259         u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 260         u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 261         u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 262         u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 263         u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 264         u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
 265         u8 tssi_a[3];           /* 5GL/5GM/5GH */
 266         u8 tssi_b[3];
 267 };
 268
 269 #endif