2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #define DRM_MODE_ENCODER_MIPI 5
26 /* Medfield DSI controller registers */
28 #define MIPIA_DEVICE_READY_REG 0xb000
29 #define MIPIA_INTR_STAT_REG 0xb004
30 #define MIPIA_INTR_EN_REG 0xb008
31 #define MIPIA_DSI_FUNC_PRG_REG 0xb00c
32 #define MIPIA_HS_TX_TIMEOUT_REG 0xb010
33 #define MIPIA_LP_RX_TIMEOUT_REG 0xb014
34 #define MIPIA_TURN_AROUND_TIMEOUT_REG 0xb018
35 #define MIPIA_DEVICE_RESET_TIMER_REG 0xb01c
36 #define MIPIA_DPI_RESOLUTION_REG 0xb020
37 #define MIPIA_DBI_FIFO_THROTTLE_REG 0xb024
38 #define MIPIA_HSYNC_COUNT_REG 0xb028
39 #define MIPIA_HBP_COUNT_REG 0xb02c
40 #define MIPIA_HFP_COUNT_REG 0xb030
41 #define MIPIA_HACTIVE_COUNT_REG 0xb034
42 #define MIPIA_VSYNC_COUNT_REG 0xb038
43 #define MIPIA_VBP_COUNT_REG 0xb03c
44 #define MIPIA_VFP_COUNT_REG 0xb040
45 #define MIPIA_HIGH_LOW_SWITCH_COUNT_REG 0xb044
46 #define MIPIA_DPI_CONTROL_REG 0xb048
47 #define MIPIA_DPI_DATA_REG 0xb04c
48 #define MIPIA_INIT_COUNT_REG 0xb050
49 #define MIPIA_MAX_RETURN_PACK_SIZE_REG 0xb054
50 #define MIPIA_VIDEO_MODE_FORMAT_REG 0xb058
51 #define MIPIA_EOT_DISABLE_REG 0xb05c
52 #define MIPIA_LP_BYTECLK_REG 0xb060
53 #define MIPIA_LP_GEN_DATA_REG 0xb064
54 #define MIPIA_HS_GEN_DATA_REG 0xb068
55 #define MIPIA_LP_GEN_CTRL_REG 0xb06c
56 #define MIPIA_HS_GEN_CTRL_REG 0xb070
57 #define MIPIA_GEN_FIFO_STAT_REG 0xb074
58 #define MIPIA_HS_LS_DBI_ENABLE_REG 0xb078
59 #define MIPIA_DPHY_PARAM_REG 0xb080
60 #define MIPIA_DBI_BW_CTRL_REG 0xb084
61 #define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG 0xb088
63 #define DSI_DEVICE_READY (0x1)
64 #define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
65 #define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
66 #define DSI_POWER_STATE_ULPS_OFFSET (0x1)
69 #define DSI_ONE_DATA_LANE (0x1)
70 #define DSI_TWO_DATA_LANE (0x2)
71 #define DSI_THREE_DATA_LANE (0X3)
72 #define DSI_FOUR_DATA_LANE (0x4)
73 #define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
74 #define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
75 #define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
76 #define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
77 #define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
78 #define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
79 #define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
81 #define DSI_INTR_STATE_RXSOTERROR 1
83 #define DSI_INTR_STATE_SPL_PKG_SENT (1 << 30)
84 #define DSI_INTR_STATE_TE (1 << 31)
86 #define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
88 #define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
90 #define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
92 #define DSI_RESET_TIMER_MASK (0xffff)
94 #define DSI_DBI_FIFO_WM_HALF (0x0)
95 #define DSI_DBI_FIFO_WM_QUARTER (0x1)
96 #define DSI_DBI_FIFO_WM_LOW (0x2)
98 #define DSI_DPI_TIMING_MASK (0xffff)
100 #define DSI_INIT_TIMER_MASK (0xffff)
102 #define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
104 #define DSI_LP_BYTECLK_MASK (0x0ffff)
106 #define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
107 #define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
108 #define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
109 #define DSI_HS_CTRL_GEN_R0 (0x04)
110 #define DSI_HS_CTRL_GEN_R1 (0x14)
111 #define DSI_HS_CTRL_GEN_R2 (0x24)
112 #define DSI_HS_CTRL_GEN_LONG_W (0x29)
113 #define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
114 #define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
115 #define DSI_HS_CTRL_MCS_R0 (0x06)
116 #define DSI_HS_CTRL_MCS_LONG_W (0x39)
117 #define DSI_HS_CTRL_VC_OFFSET (0x06)
118 #define DSI_HS_CTRL_WC_OFFSET (0x08)
120 #define DSI_FIFO_GEN_HS_DATA_FULL (1 << 0)
121 #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY (1 << 1)
122 #define DSI_FIFO_GEN_HS_DATA_EMPTY (1 << 2)
123 #define DSI_FIFO_GEN_LP_DATA_FULL (1 << 8)
124 #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY (1 << 9)
125 #define DSI_FIFO_GEN_LP_DATA_EMPTY (1 << 10)
126 #define DSI_FIFO_GEN_HS_CTRL_FULL (1 << 16)
127 #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY (1 << 17)
128 #define DSI_FIFO_GEN_HS_CTRL_EMPTY (1 << 18)
129 #define DSI_FIFO_GEN_LP_CTRL_FULL (1 << 24)
130 #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY (1 << 25)
131 #define DSI_FIFO_GEN_LP_CTRL_EMPTY (1 << 26)
132 #define DSI_FIFO_DBI_EMPTY (1 << 27)
133 #define DSI_FIFO_DPI_EMPTY (1 << 28)
135 #define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
137 #define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
138 #define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
140 #define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
141 #define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
143 /* Medfield DSI adapter registers */
144 #define MIPIA_CONTROL_REG 0xb104
145 #define MIPIA_DATA_ADD_REG 0xb108
146 #define MIPIA_DATA_LEN_REG 0xb10c
147 #define MIPIA_CMD_ADD_REG 0xb110
148 #define MIPIA_CMD_LEN_REG 0xb114
151 #define DSI_POWER_MODE_DISPLAY_ON (1 << 2)
152 #define DSI_POWER_MODE_NORMAL_ON (1 << 3)
153 #define DSI_POWER_MODE_SLEEP_OUT (1 << 4)
154 #define DSI_POWER_MODE_PARTIAL_ON (1 << 5)
155 #define DSI_POWER_MODE_IDLE_ON (1 << 6)
158 MDFLD_DSI_ENCODER_DBI
= 0,
159 MDFLD_DSI_ENCODER_DPI
,
163 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE
= 1,
164 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS
= 2,
165 MDFLD_DSI_VIDEO_BURST_MODE
= 3,
168 #define DSI_DPI_COMPLETE_LAST_LINE (1 << 2)
169 #define DSI_DPI_DISABLE_BTA (1 << 3)
185 /* Junk that belongs elsewhere */
186 #define TPO_PANEL_WIDTH 84
187 #define TPO_PANEL_HEIGHT 46
188 #define TMD_PANEL_WIDTH 39
189 #define TMD_PANEL_HEIGHT 71
190 #define PYR_PANEL_WIDTH 53
191 #define PYR_PANEL_HEIGHT 95
193 /* Panel interface */
199 struct mdfld_dsi_dbi_output
;
201 struct mdfld_dsi_connector_state
{
205 struct mdfld_dsi_encoder_state
{
209 struct mdfld_dsi_connector
{
211 * This is ugly, but I have to use connector in it! :-(
212 * FIXME: use drm_connector instead.
214 struct psb_intel_output base
;
220 /* Connection status */
221 enum drm_connector_status status
;
224 struct mdfld_dsi_encoder
{
225 struct drm_encoder base
;
230 * DSI config, consists of one DSI connector, two DSI encoders.
231 * DRM will pick up on DSI encoder basing on differents configs.
233 struct mdfld_dsi_config
{
234 struct drm_device
*dev
;
235 struct drm_display_mode
*fixed_mode
;
236 struct drm_display_mode
*mode
;
238 struct mdfld_dsi_connector
*connector
;
239 struct mdfld_dsi_encoder
*encoders
[DRM_CONNECTOR_MAX_ENCODER
];
240 struct mdfld_dsi_encoder
*encoder
;
247 /*Virtual channel number for this encoder*/
249 /*video mode configure*/
255 #define MDFLD_DSI_CONNECTOR(psb_output) \
256 (container_of(psb_output, struct mdfld_dsi_connector, base))
258 #define MDFLD_DSI_ENCODER(encoder) \
259 (container_of(encoder, struct mdfld_dsi_encoder, base))
262 const struct drm_encoder_funcs
*encoder_funcs
;
263 const struct drm_encoder_helper_funcs
*encoder_helper_funcs
;
264 struct drm_display_mode
*(*get_config_mode
) (struct drm_device
*);
265 void (*update_fb
) (struct mdfld_dsi_dbi_output
*, int);
266 int (*get_panel_info
) (struct drm_device
*, int, struct panel_info
*);
267 int (*reset
)(int pipe
);
268 void (*drv_ic_init
)(struct mdfld_dsi_config
*dsi_config
, int pipe
);