include/linux/mlx4/device.h

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_DEVICE_H
  34 #define MLX4_DEVICE_H
  35
  36 #include <linux/pci.h>
  37 #include <linux/completion.h>
  38 #include <linux/radix-tree.h>
  39
  40 #include <linux/atomic.h>
  41
  42 #define MAX_MSIX_P_PORT         17
  43 #define MAX_MSIX                64
  44 #define MSIX_LEGACY_SZ          4
  45 #define MIN_MSIX_P_PORT         5
  46
  47 enum {
  48         MLX4_FLAG_MSI_X         = 1 << 0,
  49         MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
  50 };
  51
  52 enum {
  53         MLX4_MAX_PORTS          = 2
  54 };
  55
  56 enum {
  57         MLX4_BOARD_ID_LEN = 64
  58 };
  59
  60 enum {
  61         MLX4_DEV_CAP_FLAG_RC            = 1LL <<  0,
  62         MLX4_DEV_CAP_FLAG_UC            = 1LL <<  1,
  63         MLX4_DEV_CAP_FLAG_UD            = 1LL <<  2,
  64         MLX4_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
  65         MLX4_DEV_CAP_FLAG_IPOIB_CSUM    = 1LL <<  7,
  66         MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
  67         MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
  68         MLX4_DEV_CAP_FLAG_DPDP          = 1LL << 12,
  69         MLX4_DEV_CAP_FLAG_BLH           = 1LL << 15,
  70         MLX4_DEV_CAP_FLAG_MEM_WINDOW    = 1LL << 16,
  71         MLX4_DEV_CAP_FLAG_APM           = 1LL << 17,
  72         MLX4_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
  73         MLX4_DEV_CAP_FLAG_RAW_MCAST     = 1LL << 19,
  74         MLX4_DEV_CAP_FLAG_UD_AV_PORT    = 1LL << 20,
  75         MLX4_DEV_CAP_FLAG_UD_MCAST      = 1LL << 21,
  76         MLX4_DEV_CAP_FLAG_IBOE          = 1LL << 30,
  77         MLX4_DEV_CAP_FLAG_UC_LOOPBACK   = 1LL << 32,
  78         MLX4_DEV_CAP_FLAG_WOL           = 1LL << 38,
  79         MLX4_DEV_CAP_FLAG_UDP_RSS       = 1LL << 40,
  80         MLX4_DEV_CAP_FLAG_VEP_UC_STEER  = 1LL << 41,
  81         MLX4_DEV_CAP_FLAG_VEP_MC_STEER  = 1LL << 42,
  82         MLX4_DEV_CAP_FLAG_COUNTERS      = 1LL << 48
  83 };
  84
  85 enum {
  86         MLX4_BMME_FLAG_LOCAL_INV        = 1 <<  6,
  87         MLX4_BMME_FLAG_REMOTE_INV       = 1 <<  7,
  88         MLX4_BMME_FLAG_TYPE_2_WIN       = 1 <<  9,
  89         MLX4_BMME_FLAG_RESERVED_LKEY    = 1 << 10,
  90         MLX4_BMME_FLAG_FAST_REG_WR      = 1 << 11,
  91 };
  92
  93 enum mlx4_event {
  94         MLX4_EVENT_TYPE_COMP               = 0x00,
  95         MLX4_EVENT_TYPE_PATH_MIG           = 0x01,
  96         MLX4_EVENT_TYPE_COMM_EST           = 0x02,
  97         MLX4_EVENT_TYPE_SQ_DRAINED         = 0x03,
  98         MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE    = 0x13,
  99         MLX4_EVENT_TYPE_SRQ_LIMIT          = 0x14,
 100         MLX4_EVENT_TYPE_CQ_ERROR           = 0x04,
 101         MLX4_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 102         MLX4_EVENT_TYPE_EEC_CATAS_ERROR    = 0x06,
 103         MLX4_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 104         MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 105         MLX4_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 106         MLX4_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 107         MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
 108         MLX4_EVENT_TYPE_PORT_CHANGE        = 0x09,
 109         MLX4_EVENT_TYPE_EQ_OVERFLOW        = 0x0f,
 110         MLX4_EVENT_TYPE_ECC_DETECT         = 0x0e,
 111         MLX4_EVENT_TYPE_CMD                = 0x0a
 112 };
 113
 114 enum {
 115         MLX4_PORT_CHANGE_SUBTYPE_DOWN   = 1,
 116         MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
 117 };
 118
 119 enum {
 120         MLX4_PERM_LOCAL_READ    = 1 << 10,
 121         MLX4_PERM_LOCAL_WRITE   = 1 << 11,
 122         MLX4_PERM_REMOTE_READ   = 1 << 12,
 123         MLX4_PERM_REMOTE_WRITE  = 1 << 13,
 124         MLX4_PERM_ATOMIC        = 1 << 14
 125 };
 126
 127 enum {
 128         MLX4_OPCODE_NOP                 = 0x00,
 129         MLX4_OPCODE_SEND_INVAL          = 0x01,
 130         MLX4_OPCODE_RDMA_WRITE          = 0x08,
 131         MLX4_OPCODE_RDMA_WRITE_IMM      = 0x09,
 132         MLX4_OPCODE_SEND                = 0x0a,
 133         MLX4_OPCODE_SEND_IMM            = 0x0b,
 134         MLX4_OPCODE_LSO                 = 0x0e,
 135         MLX4_OPCODE_RDMA_READ           = 0x10,
 136         MLX4_OPCODE_ATOMIC_CS           = 0x11,
 137         MLX4_OPCODE_ATOMIC_FA           = 0x12,
 138         MLX4_OPCODE_MASKED_ATOMIC_CS    = 0x14,
 139         MLX4_OPCODE_MASKED_ATOMIC_FA    = 0x15,
 140         MLX4_OPCODE_BIND_MW             = 0x18,
 141         MLX4_OPCODE_FMR                 = 0x19,
 142         MLX4_OPCODE_LOCAL_INVAL         = 0x1b,
 143         MLX4_OPCODE_CONFIG_CMD          = 0x1f,
 144
 145         MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 146         MLX4_RECV_OPCODE_SEND           = 0x01,
 147         MLX4_RECV_OPCODE_SEND_IMM       = 0x02,
 148         MLX4_RECV_OPCODE_SEND_INVAL     = 0x03,
 149
 150         MLX4_CQE_OPCODE_ERROR           = 0x1e,
 151         MLX4_CQE_OPCODE_RESIZE          = 0x16,
 152 };
 153
 154 enum {
 155         MLX4_STAT_RATE_OFFSET   = 5
 156 };
 157
 158 enum mlx4_protocol {
 159         MLX4_PROT_IB_IPV6 = 0,
 160         MLX4_PROT_ETH,
 161         MLX4_PROT_IB_IPV4,
 162         MLX4_PROT_FCOE
 163 };
 164
 165 enum {
 166         MLX4_MTT_FLAG_PRESENT           = 1
 167 };
 168
 169 enum mlx4_qp_region {
 170         MLX4_QP_REGION_FW = 0,
 171         MLX4_QP_REGION_ETH_ADDR,
 172         MLX4_QP_REGION_FC_ADDR,
 173         MLX4_QP_REGION_FC_EXCH,
 174         MLX4_NUM_QP_REGION
 175 };
 176
 177 enum mlx4_port_type {
 178         MLX4_PORT_TYPE_IB       = 1,
 179         MLX4_PORT_TYPE_ETH      = 2,
 180         MLX4_PORT_TYPE_AUTO     = 3
 181 };
 182
 183 enum mlx4_special_vlan_idx {
 184         MLX4_NO_VLAN_IDX        = 0,
 185         MLX4_VLAN_MISS_IDX,
 186         MLX4_VLAN_REGULAR
 187 };
 188
 189 enum mlx4_steer_type {
 190         MLX4_MC_STEER = 0,
 191         MLX4_UC_STEER,
 192         MLX4_NUM_STEERS
 193 };
 194
 195 enum {
 196         MLX4_NUM_FEXCH          = 64 * 1024,
 197 };
 198
 199 enum {
 200         MLX4_MAX_FAST_REG_PAGES = 511,
 201 };
 202
 203 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 204 {
 205         return (major << 32) | (minor << 16) | subminor;
 206 }
 207
 208 struct mlx4_caps {
 209         u64                     fw_ver;
 210         int                     num_ports;
 211         int                     vl_cap[MLX4_MAX_PORTS + 1];
 212         int                     ib_mtu_cap[MLX4_MAX_PORTS + 1];
 213         __be32                  ib_port_def_cap[MLX4_MAX_PORTS + 1];
 214         u64                     def_mac[MLX4_MAX_PORTS + 1];
 215         int                     eth_mtu_cap[MLX4_MAX_PORTS + 1];
 216         int                     gid_table_len[MLX4_MAX_PORTS + 1];
 217         int                     pkey_table_len[MLX4_MAX_PORTS + 1];
 218         int                     trans_type[MLX4_MAX_PORTS + 1];
 219         int                     vendor_oui[MLX4_MAX_PORTS + 1];
 220         int                     wavelength[MLX4_MAX_PORTS + 1];
 221         u64                     trans_code[MLX4_MAX_PORTS + 1];
 222         int                     local_ca_ack_delay;
 223         int                     num_uars;
 224         int                     bf_reg_size;
 225         int                     bf_regs_per_page;
 226         int                     max_sq_sg;
 227         int                     max_rq_sg;
 228         int                     num_qps;
 229         int                     max_wqes;
 230         int                     max_sq_desc_sz;
 231         int                     max_rq_desc_sz;
 232         int                     max_qp_init_rdma;
 233         int                     max_qp_dest_rdma;
 234         int                     sqp_start;
 235         int                     num_srqs;
 236         int                     max_srq_wqes;
 237         int                     max_srq_sge;
 238         int                     reserved_srqs;
 239         int                     num_cqs;
 240         int                     max_cqes;
 241         int                     reserved_cqs;
 242         int                     num_eqs;
 243         int                     reserved_eqs;
 244         int                     num_comp_vectors;
 245         int                     comp_pool;
 246         int                     num_mpts;
 247         int                     num_mtt_segs;
 248         int                     mtts_per_seg;
 249         int                     fmr_reserved_mtts;
 250         int                     reserved_mtts;
 251         int                     reserved_mrws;
 252         int                     reserved_uars;
 253         int                     num_mgms;
 254         int                     num_amgms;
 255         int                     reserved_mcgs;
 256         int                     num_qp_per_mgm;
 257         int                     num_pds;
 258         int                     reserved_pds;
 259         int                     mtt_entry_sz;
 260         u32                     max_msg_sz;
 261         u32                     page_size_cap;
 262         u64                     flags;
 263         u32                     bmme_flags;
 264         u32                     reserved_lkey;
 265         u16                     stat_rate_support;
 266         u8                      port_width_cap[MLX4_MAX_PORTS + 1];
 267         int                     max_gso_sz;
 268         int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
 269         int                     reserved_qps;
 270         int                     reserved_qps_base[MLX4_NUM_QP_REGION];
 271         int                     log_num_macs;
 272         int                     log_num_vlans;
 273         int                     log_num_prios;
 274         enum mlx4_port_type     port_type[MLX4_MAX_PORTS + 1];
 275         u8                      supported_type[MLX4_MAX_PORTS + 1];
 276         u32                     port_mask;
 277         enum mlx4_port_type     possible_type[MLX4_MAX_PORTS + 1];
 278         u32                     max_counters;
 279 };
 280
 281 struct mlx4_buf_list {
 282         void                   *buf;
 283         dma_addr_t              map;
 284 };
 285
 286 struct mlx4_buf {
 287         struct mlx4_buf_list    direct;
 288         struct mlx4_buf_list   *page_list;
 289         int                     nbufs;
 290         int                     npages;
 291         int                     page_shift;
 292 };
 293
 294 struct mlx4_mtt {
 295         u32                     first_seg;
 296         int                     order;
 297         int                     page_shift;
 298 };
 299
 300 enum {
 301         MLX4_DB_PER_PAGE = PAGE_SIZE / 4
 302 };
 303
 304 struct mlx4_db_pgdir {
 305         struct list_head        list;
 306         DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
 307         DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
 308         unsigned long          *bits[2];
 309         __be32                 *db_page;
 310         dma_addr_t              db_dma;
 311 };
 312
 313 struct mlx4_ib_user_db_page;
 314
 315 struct mlx4_db {
 316         __be32                  *db;
 317         union {
 318                 struct mlx4_db_pgdir            *pgdir;
 319                 struct mlx4_ib_user_db_page     *user_page;
 320         }                       u;
 321         dma_addr_t              dma;
 322         int                     index;
 323         int                     order;
 324 };
 325
 326 struct mlx4_hwq_resources {
 327         struct mlx4_db          db;
 328         struct mlx4_mtt         mtt;
 329         struct mlx4_buf         buf;
 330 };
 331
 332 struct mlx4_mr {
 333         struct mlx4_mtt         mtt;
 334         u64                     iova;
 335         u64                     size;
 336         u32                     key;
 337         u32                     pd;
 338         u32                     access;
 339         int                     enabled;
 340 };
 341
 342 struct mlx4_fmr {
 343         struct mlx4_mr          mr;
 344         struct mlx4_mpt_entry  *mpt;
 345         __be64                 *mtts;
 346         dma_addr_t              dma_handle;
 347         int                     max_pages;
 348         int                     max_maps;
 349         int                     maps;
 350         u8                      page_shift;
 351 };
 352
 353 struct mlx4_uar {
 354         unsigned long           pfn;
 355         int                     index;
 356         struct list_head        bf_list;
 357         unsigned                free_bf_bmap;
 358         void __iomem           *map;
 359         void __iomem           *bf_map;
 360 };
 361
 362 struct mlx4_bf {
 363         unsigned long           offset;
 364         int                     buf_size;
 365         struct mlx4_uar        *uar;
 366         void __iomem           *reg;
 367 };
 368
 369 struct mlx4_cq {
 370         void (*comp)            (struct mlx4_cq *);
 371         void (*event)           (struct mlx4_cq *, enum mlx4_event);
 372
 373         struct mlx4_uar        *uar;
 374
 375         u32                     cons_index;
 376
 377         __be32                 *set_ci_db;
 378         __be32                 *arm_db;
 379         int                     arm_sn;
 380
 381         int                     cqn;
 382         unsigned                vector;
 383
 384         atomic_t                refcount;
 385         struct completion       free;
 386 };
 387
 388 struct mlx4_qp {
 389         void (*event)           (struct mlx4_qp *, enum mlx4_event);
 390
 391         int                     qpn;
 392
 393         atomic_t                refcount;
 394         struct completion       free;
 395 };
 396
 397 struct mlx4_srq {
 398         void (*event)           (struct mlx4_srq *, enum mlx4_event);
 399
 400         int                     srqn;
 401         int                     max;
 402         int                     max_gs;
 403         int                     wqe_shift;
 404
 405         atomic_t                refcount;
 406         struct completion       free;
 407 };
 408
 409 struct mlx4_av {
 410         __be32                  port_pd;
 411         u8                      reserved1;
 412         u8                      g_slid;
 413         __be16                  dlid;
 414         u8                      reserved2;
 415         u8                      gid_index;
 416         u8                      stat_rate;
 417         u8                      hop_limit;
 418         __be32                  sl_tclass_flowlabel;
 419         u8                      dgid[16];
 420 };
 421
 422 struct mlx4_eth_av {
 423         __be32          port_pd;
 424         u8              reserved1;
 425         u8              smac_idx;
 426         u16             reserved2;
 427         u8              reserved3;
 428         u8              gid_index;
 429         u8              stat_rate;
 430         u8              hop_limit;
 431         __be32          sl_tclass_flowlabel;
 432         u8              dgid[16];
 433         u32             reserved4[2];
 434         __be16          vlan;
 435         u8              mac[6];
 436 };
 437
 438 union mlx4_ext_av {
 439         struct mlx4_av          ib;
 440         struct mlx4_eth_av      eth;
 441 };
 442
 443 struct mlx4_counter {
 444         u8      reserved1[3];
 445         u8      counter_mode;
 446         __be32  num_ifc;
 447         u32     reserved2[2];
 448         __be64  rx_frames;
 449         __be64  rx_bytes;
 450         __be64  tx_frames;
 451         __be64  tx_bytes;
 452 };
 453
 454 struct mlx4_dev {
 455         struct pci_dev         *pdev;
 456         unsigned long           flags;
 457         struct mlx4_caps        caps;
 458         struct radix_tree_root  qp_table_tree;
 459         u8                      rev_id;
 460         char                    board_id[MLX4_BOARD_ID_LEN];
 461 };
 462
 463 struct mlx4_init_port_param {
 464         int                     set_guid0;
 465         int                     set_node_guid;
 466         int                     set_si_guid;
 467         u16                     mtu;
 468         int                     port_width_cap;
 469         u16                     vl_cap;
 470         u16                     max_gid;
 471         u16                     max_pkey;
 472         u64                     guid0;
 473         u64                     node_guid;
 474         u64                     si_guid;
 475 };
 476
 477 #define mlx4_foreach_port(port, dev, type)                              \
 478         for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)     \
 479                 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
 480                      ~(dev)->caps.port_mask) & 1 << ((port) - 1))
 481
 482 #define mlx4_foreach_ib_transport_port(port, dev)                       \
 483         for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)     \
 484                 if (((dev)->caps.port_mask & 1 << ((port) - 1)) ||      \
 485                     ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
 486
 487
 488 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
 489                    struct mlx4_buf *buf);
 490 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
 491 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
 492 {
 493         if (BITS_PER_LONG == 64 || buf->nbufs == 1)
 494                 return buf->direct.buf + offset;
 495         else
 496                 return buf->page_list[offset >> PAGE_SHIFT].buf +
 497                         (offset & (PAGE_SIZE - 1));
 498 }
 499
 500 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
 501 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
 502
 503 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
 504 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
 505 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
 506 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
 507
 508 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
 509                   struct mlx4_mtt *mtt);
 510 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
 511 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
 512
 513 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
 514                   int npages, int page_shift, struct mlx4_mr *mr);
 515 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
 516 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
 517 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 518                    int start_index, int npages, u64 *page_list);
 519 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 520                        struct mlx4_buf *buf);
 521
 522 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
 523 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
 524
 525 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
 526                        int size, int max_direct);
 527 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
 528                        int size);
 529
 530 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
 531                   struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
 532                   unsigned vector, int collapsed);
 533 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
 534
 535 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
 536 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 537
 538 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
 539 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
 540
 541 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
 542                    u64 db_rec, struct mlx4_srq *srq);
 543 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
 544 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
 545 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
 546
 547 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
 548 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
 549
 550 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 551                           int block_mcast_loopback, enum mlx4_protocol protocol);
 552 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 553                           enum mlx4_protocol protocol);
 554 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
 555 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
 556 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
 557 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
 558 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 559
 560 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap);
 561 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
 562 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);
 563
 564 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
 565 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
 566 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
 567
 568 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
 569                       int npages, u64 iova, u32 *lkey, u32 *rkey);
 570 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
 571                    int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
 572 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
 573 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
 574                     u32 *lkey, u32 *rkey);
 575 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
 576 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
 577 int mlx4_test_interrupts(struct mlx4_dev *dev);
 578 int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
 579 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
 580
 581 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
 582 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
 583
 584 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 585 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 586
 587 #endif /* MLX4_DEVICE_H */