include/linux/mlx4/qp.h

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_QP_H
  34 #define MLX4_QP_H
  35
  36 #include <linux/types.h>
  37
  38 #include <linux/mlx4/device.h>
  39
  40 #define MLX4_INVALID_LKEY       0x100
  41
  42 enum mlx4_qp_optpar {
  43         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  44         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
  45         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
  46         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
  47         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  48         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
  49         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  50         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  51         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  52         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  53         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
  54         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  55         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  56         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  57         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
  58         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20
  59 };
  60
  61 enum mlx4_qp_state {
  62         MLX4_QP_STATE_RST                       = 0,
  63         MLX4_QP_STATE_INIT                      = 1,
  64         MLX4_QP_STATE_RTR                       = 2,
  65         MLX4_QP_STATE_RTS                       = 3,
  66         MLX4_QP_STATE_SQER                      = 4,
  67         MLX4_QP_STATE_SQD                       = 5,
  68         MLX4_QP_STATE_ERR                       = 6,
  69         MLX4_QP_STATE_SQ_DRAINING               = 7,
  70         MLX4_QP_NUM_STATE
  71 };
  72
  73 enum {
  74         MLX4_QP_ST_RC                           = 0x0,
  75         MLX4_QP_ST_UC                           = 0x1,
  76         MLX4_QP_ST_RD                           = 0x2,
  77         MLX4_QP_ST_UD                           = 0x3,
  78         MLX4_QP_ST_MLX                          = 0x7
  79 };
  80
  81 enum {
  82         MLX4_QP_PM_MIGRATED                     = 0x3,
  83         MLX4_QP_PM_ARMED                        = 0x0,
  84         MLX4_QP_PM_REARM                        = 0x1
  85 };
  86
  87 enum {
  88         /* params1 */
  89         MLX4_QP_BIT_SRE                         = 1 << 15,
  90         MLX4_QP_BIT_SWE                         = 1 << 14,
  91         MLX4_QP_BIT_SAE                         = 1 << 13,
  92         /* params2 */
  93         MLX4_QP_BIT_RRE                         = 1 << 15,
  94         MLX4_QP_BIT_RWE                         = 1 << 14,
  95         MLX4_QP_BIT_RAE                         = 1 << 13,
  96         MLX4_QP_BIT_RIC                         = 1 <<  4,
  97 };
  98
  99 struct mlx4_qp_path {
 100         u8                      fl;
 101         u8                      reserved1[2];
 102         u8                      pkey_index;
 103         u8                      counter_index;
 104         u8                      grh_mylmc;
 105         __be16                  rlid;
 106         u8                      ackto;
 107         u8                      mgid_index;
 108         u8                      static_rate;
 109         u8                      hop_limit;
 110         __be32                  tclass_flowlabel;
 111         u8                      rgid[16];
 112         u8                      sched_queue;
 113         u8                      vlan_index;
 114         u8                      reserved3[2];
 115         u8                      reserved4[2];
 116         u8                      dmac[6];
 117 };
 118
 119 struct mlx4_qp_context {
 120         __be32                  flags;
 121         __be32                  pd;
 122         u8                      mtu_msgmax;
 123         u8                      rq_size_stride;
 124         u8                      sq_size_stride;
 125         u8                      rlkey;
 126         __be32                  usr_page;
 127         __be32                  local_qpn;
 128         __be32                  remote_qpn;
 129         struct                  mlx4_qp_path pri_path;
 130         struct                  mlx4_qp_path alt_path;
 131         __be32                  params1;
 132         u32                     reserved1;
 133         __be32                  next_send_psn;
 134         __be32                  cqn_send;
 135         u32                     reserved2[2];
 136         __be32                  last_acked_psn;
 137         __be32                  ssn;
 138         __be32                  params2;
 139         __be32                  rnr_nextrecvpsn;
 140         __be32                  srcd;
 141         __be32                  cqn_recv;
 142         __be64                  db_rec_addr;
 143         __be32                  qkey;
 144         __be32                  srqn;
 145         __be32                  msn;
 146         __be16                  rq_wqe_counter;
 147         __be16                  sq_wqe_counter;
 148         u32                     reserved3[2];
 149         __be32                  param3;
 150         __be32                  nummmcpeers_basemkey;
 151         u8                      log_page_size;
 152         u8                      reserved4[2];
 153         u8                      mtt_base_addr_h;
 154         __be32                  mtt_base_addr_l;
 155         u32                     reserved5[10];
 156 };
 157
 158 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
 159 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
 160
 161 enum {
 162         MLX4_WQE_CTRL_NEC               = 1 << 29,
 163         MLX4_WQE_CTRL_FENCE             = 1 << 6,
 164         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
 165         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
 166         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
 167         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
 168         MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
 169         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
 170         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 171 };
 172
 173 struct mlx4_wqe_ctrl_seg {
 174         __be32                  owner_opcode;
 175         __be16                  vlan_tag;
 176         u8                      ins_vlan;
 177         u8                      fence_size;
 178         /*
 179          * High 24 bits are SRC remote buffer; low 8 bits are flags:
 180          * [7]   SO (strong ordering)
 181          * [5]   TCP/UDP checksum
 182          * [4]   IP checksum
 183          * [3:2] C (generate completion queue entry)
 184          * [1]   SE (solicited event)
 185          */
 186         __be32                  srcrb_flags;
 187         /*
 188          * imm is immediate data for send/RDMA write w/ immediate;
 189          * also invalidation key for send with invalidate; input
 190          * modifier for WQEs on CCQs.
 191          */
 192         __be32                  imm;
 193 };
 194
 195 enum {
 196         MLX4_WQE_MLX_VL15       = 1 << 17,
 197         MLX4_WQE_MLX_SLR        = 1 << 16
 198 };
 199
 200 struct mlx4_wqe_mlx_seg {
 201         u8                      owner;
 202         u8                      reserved1[2];
 203         u8                      opcode;
 204         u8                      reserved2[3];
 205         u8                      size;
 206         /*
 207          * [17]    VL15
 208          * [16]    SLR
 209          * [15:12] static rate
 210          * [11:8]  SL
 211          * [4]     ICRC
 212          * [3:2]   C
 213          * [0]     FL (force loopback)
 214          */
 215         __be32                  flags;
 216         __be16                  rlid;
 217         u16                     reserved3;
 218 };
 219
 220 struct mlx4_wqe_datagram_seg {
 221         __be32                  av[8];
 222         __be32                  dqpn;
 223         __be32                  qkey;
 224         __be16                  vlan;
 225         u8                      mac[6];
 226 };
 227
 228 struct mlx4_wqe_lso_seg {
 229         __be32                  mss_hdr_size;
 230         __be32                  header[0];
 231 };
 232
 233 struct mlx4_wqe_bind_seg {
 234         __be32                  flags1;
 235         __be32                  flags2;
 236         __be32                  new_rkey;
 237         __be32                  lkey;
 238         __be64                  addr;
 239         __be64                  length;
 240 };
 241
 242 enum {
 243         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 244         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 245         MLX4_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 246         MLX4_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 247         MLX4_WQE_FMR_PERM_ATOMIC        = 1 << 31
 248 };
 249
 250 struct mlx4_wqe_fmr_seg {
 251         __be32                  flags;
 252         __be32                  mem_key;
 253         __be64                  buf_list;
 254         __be64                  start_addr;
 255         __be64                  reg_len;
 256         __be32                  offset;
 257         __be32                  page_size;
 258         u32                     reserved[2];
 259 };
 260
 261 struct mlx4_wqe_fmr_ext_seg {
 262         u8                      flags;
 263         u8                      reserved;
 264         __be16                  app_mask;
 265         __be16                  wire_app_tag;
 266         __be16                  mem_app_tag;
 267         __be32                  wire_ref_tag_base;
 268         __be32                  mem_ref_tag_base;
 269 };
 270
 271 struct mlx4_wqe_local_inval_seg {
 272         __be32                  flags;
 273         u32                     reserved1;
 274         __be32                  mem_key;
 275         u32                     reserved2[2];
 276         __be32                  guest_id;
 277         __be64                  pa;
 278 };
 279
 280 struct mlx4_wqe_raddr_seg {
 281         __be64                  raddr;
 282         __be32                  rkey;
 283         u32                     reserved;
 284 };
 285
 286 struct mlx4_wqe_atomic_seg {
 287         __be64                  swap_add;
 288         __be64                  compare;
 289 };
 290
 291 struct mlx4_wqe_masked_atomic_seg {
 292         __be64                  swap_add;
 293         __be64                  compare;
 294         __be64                  swap_add_mask;
 295         __be64                  compare_mask;
 296 };
 297
 298 struct mlx4_wqe_data_seg {
 299         __be32                  byte_count;
 300         __be32                  lkey;
 301         __be64                  addr;
 302 };
 303
 304 enum {
 305         MLX4_INLINE_ALIGN       = 64,
 306         MLX4_INLINE_SEG         = 1 << 31,
 307 };
 308
 309 struct mlx4_wqe_inline_seg {
 310         __be32                  byte_count;
 311 };
 312
 313 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 314                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 315                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
 316                    int sqd_event, struct mlx4_qp *qp);
 317
 318 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 319                   struct mlx4_qp_context *context);
 320
 321 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 322                      struct mlx4_qp_context *context,
 323                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
 324
 325 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 326 {
 327         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
 328 }
 329
 330 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 331
 332 #endif /* MLX4_QP_H */