?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
include: replace linux/module.h with "struct module" wherever possible
[linux-2.6/next.git] / include / linux / mmc / mmc.h
blob5a794cb503ea77eadf3ed7dc3330872fd5fe9973
1 /*
2 * Header for MultiMediaCard (MMC)
3 *
4 * Copyright 2002 Hewlett-Packard Company
5 *
6 * Use consistent with the GNU GPL is permitted,
7 * provided that this copyright notice is
8 * preserved in its entirety in all copies and derived works.
9 *
10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12 * FITNESS FOR ANY PARTICULAR PURPOSE.
13 *
14 * Many thanks to Alessandro Rubini and Jonathan Corbet!
15 *
16 * Based strongly on code by:
17 *
18 * Author: Yong-iL Joh <tolkien@mizi.com>
19 *
20 * Author: Andrew Christian
21 * 15 May 2002
22 */
23
24 #ifndef LINUX_MMC_MMC_H
25 #define LINUX_MMC_MMC_H
26
27 /* Standard MMC commands (4.1) type argument response */
28 /* class 1 */
29 #define MMC_GO_IDLE_STATE 0 /* bc */
30 #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
31 #define MMC_ALL_SEND_CID 2 /* bcr R2 */
32 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
33 #define MMC_SET_DSR 4 /* bc [31:16] RCA */
34 #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
35 #define MMC_SWITCH 6 /* ac [31:0] See below R1b */
36 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
37 #define MMC_SEND_EXT_CSD 8 /* adtc R1 */
38 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
40 #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41 #define MMC_STOP_TRANSMISSION 12 /* ac R1b */
42 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
43 #define MMC_BUS_TEST_R 14 /* adtc R1 */
44 #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
45 #define MMC_BUS_TEST_W 19 /* adtc R1 */
46 #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
47 #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
48
49 /* class 2 */
50 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
51 #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
52 #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
53 #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
54
55 /* class 3 */
56 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
57
58 /* class 4 */
59 #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
60 #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
61 #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
62 #define MMC_PROGRAM_CID 26 /* adtc R1 */
63 #define MMC_PROGRAM_CSD 27 /* adtc R1 */
64
65 /* class 6 */
66 #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
67 #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
68 #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
69
70 /* class 5 */
71 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
72 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
73 #define MMC_ERASE 38 /* ac R1b */
74
75 /* class 9 */
76 #define MMC_FAST_IO 39 /* ac <Complex> R4 */
77 #define MMC_GO_IRQ_STATE 40 /* bcr R5 */
78
79 /* class 7 */
80 #define MMC_LOCK_UNLOCK 42 /* adtc R1b */
81
82 /* class 8 */
83 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
84 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
85
86 static inline bool mmc_op_multi(u32 opcode)
87 {
88 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
89 opcode == MMC_READ_MULTIPLE_BLOCK;
90 }
91
92 /*
93 * MMC_SWITCH argument format:
94 *
95 * [31:26] Always 0
96 * [25:24] Access Mode
97 * [23:16] Location of target Byte in EXT_CSD
98 * [15:08] Value Byte
99 * [07:03] Always 0
100 * [02:00] Command Set
101 */
102
103 /*
104 MMC status in R1, for native mode (SPI bits are different)
105 Type
106 e : error bit
107 s : status bit
108 r : detected and set for the actual command response
109 x : detected and set during command execution. the host must poll
110 the card by sending status command in order to read these bits.
111 Clear condition
112 a : according to the card state
113 b : always related to the previous command. Reception of
114 a valid command will clear it (with a delay of one command)
115 c : clear by read
116 */
117
118 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
119 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
120 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
121 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
122 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
123 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
124 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
125 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
126 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
127 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
128 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
129 #define R1_CC_ERROR (1 << 20) /* erx, c */
130 #define R1_ERROR (1 << 19) /* erx, c */
131 #define R1_UNDERRUN (1 << 18) /* ex, c */
132 #define R1_OVERRUN (1 << 17) /* ex, c */
133 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
134 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
135 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
136 #define R1_ERASE_RESET (1 << 13) /* sr, c */
137 #define R1_STATUS(x) (x & 0xFFFFE000)
138 #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
139 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
140 #define R1_SWITCH_ERROR (1 << 7) /* sx, c */
141 #define R1_APP_CMD (1 << 5) /* sr, c */
142
143 #define R1_STATE_IDLE 0
144 #define R1_STATE_READY 1
145 #define R1_STATE_IDENT 2
146 #define R1_STATE_STBY 3
147 #define R1_STATE_TRAN 4
148 #define R1_STATE_DATA 5
149 #define R1_STATE_RCV 6
150 #define R1_STATE_PRG 7
151 #define R1_STATE_DIS 8
152
153 /*
154 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
155 * R1 is the low order byte; R2 is the next highest byte, when present.
156 */
157 #define R1_SPI_IDLE (1 << 0)
158 #define R1_SPI_ERASE_RESET (1 << 1)
159 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
160 #define R1_SPI_COM_CRC (1 << 3)
161 #define R1_SPI_ERASE_SEQ (1 << 4)
162 #define R1_SPI_ADDRESS (1 << 5)
163 #define R1_SPI_PARAMETER (1 << 6)
164 /* R1 bit 7 is always zero */
165 #define R2_SPI_CARD_LOCKED (1 << 8)
166 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
167 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
168 #define R2_SPI_ERROR (1 << 10)
169 #define R2_SPI_CC_ERROR (1 << 11)
170 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
171 #define R2_SPI_WP_VIOLATION (1 << 13)
172 #define R2_SPI_ERASE_PARAM (1 << 14)
173 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
174 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
175
176 /* These are unpacked versions of the actual responses */
177
178 struct _mmc_csd {
179 u8 csd_structure;
180 u8 spec_vers;
181 u8 taac;
182 u8 nsac;
183 u8 tran_speed;
184 u16 ccc;
185 u8 read_bl_len;
186 u8 read_bl_partial;
187 u8 write_blk_misalign;
188 u8 read_blk_misalign;
189 u8 dsr_imp;
190 u16 c_size;
191 u8 vdd_r_curr_min;
192 u8 vdd_r_curr_max;
193 u8 vdd_w_curr_min;
194 u8 vdd_w_curr_max;
195 u8 c_size_mult;
196 union {
197 struct { /* MMC system specification version 3.1 */
198 u8 erase_grp_size;
199 u8 erase_grp_mult;
200 } v31;
201 struct { /* MMC system specification version 2.2 */
202 u8 sector_size;
203 u8 erase_grp_size;
204 } v22;
205 } erase;
206 u8 wp_grp_size;
207 u8 wp_grp_enable;
208 u8 default_ecc;
209 u8 r2w_factor;
210 u8 write_bl_len;
211 u8 write_bl_partial;
212 u8 file_format_grp;
213 u8 copy;
214 u8 perm_write_protect;
215 u8 tmp_write_protect;
216 u8 file_format;
217 u8 ecc;
218 };
219
220 /*
221 * OCR bits are mostly in host.h
222 */
223 #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
224
225 /*
226 * Card Command Classes (CCC)
227 */
228 #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
229 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
230 /* (and for SPI, CMD58,59) */
231 #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
232 /* (CMD11) */
233 #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
234 /* (CMD16,17,18) */
235 #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
236 /* (CMD20) */
237 #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
238 /* (CMD16,24,25,26,27) */
239 #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
240 /* (CMD32,33,34,35,36,37,38,39) */
241 #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
242 /* (CMD28,29,30) */
243 #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
244 /* (CMD16,CMD42) */
245 #define CCC_APP_SPEC (1<<8) /* (8) Application specific */
246 /* (CMD55,56,57,ACMD*) */
247 #define CCC_IO_MODE (1<<9) /* (9) I/O mode */
248 /* (CMD5,39,40,52,53) */
249 #define CCC_SWITCH (1<<10) /* (10) High speed switch */
250 /* (CMD6,34,35,36,37,50) */
251 /* (11) Reserved */
252 /* (CMD?) */
253
254 /*
255 * CSD field definitions
256 */
257
258 #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
259 #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
260 #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
261 #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
262
263 #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
264 #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
265 #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
266 #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
267 #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
268
269 /*
270 * EXT_CSD fields
271 */
272
273 #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
274 #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
275 #define EXT_CSD_WR_REL_PARAM 166 /* RO */
276 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
277 #define EXT_CSD_PART_CONFIG 179 /* R/W */
278 #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
279 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
280 #define EXT_CSD_HS_TIMING 185 /* R/W */
281 #define EXT_CSD_REV 192 /* RO */
282 #define EXT_CSD_STRUCTURE 194 /* RO */
283 #define EXT_CSD_CARD_TYPE 196 /* RO */
284 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
285 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
286 #define EXT_CSD_S_A_TIMEOUT 217 /* RO */
287 #define EXT_CSD_REL_WR_SEC_C 222 /* RO */
288 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
289 #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
290 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
291 #define EXT_CSD_BOOT_MULT 226 /* RO */
292 #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
293 #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
294 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
295 #define EXT_CSD_TRIM_MULT 232 /* RO */
296
297 /*
298 * EXT_CSD field definitions
299 */
300
301 #define EXT_CSD_WR_REL_PARAM_EN (1<<2)
302
303 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
304 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
305 #define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2)
306
307 #define EXT_CSD_CMD_SET_NORMAL (1<<0)
308 #define EXT_CSD_CMD_SET_SECURE (1<<1)
309 #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
310
311 #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
312 #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
313 #define EXT_CSD_CARD_TYPE_MASK 0xF /* Mask out reserved bits */
314 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
315 /* DDR mode @1.8V or 3V I/O */
316 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
317 /* DDR mode @1.2V I/O */
318 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
319 | EXT_CSD_CARD_TYPE_DDR_1_2V)
320
321 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
322 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
323 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
324 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
325 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
326
327 #define EXT_CSD_SEC_ER_EN BIT(0)
328 #define EXT_CSD_SEC_BD_BLK_EN BIT(2)
329 #define EXT_CSD_SEC_GB_CL_EN BIT(4)
330
331 /*
332 * MMC_SWITCH access modes
333 */
334
335 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
336 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
337 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
338 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
339
340 #endif /* LINUX_MMC_MMC_H */
linux-next