arch/alpha/kernel/sys_noritake.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_noritake.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the NORITAKE (AlphaServer 1000A),
   9  * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/io.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/core_apecs.h>
  28 #include <asm/core_cia.h>
  29 #include <asm/tlbflush.h>
  30
  31 #include "proto.h"
  32 #include "irq_impl.h"
  33 #include "pci_impl.h"
  34 #include "machvec_impl.h"
  35
  36 /* Note mask bit is true for ENABLED irqs.  */
  37 static int cached_irq_mask;
  38
  39 static inline void
  40 noritake_update_irq_hw(int irq, int mask)
  41 {
  42         int port = 0x54a;
  43         if (irq >= 32) {
  44             mask >>= 16;
  45             port = 0x54c;
  46         }
  47         outw(mask, port);
  48 }
  49
  50 static void
  51 noritake_enable_irq(unsigned int irq)
  52 {
  53         noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
  54 }
  55
  56 static void
  57 noritake_disable_irq(unsigned int irq)
  58 {
  59         noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
  60 }
  61
  62 static unsigned int
  63 noritake_startup_irq(unsigned int irq)
  64 {
  65         noritake_enable_irq(irq);
  66         return 0;
  67 }
  68
  69 static void
  70 noritake_end_irq(unsigned int irq)
  71 {
  72         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  73                 noritake_enable_irq(irq);
  74 }
  75
  76 static struct hw_interrupt_type noritake_irq_type = {
  77         .typename       = "NORITAKE",
  78         .startup        = noritake_startup_irq,
  79         .shutdown       = noritake_disable_irq,
  80         .enable         = noritake_enable_irq,
  81         .disable        = noritake_disable_irq,
  82         .ack            = noritake_disable_irq,
  83         .end            = noritake_end_irq,
  84 };
  85
  86 static void
  87 noritake_device_interrupt(unsigned long vector)
  88 {
  89         unsigned long pld;
  90         unsigned int i;
  91
  92         /* Read the interrupt summary registers of NORITAKE */
  93         pld = (((unsigned long) inw(0x54c) << 32)
  94                | ((unsigned long) inw(0x54a) << 16)
  95                | ((unsigned long) inb(0xa0) << 8)
  96                | inb(0x20));
  97
  98         /*
  99          * Now for every possible bit set, work through them and call
 100          * the appropriate interrupt handler.
 101          */
 102         while (pld) {
 103                 i = ffz(~pld);
 104                 pld &= pld - 1; /* clear least bit set */
 105                 if (i < 16) {
 106                         isa_device_interrupt(vector);
 107                 } else {
 108                         handle_irq(i);
 109                 }
 110         }
 111 }
 112
 113 static void
 114 noritake_srm_device_interrupt(unsigned long vector)
 115 {
 116         int irq;
 117
 118         irq = (vector - 0x800) >> 4;
 119
 120         /*
 121          * I really hate to do this, too, but the NORITAKE SRM console also
 122          * reports PCI vectors *lower* than I expected from the bit numbers
 123          * in the documentation.
 124          * But I really don't want to change the fixup code for allocation
 125          * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
 126          * look nice and clean now.
 127          * So, here's this additional grotty hack... :-(
 128          */
 129         if (irq >= 16)
 130                 irq = irq + 1;
 131
 132         handle_irq(irq);
 133 }
 134
 135 static void __init
 136 noritake_init_irq(void)
 137 {
 138         long i;
 139
 140         if (alpha_using_srm)
 141                 alpha_mv.device_interrupt = noritake_srm_device_interrupt;
 142
 143         outw(0, 0x54a);
 144         outw(0, 0x54c);
 145
 146         for (i = 16; i < 48; ++i) {
 147                 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 148                 irq_desc[i].chip = &noritake_irq_type;
 149         }
 150
 151         init_i8259a_irqs();
 152         common_init_isa_dma();
 153 }
 154
 155
 156 /*
 157  * PCI Fixup configuration.
 158  *
 159  * Summary @ 0x542, summary register #1:
 160  * Bit      Meaning
 161  * 0        All valid ints from summary regs 2 & 3
 162  * 1        QLOGIC ISP1020A SCSI
 163  * 2        Interrupt Line A from slot 0
 164  * 3        Interrupt Line B from slot 0
 165  * 4        Interrupt Line A from slot 1
 166  * 5        Interrupt line B from slot 1
 167  * 6        Interrupt Line A from slot 2
 168  * 7        Interrupt Line B from slot 2
 169  * 8        Interrupt Line A from slot 3
 170  * 9        Interrupt Line B from slot 3
 171  *10        Interrupt Line A from slot 4
 172  *11        Interrupt Line B from slot 4
 173  *12        Interrupt Line A from slot 5
 174  *13        Interrupt Line B from slot 5
 175  *14        Interrupt Line A from slot 6
 176  *15        Interrupt Line B from slot 6
 177  *
 178  * Summary @ 0x544, summary register #2:
 179  * Bit      Meaning
 180  * 0        OR of all unmasked ints in SR #2
 181  * 1        OR of secondary bus ints
 182  * 2        Interrupt Line C from slot 0
 183  * 3        Interrupt Line D from slot 0
 184  * 4        Interrupt Line C from slot 1
 185  * 5        Interrupt line D from slot 1
 186  * 6        Interrupt Line C from slot 2
 187  * 7        Interrupt Line D from slot 2
 188  * 8        Interrupt Line C from slot 3
 189  * 9        Interrupt Line D from slot 3
 190  *10        Interrupt Line C from slot 4
 191  *11        Interrupt Line D from slot 4
 192  *12        Interrupt Line C from slot 5
 193  *13        Interrupt Line D from slot 5
 194  *14        Interrupt Line C from slot 6
 195  *15        Interrupt Line D from slot 6
 196  *
 197  * The device to slot mapping looks like:
 198  *
 199  * Slot     Device
 200  *  7       Intel PCI-EISA bridge chip
 201  *  8       DEC PCI-PCI bridge chip
 202  * 11       PCI on board slot 0
 203  * 12       PCI on board slot 1
 204  * 13       PCI on board slot 2
 205  *
 206  *
 207  * This two layered interrupt approach means that we allocate IRQ 16 and
 208  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 209  * comes in on.  This makes interrupt processing much easier.
 210  */
 211
 212 static int __init
 213 noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 214 {
 215         static char irq_tab[15][5] __initdata = {
 216                 /*INT    INTA   INTB   INTC   INTD */
 217                 /* note: IDSELs 16, 17, and 25 are CORELLE only */
 218                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 219                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17, S3 Trio64 */
 220                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCEB */
 221                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PPB  */
 222                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  ???? */
 223                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  ???? */
 224                 { 16+2,  16+2,  16+3,  32+2,  32+3},  /* IdSel 22,  slot 0 */
 225                 { 16+4,  16+4,  16+5,  32+4,  32+5},  /* IdSel 23,  slot 1 */
 226                 { 16+6,  16+6,  16+7,  32+6,  32+7},  /* IdSel 24,  slot 2 */
 227                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 25,  slot 3 */
 228                 /* The following 5 are actually on PCI bus 1, which is
 229                    across the built-in bridge of the NORITAKE only.  */
 230                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 231                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 17,  slot 3 */
 232                 {16+10, 16+10, 16+11, 32+10, 32+11},  /* IdSel 18,  slot 4 */
 233                 {16+12, 16+12, 16+13, 32+12, 32+13},  /* IdSel 19,  slot 5 */
 234                 {16+14, 16+14, 16+15, 32+14, 32+15},  /* IdSel 20,  slot 6 */
 235         };
 236         const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
 237         return COMMON_TABLE_LOOKUP;
 238 }
 239
 240 static u8 __init
 241 noritake_swizzle(struct pci_dev *dev, u8 *pinp)
 242 {
 243         int slot, pin = *pinp;
 244
 245         if (dev->bus->number == 0) {
 246                 slot = PCI_SLOT(dev->devfn);
 247         }
 248         /* Check for the built-in bridge */
 249         else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 250                 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
 251         }
 252         else
 253         {
 254                 /* Must be a card-based bridge.  */
 255                 do {
 256                         if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 257                                 slot = PCI_SLOT(dev->devfn) + 15;
 258                                 break;
 259                         }
 260                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
 261
 262                         /* Move up the chain of bridges.  */
 263                         dev = dev->bus->self;
 264                         /* Slot of the next bridge.  */
 265                         slot = PCI_SLOT(dev->devfn);
 266                 } while (dev->bus->self);
 267         }
 268         *pinp = pin;
 269         return slot;
 270 }
 271
 272 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 273 static void
 274 noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
 275 {
 276 #define MCHK_NO_DEVSEL 0x205U
 277 #define MCHK_NO_TABT 0x204U
 278
 279         struct el_common *mchk_header;
 280         unsigned int code;
 281
 282         mchk_header = (struct el_common *)la_ptr;
 283
 284         /* Clear the error before any reporting.  */
 285         mb();
 286         mb(); /* magic */
 287         draina();
 288         apecs_pci_clr_err();
 289         wrmces(0x7);
 290         mb();
 291
 292         code = mchk_header->code;
 293         process_mcheck_info(vector, la_ptr, "NORITAKE APECS",
 294                             (mcheck_expected(0)
 295                              && (code == MCHK_NO_DEVSEL
 296                                  || code == MCHK_NO_TABT)));
 297 }
 298 #endif
 299
 300
 301 /*
 302  * The System Vectors
 303  */
 304
 305 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 306 struct alpha_machine_vector noritake_mv __initmv = {
 307         .vector_name            = "Noritake",
 308         DO_EV4_MMU,
 309         DO_DEFAULT_RTC,
 310         DO_APECS_IO,
 311         .machine_check          = noritake_apecs_machine_check,
 312         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 313         .min_io_address         = EISA_DEFAULT_IO_BASE,
 314         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 315
 316         .nr_irqs                = 48,
 317         .device_interrupt       = noritake_device_interrupt,
 318
 319         .init_arch              = apecs_init_arch,
 320         .init_irq               = noritake_init_irq,
 321         .init_rtc               = common_init_rtc,
 322         .init_pci               = common_init_pci,
 323         .pci_map_irq            = noritake_map_irq,
 324         .pci_swizzle            = noritake_swizzle,
 325 };
 326 ALIAS_MV(noritake)
 327 #endif
 328
 329 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
 330 struct alpha_machine_vector noritake_primo_mv __initmv = {
 331         .vector_name            = "Noritake-Primo",
 332         DO_EV5_MMU,
 333         DO_DEFAULT_RTC,
 334         DO_CIA_IO,
 335         .machine_check          = cia_machine_check,
 336         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 337         .min_io_address         = EISA_DEFAULT_IO_BASE,
 338         .min_mem_address        = CIA_DEFAULT_MEM_BASE,
 339
 340         .nr_irqs                = 48,
 341         .device_interrupt       = noritake_device_interrupt,
 342
 343         .init_arch              = cia_init_arch,
 344         .init_irq               = noritake_init_irq,
 345         .init_rtc               = common_init_rtc,
 346         .init_pci               = cia_init_pci,
 347         .kill_arch              = cia_kill_arch,
 348         .pci_map_irq            = noritake_map_irq,
 349         .pci_swizzle            = noritake_swizzle,
 350 };
 351 ALIAS_MV(noritake_primo)
 352 #endif