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Linux 2.6.25-rc4
[linux-2.6/next.git] / arch / arm / mach-omap2 / clock.h
blob4f791866b910900bdd1b40058929e6acd408976f
1 /*
2 * linux/arch/arm/mach-omap24xx/clock.h
3 *
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Created for OMAP2.
7 *
8 * Copyright (C) 2004 Nokia corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19
20 static void omap2_sys_clk_recalc(struct clk * clk);
21 static void omap2_clksel_recalc(struct clk * clk);
22 static void omap2_followparent_recalc(struct clk * clk);
23 static void omap2_propagate_rate(struct clk * clk);
24 static void omap2_mpu_recalc(struct clk * clk);
25 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
26 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
27 static void omap2_clk_disable(struct clk *clk);
28 static void omap2_sys_clk_recalc(struct clk * clk);
29 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
30 static u32 omap2_clksel_get_divisor(struct clk *clk);
31
32
33 #define RATE_IN_242X (1 << 0)
34 #define RATE_IN_243X (1 << 1)
35
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
39 */
40 struct prcm_config {
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
52 unsigned char flags;
53 };
54
55 /* Mask for clksel which support parent settign in set_rate */
56 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
57 CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
58
59 /* Mask for clksel regs which support rate operations */
60 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
61 CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
62 CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
63 CM_SYSCLKOUT_SEL1)
64
65 /*
66 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
67 * These configurations are characterized by voltage and speed for clocks.
68 * The device is only validated for certain combinations. One way to express
69 * these combinations is via the 'ratio's' which the clocks operate with
70 * respect to each other. These ratio sets are for a given voltage/DPLL
71 * setting. All configurations can be described by a DPLL setting and a ratio
72 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
73 *
74 * 2430 differs from 2420 in that there are no more phase synchronizers used.
75 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
76 * 2430 (iva2.1, NOdsp, mdm)
77 */
78
79 /* Core fields for cm_clksel, not ratio governed */
80 #define RX_CLKSEL_DSS1 (0x10 << 8)
81 #define RX_CLKSEL_DSS2 (0x0 << 13)
82 #define RX_CLKSEL_SSI (0x5 << 20)
83
84 /*-------------------------------------------------------------------------
85 * Voltage/DPLL ratios
86 *-------------------------------------------------------------------------*/
87
88 /* 2430 Ratio's, 2430-Ratio Config 1 */
89 #define R1_CLKSEL_L3 (4 << 0)
90 #define R1_CLKSEL_L4 (2 << 5)
91 #define R1_CLKSEL_USB (4 << 25)
92 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
93 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
94 R1_CLKSEL_L4 | R1_CLKSEL_L3
95 #define R1_CLKSEL_MPU (2 << 0)
96 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
97 #define R1_CLKSEL_DSP (2 << 0)
98 #define R1_CLKSEL_DSP_IF (2 << 5)
99 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
100 #define R1_CLKSEL_GFX (2 << 0)
101 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
102 #define R1_CLKSEL_MDM (4 << 0)
103 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
104
105 /* 2430-Ratio Config 2 */
106 #define R2_CLKSEL_L3 (6 << 0)
107 #define R2_CLKSEL_L4 (2 << 5)
108 #define R2_CLKSEL_USB (2 << 25)
109 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
110 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
111 R2_CLKSEL_L4 | R2_CLKSEL_L3
112 #define R2_CLKSEL_MPU (2 << 0)
113 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
114 #define R2_CLKSEL_DSP (2 << 0)
115 #define R2_CLKSEL_DSP_IF (3 << 5)
116 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
117 #define R2_CLKSEL_GFX (2 << 0)
118 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
119 #define R2_CLKSEL_MDM (6 << 0)
120 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
121
122 /* 2430-Ratio Bootm (BYPASS) */
123 #define RB_CLKSEL_L3 (1 << 0)
124 #define RB_CLKSEL_L4 (1 << 5)
125 #define RB_CLKSEL_USB (1 << 25)
126 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
127 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
128 RB_CLKSEL_L4 | RB_CLKSEL_L3
129 #define RB_CLKSEL_MPU (1 << 0)
130 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
131 #define RB_CLKSEL_DSP (1 << 0)
132 #define RB_CLKSEL_DSP_IF (1 << 5)
133 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
134 #define RB_CLKSEL_GFX (1 << 0)
135 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
136 #define RB_CLKSEL_MDM (1 << 0)
137 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
138
139 /* 2420 Ratio Equivalents */
140 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
141 #define RXX_CLKSEL_SSI (0x8 << 20)
142
143 /* 2420-PRCM III 532MHz core */
144 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
145 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
146 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
147 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
148 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
149 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
150 RIII_CLKSEL_L3
151 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
152 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
153 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
154 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
155 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
156 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
157 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
158 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
159 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
160 RIII_CLKSEL_DSP
161 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
162 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
163
164 /* 2420-PRCM II 600MHz core */
165 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
166 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
167 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
168 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
169 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
170 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
171 RII_CLKSEL_L4 | RII_CLKSEL_L3
172 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
173 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
174 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
175 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
176 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
177 #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
178 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
179 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
180 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
181 RII_CLKSEL_DSP
182 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
183 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
184
185 /* 2420-PRCM VII (boot) */
186 #define RVII_CLKSEL_L3 (1 << 0)
187 #define RVII_CLKSEL_L4 (1 << 5)
188 #define RVII_CLKSEL_DSS1 (1 << 8)
189 #define RVII_CLKSEL_DSS2 (0 << 13)
190 #define RVII_CLKSEL_VLYNQ (1 << 15)
191 #define RVII_CLKSEL_SSI (1 << 20)
192 #define RVII_CLKSEL_USB (1 << 25)
193
194 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
195 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
196 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
197
198 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
199 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
200
201 #define RVII_CLKSEL_DSP (1 << 0)
202 #define RVII_CLKSEL_DSP_IF (1 << 5)
203 #define RVII_SYNC_DSP (0 << 7)
204 #define RVII_CLKSEL_IVA (1 << 8)
205 #define RVII_SYNC_IVA (0 << 13)
206 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
207 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
208
209 #define RVII_CLKSEL_GFX (1 << 0)
210 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
211
212 /*-------------------------------------------------------------------------
213 * 2430 Target modes: Along with each configuration the CPU has several
214 * modes which goes along with them. Modes mainly are the addition of
215 * describe DPLL combinations to go along with a ratio.
216 *-------------------------------------------------------------------------*/
217
218 /* Hardware governed */
219 #define MX_48M_SRC (0 << 3)
220 #define MX_54M_SRC (0 << 5)
221 #define MX_APLLS_CLIKIN_12 (3 << 23)
222 #define MX_APLLS_CLIKIN_13 (2 << 23)
223 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
224
225 /*
226 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
227 * #2 (ratio1) baseport-target
228 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
229 */
230 #define M5A_DPLL_MULT_12 (133 << 12)
231 #define M5A_DPLL_DIV_12 (5 << 8)
232 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
233 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
234 MX_APLLS_CLIKIN_12
235 #define M5A_DPLL_MULT_13 (266 << 12)
236 #define M5A_DPLL_DIV_13 (12 << 8)
237 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
238 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
239 MX_APLLS_CLIKIN_13
240 #define M5A_DPLL_MULT_19 (180 << 12)
241 #define M5A_DPLL_DIV_19 (12 << 8)
242 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
244 MX_APLLS_CLIKIN_19_2
245 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
246 #define M5B_DPLL_MULT_12 (50 << 12)
247 #define M5B_DPLL_DIV_12 (2 << 8)
248 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
249 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
250 MX_APLLS_CLIKIN_12
251 #define M5B_DPLL_MULT_13 (200 << 12)
252 #define M5B_DPLL_DIV_13 (12 << 8)
253
254 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
255 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
256 MX_APLLS_CLIKIN_13
257 #define M5B_DPLL_MULT_19 (125 << 12)
258 #define M5B_DPLL_DIV_19 (31 << 8)
259 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
260 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
261 MX_APLLS_CLIKIN_19_2
262 /*
263 * #4 (ratio2)
264 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
265 */
266 #define M3_DPLL_MULT_12 (55 << 12)
267 #define M3_DPLL_DIV_12 (1 << 8)
268 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
269 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
270 MX_APLLS_CLIKIN_12
271 #define M3_DPLL_MULT_13 (330 << 12)
272 #define M3_DPLL_DIV_13 (12 << 8)
273 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
274 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
275 MX_APLLS_CLIKIN_13
276 #define M3_DPLL_MULT_19 (275 << 12)
277 #define M3_DPLL_DIV_19 (15 << 8)
278 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
279 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
280 MX_APLLS_CLIKIN_19_2
281 /* boot (boot) */
282 #define MB_DPLL_MULT (1 << 12)
283 #define MB_DPLL_DIV (0 << 8)
284 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
285 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
286
287 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
288 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
289
290 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
291 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
292
293 /*
294 * 2430 - chassis (sedna)
295 * 165 (ratio1) same as above #2
296 * 150 (ratio1)
297 * 133 (ratio2) same as above #4
298 * 110 (ratio2) same as above #3
299 * 104 (ratio2)
300 * boot (boot)
301 */
302
303 /*
304 * 2420 Equivalent - mode registers
305 * PRCM II , target DPLL = 2*300MHz = 600MHz
306 */
307 #define MII_DPLL_MULT_12 (50 << 12)
308 #define MII_DPLL_DIV_12 (1 << 8)
309 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
310 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
311 MX_APLLS_CLIKIN_12
312 #define MII_DPLL_MULT_13 (300 << 12)
313 #define MII_DPLL_DIV_13 (12 << 8)
314 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
315 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
316 MX_APLLS_CLIKIN_13
317
318 /* PRCM III target DPLL = 2*266 = 532MHz*/
319 #define MIII_DPLL_MULT_12 (133 << 12)
320 #define MIII_DPLL_DIV_12 (5 << 8)
321 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324 #define MIII_DPLL_MULT_13 (266 << 12)
325 #define MIII_DPLL_DIV_13 (12 << 8)
326 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
328 MX_APLLS_CLIKIN_13
329
330 /* PRCM VII (boot bypass) */
331 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
332 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
333
334 /* High and low operation value */
335 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
336 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
337
338 /*
339 * These represent optimal values for common parts, it won't work for all.
340 * As long as you scale down, most parameters are still work, they just
341 * become sub-optimal. The RFR value goes in the opposite direction. If you
342 * don't adjust it down as your clock period increases the refresh interval
343 * will not be met. Setting all parameters for complete worst case may work,
344 * but may cut memory performance by 2x. Due to errata the DLLs need to be
345 * unlocked and their value needs run time calibration. A dynamic call is
346 * need for that as no single right value exists acorss production samples.
347 *
348 * Only the FULL speed values are given. Current code is such that rate
349 * changes must be made at DPLLoutx2. The actual value adjustment for low
350 * frequency operation will be handled by omap_set_performance()
351 *
352 * By having the boot loader boot up in the fastest L4 speed available likely
353 * will result in something which you can switch between.
354 */
355 #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
356 #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
357 #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
358 #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
359
360 /* MPU speed defines */
361 #define S12M 12000000
362 #define S13M 13000000
363 #define S19M 19200000
364 #define S26M 26000000
365 #define S100M 100000000
366 #define S133M 133000000
367 #define S150M 150000000
368 #define S165M 165000000
369 #define S200M 200000000
370 #define S266M 266000000
371 #define S300M 300000000
372 #define S330M 330000000
373 #define S400M 400000000
374 #define S532M 532000000
375 #define S600M 600000000
376 #define S660M 660000000
377
378 /*-------------------------------------------------------------------------
379 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
380 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
381 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
382 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
383 *
384 * Filling in table based on H4 boards and 2430-SDPs variants available.
385 * There are quite a few more rates combinations which could be defined.
386 *
387 * When multiple values are defined the start up will try and choose the
388 * fastest one. If a 'fast' value is defined, then automatically, the /2
389 * one should be included as it can be used. Generally having more that
390 * one fast set does not make sense, as static timings need to be changed
391 * to change the set. The exception is the bypass setting which is
392 * availble for low power bypass.
393 *
394 * Note: This table needs to be sorted, fastest to slowest.
395 *-------------------------------------------------------------------------*/
396 static struct prcm_config rate_table[] = {
397 /* PRCM II - FAST */
398 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
399 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
400 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
401 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
402 RATE_IN_242X},
403
404 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
405 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
406 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
407 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
408 RATE_IN_242X},
409
410 /* PRCM III - FAST */
411 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
412 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
413 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
414 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
415 RATE_IN_242X},
416
417 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
418 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
419 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
420 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
421 RATE_IN_242X},
422
423 /* PRCM II - SLOW */
424 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
425 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
426 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
427 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
428 RATE_IN_242X},
429
430 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
431 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
432 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
433 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
434 RATE_IN_242X},
435
436 /* PRCM III - SLOW */
437 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
438 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
439 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
440 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
441 RATE_IN_242X},
442
443 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
444 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
445 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
446 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
447 RATE_IN_242X},
448
449 /* PRCM-VII (boot-bypass) */
450 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
451 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
452 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
453 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
454 RATE_IN_242X},
455
456 /* PRCM-VII (boot-bypass) */
457 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
458 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
459 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
461 RATE_IN_242X},
462
463 /* PRCM #3 - ratio2 (ES2) - FAST */
464 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
465 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
466 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
468 V24XX_SDRC_RFR_CTRL_110MHz,
469 RATE_IN_243X},
470
471 /* PRCM #5a - ratio1 - FAST */
472 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
473 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
474 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
475 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
476 V24XX_SDRC_RFR_CTRL_133MHz,
477 RATE_IN_243X},
478
479 /* PRCM #5b - ratio1 - FAST */
480 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
481 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
482 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
483 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
484 V24XX_SDRC_RFR_CTRL_100MHz,
485 RATE_IN_243X},
486
487 /* PRCM #3 - ratio2 (ES2) - SLOW */
488 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
489 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
490 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
491 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
492 V24XX_SDRC_RFR_CTRL_110MHz,
493 RATE_IN_243X},
494
495 /* PRCM #5a - ratio1 - SLOW */
496 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
498 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
500 V24XX_SDRC_RFR_CTRL_133MHz,
501 RATE_IN_243X},
502
503 /* PRCM #5b - ratio1 - SLOW*/
504 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
505 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
506 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
507 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
508 V24XX_SDRC_RFR_CTRL_100MHz,
509 RATE_IN_243X},
510
511 /* PRCM-boot/bypass */
512 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
513 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
514 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
515 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
516 V24XX_SDRC_RFR_CTRL_BYPASS,
517 RATE_IN_243X},
518
519 /* PRCM-boot/bypass */
520 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
521 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
522 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
523 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
524 V24XX_SDRC_RFR_CTRL_BYPASS,
525 RATE_IN_243X},
526
527 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
528 };
529
530 /*-------------------------------------------------------------------------
531 * 24xx clock tree.
532 *
533 * NOTE:In many cases here we are assigning a 'default' parent. In many
534 * cases the parent is selectable. The get/set parent calls will also
535 * switch sources.
536 *
537 * Many some clocks say always_enabled, but they can be auto idled for
538 * power savings. They will always be available upon clock request.
539 *
540 * Several sources are given initial rates which may be wrong, this will
541 * be fixed up in the init func.
542 *
543 * Things are broadly separated below by clock domains. It is
544 * noteworthy that most periferals have dependencies on multiple clock
545 * domains. Many get their interface clocks from the L4 domain, but get
546 * functional clocks from fixed sources or other core domain derived
547 * clocks.
548 *-------------------------------------------------------------------------*/
549
550 /* Base external input clocks */
551 static struct clk func_32k_ck = {
552 .name = "func_32k_ck",
553 .rate = 32000,
554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
555 RATE_FIXED | ALWAYS_ENABLED,
556 };
557
558 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
559 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
560 .name = "osc_ck",
561 .rate = 26000000, /* fixed up in clock init */
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
563 RATE_FIXED | RATE_PROPAGATES,
564 };
565
566 /* With out modem likely 12MHz, with modem likely 13MHz */
567 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
568 .name = "sys_ck", /* ~ ref_clk also */
569 .parent = &osc_ck,
570 .rate = 13000000,
571 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
572 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
573 .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */
574 .recalc = &omap2_sys_clk_recalc,
575 };
576
577 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
578 .name = "alt_ck",
579 .rate = 54000000,
580 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
581 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
582 .recalc = &omap2_propagate_rate,
583 };
584
585 /*
586 * Analog domain root source clocks
587 */
588
589 /* dpll_ck, is broken out in to special cases through clksel */
590 static struct clk dpll_ck = {
591 .name = "dpll_ck",
592 .parent = &sys_ck, /* Can be func_32k also */
593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
594 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
595 .recalc = &omap2_clksel_recalc,
596 };
597
598 static struct clk apll96_ck = {
599 .name = "apll96_ck",
600 .parent = &sys_ck,
601 .rate = 96000000,
602 .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
603 RATE_FIXED | RATE_PROPAGATES,
604 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
605 .enable_bit = 0x2,
606 .recalc = &omap2_propagate_rate,
607 };
608
609 static struct clk apll54_ck = {
610 .name = "apll54_ck",
611 .parent = &sys_ck,
612 .rate = 54000000,
613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
614 RATE_FIXED | RATE_PROPAGATES,
615 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
616 .enable_bit = 0x6,
617 .recalc = &omap2_propagate_rate,
618 };
619
620 /*
621 * PRCM digital base sources
622 */
623 static struct clk func_54m_ck = {
624 .name = "func_54m_ck",
625 .parent = &apll54_ck, /* can also be alt_clk */
626 .rate = 54000000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
629 .src_offset = 5,
630 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
631 .enable_bit = 0xff,
632 .recalc = &omap2_propagate_rate,
633 };
634
635 static struct clk core_ck = {
636 .name = "core_ck",
637 .parent = &dpll_ck, /* can also be 32k */
638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
639 ALWAYS_ENABLED | RATE_PROPAGATES,
640 .recalc = &omap2_propagate_rate,
641 };
642
643 static struct clk sleep_ck = { /* sys_clk or 32k */
644 .name = "sleep_ck",
645 .parent = &func_32k_ck,
646 .rate = 32000,
647 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
648 .recalc = &omap2_propagate_rate,
649 };
650
651 static struct clk func_96m_ck = {
652 .name = "func_96m_ck",
653 .parent = &apll96_ck,
654 .rate = 96000000,
655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
656 RATE_FIXED | RATE_PROPAGATES,
657 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
658 .enable_bit = 0xff,
659 .recalc = &omap2_propagate_rate,
660 };
661
662 static struct clk func_48m_ck = {
663 .name = "func_48m_ck",
664 .parent = &apll96_ck, /* 96M or Alt */
665 .rate = 48000000,
666 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
667 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
668 .src_offset = 3,
669 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
670 .enable_bit = 0xff,
671 .recalc = &omap2_propagate_rate,
672 };
673
674 static struct clk func_12m_ck = {
675 .name = "func_12m_ck",
676 .parent = &func_48m_ck,
677 .rate = 12000000,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_FIXED | RATE_PROPAGATES,
680 .recalc = &omap2_propagate_rate,
681 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
682 .enable_bit = 0xff,
683 };
684
685 /* Secure timer, only available in secure mode */
686 static struct clk wdt1_osc_ck = {
687 .name = "ck_wdt1_osc",
688 .parent = &osc_ck,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
690 .recalc = &omap2_followparent_recalc,
691 };
692
693 static struct clk sys_clkout = {
694 .name = "sys_clkout",
695 .parent = &func_54m_ck,
696 .rate = 54000000,
697 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
698 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
699 .src_offset = 0,
700 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
701 .enable_bit = 7,
702 .rate_offset = 3,
703 .recalc = &omap2_clksel_recalc,
704 };
705
706 /* In 2430, new in 2420 ES2 */
707 static struct clk sys_clkout2 = {
708 .name = "sys_clkout2",
709 .parent = &func_54m_ck,
710 .rate = 54000000,
711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
712 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
713 .src_offset = 8,
714 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
715 .enable_bit = 15,
716 .rate_offset = 11,
717 .recalc = &omap2_clksel_recalc,
718 };
719
720 static struct clk emul_ck = {
721 .name = "emul_ck",
722 .parent = &func_54m_ck,
723 .flags = CLOCK_IN_OMAP242X,
724 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
725 .enable_bit = 0,
726 .recalc = &omap2_propagate_rate,
727
728 };
729
730 /*
731 * MPU clock domain
732 * Clocks:
733 * MPU_FCLK, MPU_ICLK
734 * INT_M_FCLK, INT_M_I_CLK
735 *
736 * - Individual clocks are hardware managed.
737 * - Base divider comes from: CM_CLKSEL_MPU
738 *
739 */
740 static struct clk mpu_ck = { /* Control cpu */
741 .name = "mpu_ck",
742 .parent = &core_ck,
743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
744 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
745 CONFIG_PARTICIPANT | RATE_PROPAGATES,
746 .rate_offset = 0, /* bits 0-4 */
747 .recalc = &omap2_clksel_recalc,
748 };
749
750 /*
751 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
752 * Clocks:
753 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
754 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
755 */
756 static struct clk iva2_1_fck = {
757 .name = "iva2_1_fck",
758 .parent = &core_ck,
759 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
760 DELAYED_APP | RATE_PROPAGATES |
761 CONFIG_PARTICIPANT,
762 .rate_offset = 0,
763 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
764 .enable_bit = 0,
765 .recalc = &omap2_clksel_recalc,
766 };
767
768 static struct clk iva2_1_ick = {
769 .name = "iva2_1_ick",
770 .parent = &iva2_1_fck,
771 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
772 DELAYED_APP | CONFIG_PARTICIPANT,
773 .rate_offset = 5,
774 .recalc = &omap2_clksel_recalc,
775 };
776
777 /*
778 * Won't be too specific here. The core clock comes into this block
779 * it is divided then tee'ed. One branch goes directly to xyz enable
780 * controls. The other branch gets further divided by 2 then possibly
781 * routed into a synchronizer and out of clocks abc.
782 */
783 static struct clk dsp_fck = {
784 .name = "dsp_fck",
785 .parent = &core_ck,
786 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
787 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
788 .rate_offset = 0,
789 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
790 .enable_bit = 0,
791 .recalc = &omap2_clksel_recalc,
792 };
793
794 static struct clk dsp_ick = {
795 .name = "dsp_ick", /* apparently ipi and isp */
796 .parent = &dsp_fck,
797 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
798 DELAYED_APP | CONFIG_PARTICIPANT,
799 .rate_offset = 5,
800 .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
801 .enable_bit = 1, /* for ipi */
802 .recalc = &omap2_clksel_recalc,
803 };
804
805 static struct clk iva1_ifck = {
806 .name = "iva1_ifck",
807 .parent = &core_ck,
808 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
809 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
810 .rate_offset= 8,
811 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
812 .enable_bit = 10,
813 .recalc = &omap2_clksel_recalc,
814 };
815
816 /* IVA1 mpu/int/i/f clocks are /2 of parent */
817 static struct clk iva1_mpu_int_ifck = {
818 .name = "iva1_mpu_int_ifck",
819 .parent = &iva1_ifck,
820 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
821 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
822 .enable_bit = 8,
823 .recalc = &omap2_clksel_recalc,
824 };
825
826 /*
827 * L3 clock domain
828 * L3 clocks are used for both interface and functional clocks to
829 * multiple entities. Some of these clocks are completely managed
830 * by hardware, and some others allow software control. Hardware
831 * managed ones general are based on directly CLK_REQ signals and
832 * various auto idle settings. The functional spec sets many of these
833 * as 'tie-high' for their enables.
834 *
835 * I-CLOCKS:
836 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
837 * CAM, HS-USB.
838 * F-CLOCK
839 * SSI.
840 *
841 * GPMC memories and SDRC have timing and clock sensitive registers which
842 * may very well need notification when the clock changes. Currently for low
843 * operating points, these are taken care of in sleep.S.
844 */
845 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
846 .name = "core_l3_ck",
847 .parent = &core_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
849 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
850 DELAYED_APP | CONFIG_PARTICIPANT |
851 RATE_PROPAGATES,
852 .rate_offset = 0,
853 .recalc = &omap2_clksel_recalc,
854 };
855
856 static struct clk usb_l4_ick = { /* FS-USB interface clock */
857 .name = "usb_l4_ick",
858 .parent = &core_l3_ck,
859 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
860 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
861 CONFIG_PARTICIPANT,
862 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
863 .enable_bit = 0,
864 .rate_offset = 25,
865 .recalc = &omap2_clksel_recalc,
866 };
867
868 /*
869 * SSI is in L3 management domain, its direct parent is core not l3,
870 * many core power domain entities are grouped into the L3 clock
871 * domain.
872 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
873 *
874 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
875 */
876 static struct clk ssi_ssr_sst_fck = {
877 .name = "ssi_fck",
878 .parent = &core_ck,
879 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
880 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
881 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
882 .enable_bit = 1,
883 .rate_offset = 20,
884 .recalc = &omap2_clksel_recalc,
885 };
886
887 /*
888 * GFX clock domain
889 * Clocks:
890 * GFX_FCLK, GFX_ICLK
891 * GFX_CG1(2d), GFX_CG2(3d)
892 *
893 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
894 * The 2d and 3d clocks run at a hardware determined
895 * divided value of fclk.
896 *
897 */
898 static struct clk gfx_3d_fck = {
899 .name = "gfx_3d_fck",
900 .parent = &core_l3_ck,
901 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
902 RATE_CKCTL | CM_GFX_SEL1,
903 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
904 .enable_bit = 2,
905 .rate_offset= 0,
906 .recalc = &omap2_clksel_recalc,
907 };
908
909 static struct clk gfx_2d_fck = {
910 .name = "gfx_2d_fck",
911 .parent = &core_l3_ck,
912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
913 RATE_CKCTL | CM_GFX_SEL1,
914 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
915 .enable_bit = 1,
916 .rate_offset= 0,
917 .recalc = &omap2_clksel_recalc,
918 };
919
920 static struct clk gfx_ick = {
921 .name = "gfx_ick", /* From l3 */
922 .parent = &core_l3_ck,
923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
924 RATE_CKCTL,
925 .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
926 .enable_bit = 0,
927 .recalc = &omap2_followparent_recalc,
928 };
929
930 /*
931 * Modem clock domain (2430)
932 * CLOCKS:
933 * MDM_OSC_CLK
934 * MDM_ICLK
935 */
936 static struct clk mdm_ick = { /* used both as a ick and fck */
937 .name = "mdm_ick",
938 .parent = &core_ck,
939 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
940 DELAYED_APP | CONFIG_PARTICIPANT,
941 .rate_offset = 0,
942 .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
943 .enable_bit = 0,
944 .recalc = &omap2_clksel_recalc,
945 };
946
947 static struct clk mdm_osc_ck = {
948 .name = "mdm_osc_ck",
949 .rate = 26000000,
950 .parent = &osc_ck,
951 .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
952 .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
953 .enable_bit = 1,
954 .recalc = &omap2_followparent_recalc,
955 };
956
957 /*
958 * L4 clock management domain
959 *
960 * This domain contains lots of interface clocks from the L4 interface, some
961 * functional clocks. Fixed APLL functional source clocks are managed in
962 * this domain.
963 */
964 static struct clk l4_ck = { /* used both as an ick and fck */
965 .name = "l4_ck",
966 .parent = &core_l3_ck,
967 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
968 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
969 DELAYED_APP | RATE_PROPAGATES,
970 .rate_offset = 5,
971 .recalc = &omap2_clksel_recalc,
972 };
973
974 static struct clk ssi_l4_ick = {
975 .name = "ssi_l4_ick",
976 .parent = &l4_ck,
977 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
978 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
979 .enable_bit = 1,
980 .recalc = &omap2_followparent_recalc,
981 };
982
983 /*
984 * DSS clock domain
985 * CLOCKs:
986 * DSS_L4_ICLK, DSS_L3_ICLK,
987 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
988 *
989 * DSS is both initiator and target.
990 */
991 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
992 .name = "dss_ick",
993 .parent = &l4_ck, /* really both l3 and l4 */
994 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
995 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
996 .enable_bit = 0,
997 .recalc = &omap2_followparent_recalc,
998 };
999
1000 static struct clk dss1_fck = {
1001 .name = "dss1_fck",
1002 .parent = &core_ck, /* Core or sys */
1003 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1004 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1005 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1006 .enable_bit = 0,
1007 .rate_offset = 8,
1008 .src_offset = 8,
1009 .recalc = &omap2_clksel_recalc,
1010 };
1011
1012 static struct clk dss2_fck = { /* Alt clk used in power management */
1013 .name = "dss2_fck",
1014 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1017 DELAYED_APP,
1018 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1019 .enable_bit = 1,
1020 .src_offset = 13,
1021 .recalc = &omap2_followparent_recalc,
1022 };
1023
1024 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1025 .name = "dss_54m_fck", /* 54m tv clk */
1026 .parent = &func_54m_ck,
1027 .rate = 54000000,
1028 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1029 RATE_FIXED | RATE_PROPAGATES,
1030 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1031 .enable_bit = 2,
1032 .recalc = &omap2_propagate_rate,
1033 };
1034
1035 /*
1036 * CORE power domain ICLK & FCLK defines.
1037 * Many of the these can have more than one possible parent. Entries
1038 * here will likely have an L4 interface parent, and may have multiple
1039 * functional clock parents.
1040 */
1041 static struct clk gpt1_ick = {
1042 .name = "gpt1_ick",
1043 .parent = &l4_ck,
1044 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1045 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
1046 .enable_bit = 0,
1047 .recalc = &omap2_followparent_recalc,
1048 };
1049
1050 static struct clk gpt1_fck = {
1051 .name = "gpt1_fck",
1052 .parent = &func_32k_ck,
1053 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1054 CM_WKUP_SEL1,
1055 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
1056 .enable_bit = 0,
1057 .src_offset = 0,
1058 .recalc = &omap2_followparent_recalc,
1059 };
1060
1061 static struct clk gpt2_ick = {
1062 .name = "gpt2_ick",
1063 .parent = &l4_ck,
1064 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1065 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1066 .enable_bit = 4,
1067 .recalc = &omap2_followparent_recalc,
1068 };
1069
1070 static struct clk gpt2_fck = {
1071 .name = "gpt2_fck",
1072 .parent = &func_32k_ck,
1073 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1074 CM_CORE_SEL2,
1075 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1076 .enable_bit = 4,
1077 .src_offset = 2,
1078 .recalc = &omap2_followparent_recalc,
1079 };
1080
1081 static struct clk gpt3_ick = {
1082 .name = "gpt3_ick",
1083 .parent = &l4_ck,
1084 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1085 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
1086 .enable_bit = 5,
1087 .recalc = &omap2_followparent_recalc,
1088 };
1089
1090 static struct clk gpt3_fck = {
1091 .name = "gpt3_fck",
1092 .parent = &func_32k_ck,
1093 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1094 CM_CORE_SEL2,
1095 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1096 .enable_bit = 5,
1097 .src_offset = 4,
1098 .recalc = &omap2_followparent_recalc,
1099 };
1100
1101 static struct clk gpt4_ick = {
1102 .name = "gpt4_ick",
1103 .parent = &l4_ck,
1104 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1105 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
1106 .enable_bit = 6,
1107 .recalc = &omap2_followparent_recalc,
1108 };
1109
1110 static struct clk gpt4_fck = {
1111 .name = "gpt4_fck",
1112 .parent = &func_32k_ck,
1113 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1114 CM_CORE_SEL2,
1115 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1116 .enable_bit = 6,
1117 .src_offset = 6,
1118 .recalc = &omap2_followparent_recalc,
1119 };
1120
1121 static struct clk gpt5_ick = {
1122 .name = "gpt5_ick",
1123 .parent = &l4_ck,
1124 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1125 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
1126 .enable_bit = 7,
1127 .recalc = &omap2_followparent_recalc,
1128 };
1129
1130 static struct clk gpt5_fck = {
1131 .name = "gpt5_fck",
1132 .parent = &func_32k_ck,
1133 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1134 CM_CORE_SEL2,
1135 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1136 .enable_bit = 7,
1137 .src_offset = 8,
1138 .recalc = &omap2_followparent_recalc,
1139 };
1140
1141 static struct clk gpt6_ick = {
1142 .name = "gpt6_ick",
1143 .parent = &l4_ck,
1144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1145 .enable_bit = 8,
1146 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
1147 .recalc = &omap2_followparent_recalc,
1148 };
1149
1150 static struct clk gpt6_fck = {
1151 .name = "gpt6_fck",
1152 .parent = &func_32k_ck,
1153 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1154 CM_CORE_SEL2,
1155 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1156 .enable_bit = 8,
1157 .src_offset = 10,
1158 .recalc = &omap2_followparent_recalc,
1159 };
1160
1161 static struct clk gpt7_ick = {
1162 .name = "gpt7_ick",
1163 .parent = &l4_ck,
1164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1165 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
1166 .enable_bit = 9,
1167 .recalc = &omap2_followparent_recalc,
1168 };
1169
1170 static struct clk gpt7_fck = {
1171 .name = "gpt7_fck",
1172 .parent = &func_32k_ck,
1173 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1174 CM_CORE_SEL2,
1175 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1176 .enable_bit = 9,
1177 .src_offset = 12,
1178 .recalc = &omap2_followparent_recalc,
1179 };
1180
1181 static struct clk gpt8_ick = {
1182 .name = "gpt8_ick",
1183 .parent = &l4_ck,
1184 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1185 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
1186 .enable_bit = 10,
1187 .recalc = &omap2_followparent_recalc,
1188 };
1189
1190 static struct clk gpt8_fck = {
1191 .name = "gpt8_fck",
1192 .parent = &func_32k_ck,
1193 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1194 CM_CORE_SEL2,
1195 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1196 .enable_bit = 10,
1197 .src_offset = 14,
1198 .recalc = &omap2_followparent_recalc,
1199 };
1200
1201 static struct clk gpt9_ick = {
1202 .name = "gpt9_ick",
1203 .parent = &l4_ck,
1204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1205 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1206 .enable_bit = 11,
1207 .recalc = &omap2_followparent_recalc,
1208 };
1209
1210 static struct clk gpt9_fck = {
1211 .name = "gpt9_fck",
1212 .parent = &func_32k_ck,
1213 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1214 CM_CORE_SEL2,
1215 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1216 .enable_bit = 11,
1217 .src_offset = 16,
1218 .recalc = &omap2_followparent_recalc,
1219 };
1220
1221 static struct clk gpt10_ick = {
1222 .name = "gpt10_ick",
1223 .parent = &l4_ck,
1224 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1225 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1226 .enable_bit = 12,
1227 .recalc = &omap2_followparent_recalc,
1228 };
1229
1230 static struct clk gpt10_fck = {
1231 .name = "gpt10_fck",
1232 .parent = &func_32k_ck,
1233 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1234 CM_CORE_SEL2,
1235 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1236 .enable_bit = 12,
1237 .src_offset = 18,
1238 .recalc = &omap2_followparent_recalc,
1239 };
1240
1241 static struct clk gpt11_ick = {
1242 .name = "gpt11_ick",
1243 .parent = &l4_ck,
1244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1245 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1246 .enable_bit = 13,
1247 .recalc = &omap2_followparent_recalc,
1248 };
1249
1250 static struct clk gpt11_fck = {
1251 .name = "gpt11_fck",
1252 .parent = &func_32k_ck,
1253 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1254 CM_CORE_SEL2,
1255 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1256 .enable_bit = 13,
1257 .src_offset = 20,
1258 .recalc = &omap2_followparent_recalc,
1259 };
1260
1261 static struct clk gpt12_ick = {
1262 .name = "gpt12_ick",
1263 .parent = &l4_ck,
1264 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1265 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
1266 .enable_bit = 14,
1267 .recalc = &omap2_followparent_recalc,
1268 };
1269
1270 static struct clk gpt12_fck = {
1271 .name = "gpt12_fck",
1272 .parent = &func_32k_ck,
1273 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1274 CM_CORE_SEL2,
1275 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1276 .enable_bit = 14,
1277 .src_offset = 22,
1278 .recalc = &omap2_followparent_recalc,
1279 };
1280
1281 static struct clk mcbsp1_ick = {
1282 .name = "mcbsp1_ick",
1283 .parent = &l4_ck,
1284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1285 .enable_bit = 15,
1286 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
1287 .recalc = &omap2_followparent_recalc,
1288 };
1289
1290 static struct clk mcbsp1_fck = {
1291 .name = "mcbsp1_fck",
1292 .parent = &func_96m_ck,
1293 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1294 .enable_bit = 15,
1295 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1296 .recalc = &omap2_followparent_recalc,
1297 };
1298
1299 static struct clk mcbsp2_ick = {
1300 .name = "mcbsp2_ick",
1301 .parent = &l4_ck,
1302 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1303 .enable_bit = 16,
1304 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1305 .recalc = &omap2_followparent_recalc,
1306 };
1307
1308 static struct clk mcbsp2_fck = {
1309 .name = "mcbsp2_fck",
1310 .parent = &func_96m_ck,
1311 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1312 .enable_bit = 16,
1313 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1314 .recalc = &omap2_followparent_recalc,
1315 };
1316
1317 static struct clk mcbsp3_ick = {
1318 .name = "mcbsp3_ick",
1319 .parent = &l4_ck,
1320 .flags = CLOCK_IN_OMAP243X,
1321 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1322 .enable_bit = 3,
1323 .recalc = &omap2_followparent_recalc,
1324 };
1325
1326 static struct clk mcbsp3_fck = {
1327 .name = "mcbsp3_fck",
1328 .parent = &func_96m_ck,
1329 .flags = CLOCK_IN_OMAP243X,
1330 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1331 .enable_bit = 3,
1332 .recalc = &omap2_followparent_recalc,
1333 };
1334
1335 static struct clk mcbsp4_ick = {
1336 .name = "mcbsp4_ick",
1337 .parent = &l4_ck,
1338 .flags = CLOCK_IN_OMAP243X,
1339 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1340 .enable_bit = 4,
1341 .recalc = &omap2_followparent_recalc,
1342 };
1343
1344 static struct clk mcbsp4_fck = {
1345 .name = "mcbsp4_fck",
1346 .parent = &func_96m_ck,
1347 .flags = CLOCK_IN_OMAP243X,
1348 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1349 .enable_bit = 4,
1350 .recalc = &omap2_followparent_recalc,
1351 };
1352
1353 static struct clk mcbsp5_ick = {
1354 .name = "mcbsp5_ick",
1355 .parent = &l4_ck,
1356 .flags = CLOCK_IN_OMAP243X,
1357 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1358 .enable_bit = 5,
1359 .recalc = &omap2_followparent_recalc,
1360 };
1361
1362 static struct clk mcbsp5_fck = {
1363 .name = "mcbsp5_fck",
1364 .parent = &func_96m_ck,
1365 .flags = CLOCK_IN_OMAP243X,
1366 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1367 .enable_bit = 5,
1368 .recalc = &omap2_followparent_recalc,
1369 };
1370
1371 static struct clk mcspi1_ick = {
1372 .name = "mcspi_ick",
1373 .id = 1,
1374 .parent = &l4_ck,
1375 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1376 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1377 .enable_bit = 17,
1378 .recalc = &omap2_followparent_recalc,
1379 };
1380
1381 static struct clk mcspi1_fck = {
1382 .name = "mcspi_fck",
1383 .id = 1,
1384 .parent = &func_48m_ck,
1385 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1386 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1387 .enable_bit = 17,
1388 .recalc = &omap2_followparent_recalc,
1389 };
1390
1391 static struct clk mcspi2_ick = {
1392 .name = "mcspi_ick",
1393 .id = 2,
1394 .parent = &l4_ck,
1395 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1396 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1397 .enable_bit = 18,
1398 .recalc = &omap2_followparent_recalc,
1399 };
1400
1401 static struct clk mcspi2_fck = {
1402 .name = "mcspi_fck",
1403 .id = 2,
1404 .parent = &func_48m_ck,
1405 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1406 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1407 .enable_bit = 18,
1408 .recalc = &omap2_followparent_recalc,
1409 };
1410
1411 static struct clk mcspi3_ick = {
1412 .name = "mcspi_ick",
1413 .id = 3,
1414 .parent = &l4_ck,
1415 .flags = CLOCK_IN_OMAP243X,
1416 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1417 .enable_bit = 9,
1418 .recalc = &omap2_followparent_recalc,
1419 };
1420
1421 static struct clk mcspi3_fck = {
1422 .name = "mcspi_fck",
1423 .id = 3,
1424 .parent = &func_48m_ck,
1425 .flags = CLOCK_IN_OMAP243X,
1426 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1427 .enable_bit = 9,
1428 .recalc = &omap2_followparent_recalc,
1429 };
1430
1431 static struct clk uart1_ick = {
1432 .name = "uart1_ick",
1433 .parent = &l4_ck,
1434 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1435 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1436 .enable_bit = 21,
1437 .recalc = &omap2_followparent_recalc,
1438 };
1439
1440 static struct clk uart1_fck = {
1441 .name = "uart1_fck",
1442 .parent = &func_48m_ck,
1443 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1444 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1445 .enable_bit = 21,
1446 .recalc = &omap2_followparent_recalc,
1447 };
1448
1449 static struct clk uart2_ick = {
1450 .name = "uart2_ick",
1451 .parent = &l4_ck,
1452 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1453 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1454 .enable_bit = 22,
1455 .recalc = &omap2_followparent_recalc,
1456 };
1457
1458 static struct clk uart2_fck = {
1459 .name = "uart2_fck",
1460 .parent = &func_48m_ck,
1461 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1462 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1463 .enable_bit = 22,
1464 .recalc = &omap2_followparent_recalc,
1465 };
1466
1467 static struct clk uart3_ick = {
1468 .name = "uart3_ick",
1469 .parent = &l4_ck,
1470 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1472 .enable_bit = 2,
1473 .recalc = &omap2_followparent_recalc,
1474 };
1475
1476 static struct clk uart3_fck = {
1477 .name = "uart3_fck",
1478 .parent = &func_48m_ck,
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1480 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1481 .enable_bit = 2,
1482 .recalc = &omap2_followparent_recalc,
1483 };
1484
1485 static struct clk gpios_ick = {
1486 .name = "gpios_ick",
1487 .parent = &l4_ck,
1488 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1489 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1490 .enable_bit = 2,
1491 .recalc = &omap2_followparent_recalc,
1492 };
1493
1494 static struct clk gpios_fck = {
1495 .name = "gpios_fck",
1496 .parent = &func_32k_ck,
1497 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1498 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1499 .enable_bit = 2,
1500 .recalc = &omap2_followparent_recalc,
1501 };
1502
1503 static struct clk mpu_wdt_ick = {
1504 .name = "mpu_wdt_ick",
1505 .parent = &l4_ck,
1506 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1507 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1508 .enable_bit = 3,
1509 .recalc = &omap2_followparent_recalc,
1510 };
1511
1512 static struct clk mpu_wdt_fck = {
1513 .name = "mpu_wdt_fck",
1514 .parent = &func_32k_ck,
1515 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1516 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1517 .enable_bit = 3,
1518 .recalc = &omap2_followparent_recalc,
1519 };
1520
1521 static struct clk sync_32k_ick = {
1522 .name = "sync_32k_ick",
1523 .parent = &l4_ck,
1524 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1525 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1526 .enable_bit = 1,
1527 .recalc = &omap2_followparent_recalc,
1528 };
1529 static struct clk wdt1_ick = {
1530 .name = "wdt1_ick",
1531 .parent = &l4_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1534 .enable_bit = 4,
1535 .recalc = &omap2_followparent_recalc,
1536 };
1537 static struct clk omapctrl_ick = {
1538 .name = "omapctrl_ick",
1539 .parent = &l4_ck,
1540 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1541 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1542 .enable_bit = 5,
1543 .recalc = &omap2_followparent_recalc,
1544 };
1545 static struct clk icr_ick = {
1546 .name = "icr_ick",
1547 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP243X,
1549 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1550 .enable_bit = 6,
1551 .recalc = &omap2_followparent_recalc,
1552 };
1553
1554 static struct clk cam_ick = {
1555 .name = "cam_ick",
1556 .parent = &l4_ck,
1557 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1559 .enable_bit = 31,
1560 .recalc = &omap2_followparent_recalc,
1561 };
1562
1563 static struct clk cam_fck = {
1564 .name = "cam_fck",
1565 .parent = &func_96m_ck,
1566 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1568 .enable_bit = 31,
1569 .recalc = &omap2_followparent_recalc,
1570 };
1571
1572 static struct clk mailboxes_ick = {
1573 .name = "mailboxes_ick",
1574 .parent = &l4_ck,
1575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1576 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1577 .enable_bit = 30,
1578 .recalc = &omap2_followparent_recalc,
1579 };
1580
1581 static struct clk wdt4_ick = {
1582 .name = "wdt4_ick",
1583 .parent = &l4_ck,
1584 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1585 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1586 .enable_bit = 29,
1587 .recalc = &omap2_followparent_recalc,
1588 };
1589
1590 static struct clk wdt4_fck = {
1591 .name = "wdt4_fck",
1592 .parent = &func_32k_ck,
1593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1594 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1595 .enable_bit = 29,
1596 .recalc = &omap2_followparent_recalc,
1597 };
1598
1599 static struct clk wdt3_ick = {
1600 .name = "wdt3_ick",
1601 .parent = &l4_ck,
1602 .flags = CLOCK_IN_OMAP242X,
1603 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1604 .enable_bit = 28,
1605 .recalc = &omap2_followparent_recalc,
1606 };
1607
1608 static struct clk wdt3_fck = {
1609 .name = "wdt3_fck",
1610 .parent = &func_32k_ck,
1611 .flags = CLOCK_IN_OMAP242X,
1612 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1613 .enable_bit = 28,
1614 .recalc = &omap2_followparent_recalc,
1615 };
1616
1617 static struct clk mspro_ick = {
1618 .name = "mspro_ick",
1619 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1622 .enable_bit = 27,
1623 .recalc = &omap2_followparent_recalc,
1624 };
1625
1626 static struct clk mspro_fck = {
1627 .name = "mspro_fck",
1628 .parent = &func_96m_ck,
1629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1631 .enable_bit = 27,
1632 .recalc = &omap2_followparent_recalc,
1633 };
1634
1635 static struct clk mmc_ick = {
1636 .name = "mmc_ick",
1637 .parent = &l4_ck,
1638 .flags = CLOCK_IN_OMAP242X,
1639 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1640 .enable_bit = 26,
1641 .recalc = &omap2_followparent_recalc,
1642 };
1643
1644 static struct clk mmc_fck = {
1645 .name = "mmc_fck",
1646 .parent = &func_96m_ck,
1647 .flags = CLOCK_IN_OMAP242X,
1648 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1649 .enable_bit = 26,
1650 .recalc = &omap2_followparent_recalc,
1651 };
1652
1653 static struct clk fac_ick = {
1654 .name = "fac_ick",
1655 .parent = &l4_ck,
1656 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1657 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1658 .enable_bit = 25,
1659 .recalc = &omap2_followparent_recalc,
1660 };
1661
1662 static struct clk fac_fck = {
1663 .name = "fac_fck",
1664 .parent = &func_12m_ck,
1665 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1667 .enable_bit = 25,
1668 .recalc = &omap2_followparent_recalc,
1669 };
1670
1671 static struct clk eac_ick = {
1672 .name = "eac_ick",
1673 .parent = &l4_ck,
1674 .flags = CLOCK_IN_OMAP242X,
1675 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1676 .enable_bit = 24,
1677 .recalc = &omap2_followparent_recalc,
1678 };
1679
1680 static struct clk eac_fck = {
1681 .name = "eac_fck",
1682 .parent = &func_96m_ck,
1683 .flags = CLOCK_IN_OMAP242X,
1684 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1685 .enable_bit = 24,
1686 .recalc = &omap2_followparent_recalc,
1687 };
1688
1689 static struct clk hdq_ick = {
1690 .name = "hdq_ick",
1691 .parent = &l4_ck,
1692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1693 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1694 .enable_bit = 23,
1695 .recalc = &omap2_followparent_recalc,
1696 };
1697
1698 static struct clk hdq_fck = {
1699 .name = "hdq_fck",
1700 .parent = &func_12m_ck,
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1703 .enable_bit = 23,
1704 .recalc = &omap2_followparent_recalc,
1705 };
1706
1707 static struct clk i2c2_ick = {
1708 .name = "i2c_ick",
1709 .id = 2,
1710 .parent = &l4_ck,
1711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1712 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1713 .enable_bit = 20,
1714 .recalc = &omap2_followparent_recalc,
1715 };
1716
1717 static struct clk i2c2_fck = {
1718 .name = "i2c_fck",
1719 .id = 2,
1720 .parent = &func_12m_ck,
1721 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1722 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1723 .enable_bit = 20,
1724 .recalc = &omap2_followparent_recalc,
1725 };
1726
1727 static struct clk i2chs2_fck = {
1728 .name = "i2chs2_fck",
1729 .parent = &func_96m_ck,
1730 .flags = CLOCK_IN_OMAP243X,
1731 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1732 .enable_bit = 20,
1733 .recalc = &omap2_followparent_recalc,
1734 };
1735
1736 static struct clk i2c1_ick = {
1737 .name = "i2c_ick",
1738 .id = 1,
1739 .parent = &l4_ck,
1740 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1742 .enable_bit = 19,
1743 .recalc = &omap2_followparent_recalc,
1744 };
1745
1746 static struct clk i2c1_fck = {
1747 .name = "i2c_fck",
1748 .id = 1,
1749 .parent = &func_12m_ck,
1750 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1751 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1752 .enable_bit = 19,
1753 .recalc = &omap2_followparent_recalc,
1754 };
1755
1756 static struct clk i2chs1_fck = {
1757 .name = "i2chs1_fck",
1758 .parent = &func_96m_ck,
1759 .flags = CLOCK_IN_OMAP243X,
1760 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1761 .enable_bit = 19,
1762 .recalc = &omap2_followparent_recalc,
1763 };
1764
1765 static struct clk vlynq_ick = {
1766 .name = "vlynq_ick",
1767 .parent = &core_l3_ck,
1768 .flags = CLOCK_IN_OMAP242X,
1769 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1770 .enable_bit = 3,
1771 .recalc = &omap2_followparent_recalc,
1772 };
1773
1774 static struct clk vlynq_fck = {
1775 .name = "vlynq_fck",
1776 .parent = &func_96m_ck,
1777 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1778 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1779 .enable_bit = 3,
1780 .src_offset = 15,
1781 .recalc = &omap2_followparent_recalc,
1782 };
1783
1784 static struct clk sdrc_ick = {
1785 .name = "sdrc_ick",
1786 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP243X,
1788 .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
1789 .enable_bit = 2,
1790 .recalc = &omap2_followparent_recalc,
1791 };
1792
1793 static struct clk des_ick = {
1794 .name = "des_ick",
1795 .parent = &l4_ck,
1796 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1797 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1798 .enable_bit = 0,
1799 .recalc = &omap2_followparent_recalc,
1800 };
1801
1802 static struct clk sha_ick = {
1803 .name = "sha_ick",
1804 .parent = &l4_ck,
1805 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1806 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1807 .enable_bit = 1,
1808 .recalc = &omap2_followparent_recalc,
1809 };
1810
1811 static struct clk rng_ick = {
1812 .name = "rng_ick",
1813 .parent = &l4_ck,
1814 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1815 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1816 .enable_bit = 2,
1817 .recalc = &omap2_followparent_recalc,
1818 };
1819
1820 static struct clk aes_ick = {
1821 .name = "aes_ick",
1822 .parent = &l4_ck,
1823 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1824 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1825 .enable_bit = 3,
1826 .recalc = &omap2_followparent_recalc,
1827 };
1828
1829 static struct clk pka_ick = {
1830 .name = "pka_ick",
1831 .parent = &l4_ck,
1832 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1833 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1834 .enable_bit = 4,
1835 .recalc = &omap2_followparent_recalc,
1836 };
1837
1838 static struct clk usb_fck = {
1839 .name = "usb_fck",
1840 .parent = &func_48m_ck,
1841 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1842 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1843 .enable_bit = 0,
1844 .recalc = &omap2_followparent_recalc,
1845 };
1846
1847 static struct clk usbhs_ick = {
1848 .name = "usbhs_ick",
1849 .parent = &core_l3_ck,
1850 .flags = CLOCK_IN_OMAP243X,
1851 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1852 .enable_bit = 6,
1853 .recalc = &omap2_followparent_recalc,
1854 };
1855
1856 static struct clk mmchs1_ick = {
1857 .name = "mmchs1_ick",
1858 .parent = &l4_ck,
1859 .flags = CLOCK_IN_OMAP243X,
1860 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1861 .enable_bit = 7,
1862 .recalc = &omap2_followparent_recalc,
1863 };
1864
1865 static struct clk mmchs1_fck = {
1866 .name = "mmchs1_fck",
1867 .parent = &func_96m_ck,
1868 .flags = CLOCK_IN_OMAP243X,
1869 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1870 .enable_bit = 7,
1871 .recalc = &omap2_followparent_recalc,
1872 };
1873
1874 static struct clk mmchs2_ick = {
1875 .name = "mmchs2_ick",
1876 .parent = &l4_ck,
1877 .flags = CLOCK_IN_OMAP243X,
1878 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1879 .enable_bit = 8,
1880 .recalc = &omap2_followparent_recalc,
1881 };
1882
1883 static struct clk mmchs2_fck = {
1884 .name = "mmchs2_fck",
1885 .parent = &func_96m_ck,
1886 .flags = CLOCK_IN_OMAP243X,
1887 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1888 .enable_bit = 8,
1889 .recalc = &omap2_followparent_recalc,
1890 };
1891
1892 static struct clk gpio5_ick = {
1893 .name = "gpio5_ick",
1894 .parent = &l4_ck,
1895 .flags = CLOCK_IN_OMAP243X,
1896 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1897 .enable_bit = 10,
1898 .recalc = &omap2_followparent_recalc,
1899 };
1900
1901 static struct clk gpio5_fck = {
1902 .name = "gpio5_fck",
1903 .parent = &func_32k_ck,
1904 .flags = CLOCK_IN_OMAP243X,
1905 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1906 .enable_bit = 10,
1907 .recalc = &omap2_followparent_recalc,
1908 };
1909
1910 static struct clk mdm_intc_ick = {
1911 .name = "mdm_intc_ick",
1912 .parent = &l4_ck,
1913 .flags = CLOCK_IN_OMAP243X,
1914 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1915 .enable_bit = 11,
1916 .recalc = &omap2_followparent_recalc,
1917 };
1918
1919 static struct clk mmchsdb1_fck = {
1920 .name = "mmchsdb1_fck",
1921 .parent = &func_32k_ck,
1922 .flags = CLOCK_IN_OMAP243X,
1923 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1924 .enable_bit = 16,
1925 .recalc = &omap2_followparent_recalc,
1926 };
1927
1928 static struct clk mmchsdb2_fck = {
1929 .name = "mmchsdb2_fck",
1930 .parent = &func_32k_ck,
1931 .flags = CLOCK_IN_OMAP243X,
1932 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1933 .enable_bit = 17,
1934 .recalc = &omap2_followparent_recalc,
1935 };
1936
1937 /*
1938 * This clock is a composite clock which does entire set changes then
1939 * forces a rebalance. It keys on the MPU speed, but it really could
1940 * be any key speed part of a set in the rate table.
1941 *
1942 * to really change a set, you need memory table sets which get changed
1943 * in sram, pre-notifiers & post notifiers, changing the top set, without
1944 * having low level display recalc's won't work... this is why dpm notifiers
1945 * work, isr's off, walk a list of clocks already _off_ and not messing with
1946 * the bus.
1947 *
1948 * This clock should have no parent. It embodies the entire upper level
1949 * active set. A parent will mess up some of the init also.
1950 */
1951 static struct clk virt_prcm_set = {
1952 .name = "virt_prcm_set",
1953 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1954 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1955 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1956 .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
1957 .set_rate = &omap2_select_table_rate,
1958 .round_rate = &omap2_round_to_table_rate,
1959 };
1960
1961 static struct clk *onchip_clks[] = {
1962 /* external root sources */
1963 &func_32k_ck,
1964 &osc_ck,
1965 &sys_ck,
1966 &alt_ck,
1967 /* internal analog sources */
1968 &dpll_ck,
1969 &apll96_ck,
1970 &apll54_ck,
1971 /* internal prcm root sources */
1972 &func_54m_ck,
1973 &core_ck,
1974 &sleep_ck,
1975 &func_96m_ck,
1976 &func_48m_ck,
1977 &func_12m_ck,
1978 &wdt1_osc_ck,
1979 &sys_clkout,
1980 &sys_clkout2,
1981 &emul_ck,
1982 /* mpu domain clocks */
1983 &mpu_ck,
1984 /* dsp domain clocks */
1985 &iva2_1_fck, /* 2430 */
1986 &iva2_1_ick,
1987 &dsp_ick, /* 2420 */
1988 &dsp_fck,
1989 &iva1_ifck,
1990 &iva1_mpu_int_ifck,
1991 /* GFX domain clocks */
1992 &gfx_3d_fck,
1993 &gfx_2d_fck,
1994 &gfx_ick,
1995 /* Modem domain clocks */
1996 &mdm_ick,
1997 &mdm_osc_ck,
1998 /* DSS domain clocks */
1999 &dss_ick,
2000 &dss1_fck,
2001 &dss2_fck,
2002 &dss_54m_fck,
2003 /* L3 domain clocks */
2004 &core_l3_ck,
2005 &ssi_ssr_sst_fck,
2006 &usb_l4_ick,
2007 /* L4 domain clocks */
2008 &l4_ck, /* used as both core_l4 and wu_l4 */
2009 &ssi_l4_ick,
2010 /* virtual meta-group clock */
2011 &virt_prcm_set,
2012 /* general l4 interface ck, multi-parent functional clk */
2013 &gpt1_ick,
2014 &gpt1_fck,
2015 &gpt2_ick,
2016 &gpt2_fck,
2017 &gpt3_ick,
2018 &gpt3_fck,
2019 &gpt4_ick,
2020 &gpt4_fck,
2021 &gpt5_ick,
2022 &gpt5_fck,
2023 &gpt6_ick,
2024 &gpt6_fck,
2025 &gpt7_ick,
2026 &gpt7_fck,
2027 &gpt8_ick,
2028 &gpt8_fck,
2029 &gpt9_ick,
2030 &gpt9_fck,
2031 &gpt10_ick,
2032 &gpt10_fck,
2033 &gpt11_ick,
2034 &gpt11_fck,
2035 &gpt12_ick,
2036 &gpt12_fck,
2037 &mcbsp1_ick,
2038 &mcbsp1_fck,
2039 &mcbsp2_ick,
2040 &mcbsp2_fck,
2041 &mcbsp3_ick,
2042 &mcbsp3_fck,
2043 &mcbsp4_ick,
2044 &mcbsp4_fck,
2045 &mcbsp5_ick,
2046 &mcbsp5_fck,
2047 &mcspi1_ick,
2048 &mcspi1_fck,
2049 &mcspi2_ick,
2050 &mcspi2_fck,
2051 &mcspi3_ick,
2052 &mcspi3_fck,
2053 &uart1_ick,
2054 &uart1_fck,
2055 &uart2_ick,
2056 &uart2_fck,
2057 &uart3_ick,
2058 &uart3_fck,
2059 &gpios_ick,
2060 &gpios_fck,
2061 &mpu_wdt_ick,
2062 &mpu_wdt_fck,
2063 &sync_32k_ick,
2064 &wdt1_ick,
2065 &omapctrl_ick,
2066 &icr_ick,
2067 &cam_fck,
2068 &cam_ick,
2069 &mailboxes_ick,
2070 &wdt4_ick,
2071 &wdt4_fck,
2072 &wdt3_ick,
2073 &wdt3_fck,
2074 &mspro_ick,
2075 &mspro_fck,
2076 &mmc_ick,
2077 &mmc_fck,
2078 &fac_ick,
2079 &fac_fck,
2080 &eac_ick,
2081 &eac_fck,
2082 &hdq_ick,
2083 &hdq_fck,
2084 &i2c1_ick,
2085 &i2c1_fck,
2086 &i2chs1_fck,
2087 &i2c2_ick,
2088 &i2c2_fck,
2089 &i2chs2_fck,
2090 &vlynq_ick,
2091 &vlynq_fck,
2092 &sdrc_ick,
2093 &des_ick,
2094 &sha_ick,
2095 &rng_ick,
2096 &aes_ick,
2097 &pka_ick,
2098 &usb_fck,
2099 &usbhs_ick,
2100 &mmchs1_ick,
2101 &mmchs1_fck,
2102 &mmchs2_ick,
2103 &mmchs2_fck,
2104 &gpio5_ick,
2105 &gpio5_fck,
2106 &mdm_intc_ick,
2107 &mmchsdb1_fck,
2108 &mmchsdb2_fck,
2109 };
2110
2111 #endif
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