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Linux 2.6.25-rc4
[linux-2.6/next.git] / arch / arm / plat-omap / gpio.c
blob56f4d1394d562bdfc652a2d7f13ee436042ed88c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20
21 #include <asm/hardware.h>
22 #include <asm/irq.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
26
27 #include <asm/io.h>
28
29 /*
30 * OMAP1510 GPIO registers
31 */
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41 #define OMAP1510_IH_GPIO_BASE 64
42
43 /*
44 * OMAP1610 specific GPIO registers
45 */
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68 /*
69 * OMAP730 specific GPIO registers
70 */
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
83
84 /*
85 * omap24xx specific GPIO registers
86 */
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
122 /*
123 * omap34xx specific GPIO registers
124 */
125
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
134 struct gpio_bank {
135 void __iomem *base;
136 u16 irq;
137 u16 virtual_irq_start;
138 int method;
139 u32 reserved_map;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
141 u32 suspend_wakeup;
142 u32 saved_wakeup;
143 #endif
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151 #endif
152 spinlock_t lock;
153 };
154
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
160
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
168 };
169 #endif
170
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175 };
176 #endif
177
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
187 };
188 #endif
189
190 #ifdef CONFIG_ARCH_OMAP24XX
191
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
197 };
198
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
205 };
206
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217 };
218
219 #endif
220
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
223
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
225 {
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
230 }
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
235 }
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
240 }
241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
245 }
246
247 static inline int get_gpio_index(int gpio)
248 {
249 if (cpu_is_omap730())
250 return gpio & 0x1f;
251 if (cpu_is_omap24xx())
252 return gpio & 0x1f;
253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
255 return gpio & 0x0f;
256 }
257
258 static inline int gpio_valid(int gpio)
259 {
260 if (gpio < 0)
261 return -1;
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
264 return -1;
265 return 0;
266 }
267 if (cpu_is_omap15xx() && gpio < 16)
268 return 0;
269 if ((cpu_is_omap16xx()) && gpio < 64)
270 return 0;
271 if (cpu_is_omap730() && gpio < 192)
272 return 0;
273 if (cpu_is_omap24xx() && gpio < 128)
274 return 0;
275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
277 return -1;
278 }
279
280 static int check_gpio(int gpio)
281 {
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
284 dump_stack();
285 return -1;
286 }
287 return 0;
288 }
289
290 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
291 {
292 void __iomem *reg = bank->base;
293 u32 l;
294
295 switch (bank->method) {
296 #ifdef CONFIG_ARCH_OMAP1
297 case METHOD_MPUIO:
298 reg += OMAP_MPUIO_IO_CNTL;
299 break;
300 #endif
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
304 break;
305 #endif
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
309 break;
310 #endif
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
314 break;
315 #endif
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
319 break;
320 #endif
321 default:
322 WARN_ON(1);
323 return;
324 }
325 l = __raw_readl(reg);
326 if (is_input)
327 l |= 1 << gpio;
328 else
329 l &= ~(1 << gpio);
330 __raw_writel(l, reg);
331 }
332
333 void omap_set_gpio_direction(int gpio, int is_input)
334 {
335 struct gpio_bank *bank;
336
337 if (check_gpio(gpio) < 0)
338 return;
339 bank = get_gpio_bank(gpio);
340 spin_lock(&bank->lock);
341 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
342 spin_unlock(&bank->lock);
343 }
344
345 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
346 {
347 void __iomem *reg = bank->base;
348 u32 l = 0;
349
350 switch (bank->method) {
351 #ifdef CONFIG_ARCH_OMAP1
352 case METHOD_MPUIO:
353 reg += OMAP_MPUIO_OUTPUT;
354 l = __raw_readl(reg);
355 if (enable)
356 l |= 1 << gpio;
357 else
358 l &= ~(1 << gpio);
359 break;
360 #endif
361 #ifdef CONFIG_ARCH_OMAP15XX
362 case METHOD_GPIO_1510:
363 reg += OMAP1510_GPIO_DATA_OUTPUT;
364 l = __raw_readl(reg);
365 if (enable)
366 l |= 1 << gpio;
367 else
368 l &= ~(1 << gpio);
369 break;
370 #endif
371 #ifdef CONFIG_ARCH_OMAP16XX
372 case METHOD_GPIO_1610:
373 if (enable)
374 reg += OMAP1610_GPIO_SET_DATAOUT;
375 else
376 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
377 l = 1 << gpio;
378 break;
379 #endif
380 #ifdef CONFIG_ARCH_OMAP730
381 case METHOD_GPIO_730:
382 reg += OMAP730_GPIO_DATA_OUTPUT;
383 l = __raw_readl(reg);
384 if (enable)
385 l |= 1 << gpio;
386 else
387 l &= ~(1 << gpio);
388 break;
389 #endif
390 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
391 case METHOD_GPIO_24XX:
392 if (enable)
393 reg += OMAP24XX_GPIO_SETDATAOUT;
394 else
395 reg += OMAP24XX_GPIO_CLEARDATAOUT;
396 l = 1 << gpio;
397 break;
398 #endif
399 default:
400 WARN_ON(1);
401 return;
402 }
403 __raw_writel(l, reg);
404 }
405
406 void omap_set_gpio_dataout(int gpio, int enable)
407 {
408 struct gpio_bank *bank;
409
410 if (check_gpio(gpio) < 0)
411 return;
412 bank = get_gpio_bank(gpio);
413 spin_lock(&bank->lock);
414 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
415 spin_unlock(&bank->lock);
416 }
417
418 int omap_get_gpio_datain(int gpio)
419 {
420 struct gpio_bank *bank;
421 void __iomem *reg;
422
423 if (check_gpio(gpio) < 0)
424 return -EINVAL;
425 bank = get_gpio_bank(gpio);
426 reg = bank->base;
427 switch (bank->method) {
428 #ifdef CONFIG_ARCH_OMAP1
429 case METHOD_MPUIO:
430 reg += OMAP_MPUIO_INPUT_LATCH;
431 break;
432 #endif
433 #ifdef CONFIG_ARCH_OMAP15XX
434 case METHOD_GPIO_1510:
435 reg += OMAP1510_GPIO_DATA_INPUT;
436 break;
437 #endif
438 #ifdef CONFIG_ARCH_OMAP16XX
439 case METHOD_GPIO_1610:
440 reg += OMAP1610_GPIO_DATAIN;
441 break;
442 #endif
443 #ifdef CONFIG_ARCH_OMAP730
444 case METHOD_GPIO_730:
445 reg += OMAP730_GPIO_DATA_INPUT;
446 break;
447 #endif
448 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
449 case METHOD_GPIO_24XX:
450 reg += OMAP24XX_GPIO_DATAIN;
451 break;
452 #endif
453 default:
454 return -EINVAL;
455 }
456 return (__raw_readl(reg)
457 & (1 << get_gpio_index(gpio))) != 0;
458 }
459
460 #define MOD_REG_BIT(reg, bit_mask, set) \
461 do { \
462 int l = __raw_readl(base + reg); \
463 if (set) l |= bit_mask; \
464 else l &= ~bit_mask; \
465 __raw_writel(l, base + reg); \
466 } while(0)
467
468 void omap_set_gpio_debounce(int gpio, int enable)
469 {
470 struct gpio_bank *bank;
471 void __iomem *reg;
472 u32 val, l = 1 << get_gpio_index(gpio);
473
474 if (cpu_class_is_omap1())
475 return;
476
477 bank = get_gpio_bank(gpio);
478 reg = bank->base;
479
480 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
481 val = __raw_readl(reg);
482
483 if (enable)
484 val |= l;
485 else
486 val &= ~l;
487
488 __raw_writel(val, reg);
489 }
490 EXPORT_SYMBOL(omap_set_gpio_debounce);
491
492 void omap_set_gpio_debounce_time(int gpio, int enc_time)
493 {
494 struct gpio_bank *bank;
495 void __iomem *reg;
496
497 if (cpu_class_is_omap1())
498 return;
499
500 bank = get_gpio_bank(gpio);
501 reg = bank->base;
502
503 enc_time &= 0xff;
504 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
505 __raw_writel(enc_time, reg);
506 }
507 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
508
509 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
510 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
511 int trigger)
512 {
513 void __iomem *base = bank->base;
514 u32 gpio_bit = 1 << gpio;
515
516 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
517 trigger & __IRQT_LOWLVL);
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
519 trigger & __IRQT_HIGHLVL);
520 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
521 trigger & __IRQT_RISEDGE);
522 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
523 trigger & __IRQT_FALEDGE);
524
525 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
526 if (trigger != 0)
527 __raw_writel(1 << gpio, bank->base
528 + OMAP24XX_GPIO_SETWKUENA);
529 else
530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_CLEARWKUENA);
532 } else {
533 if (trigger != 0)
534 bank->enabled_non_wakeup_gpios |= gpio_bit;
535 else
536 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
537 }
538
539 /*
540 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
541 * level triggering requested.
542 */
543 }
544 #endif
545
546 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
547 {
548 void __iomem *reg = bank->base;
549 u32 l = 0;
550
551 switch (bank->method) {
552 #ifdef CONFIG_ARCH_OMAP1
553 case METHOD_MPUIO:
554 reg += OMAP_MPUIO_GPIO_INT_EDGE;
555 l = __raw_readl(reg);
556 if (trigger & __IRQT_RISEDGE)
557 l |= 1 << gpio;
558 else if (trigger & __IRQT_FALEDGE)
559 l &= ~(1 << gpio);
560 else
561 goto bad;
562 break;
563 #endif
564 #ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
568 if (trigger & __IRQT_RISEDGE)
569 l |= 1 << gpio;
570 else if (trigger & __IRQT_FALEDGE)
571 l &= ~(1 << gpio);
572 else
573 goto bad;
574 break;
575 #endif
576 #ifdef CONFIG_ARCH_OMAP16XX
577 case METHOD_GPIO_1610:
578 if (gpio & 0x08)
579 reg += OMAP1610_GPIO_EDGE_CTRL2;
580 else
581 reg += OMAP1610_GPIO_EDGE_CTRL1;
582 gpio &= 0x07;
583 l = __raw_readl(reg);
584 l &= ~(3 << (gpio << 1));
585 if (trigger & __IRQT_RISEDGE)
586 l |= 2 << (gpio << 1);
587 if (trigger & __IRQT_FALEDGE)
588 l |= 1 << (gpio << 1);
589 if (trigger)
590 /* Enable wake-up during idle for dynamic tick */
591 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
592 else
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
594 break;
595 #endif
596 #ifdef CONFIG_ARCH_OMAP730
597 case METHOD_GPIO_730:
598 reg += OMAP730_GPIO_INT_CONTROL;
599 l = __raw_readl(reg);
600 if (trigger & __IRQT_RISEDGE)
601 l |= 1 << gpio;
602 else if (trigger & __IRQT_FALEDGE)
603 l &= ~(1 << gpio);
604 else
605 goto bad;
606 break;
607 #endif
608 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
609 case METHOD_GPIO_24XX:
610 set_24xx_gpio_triggering(bank, gpio, trigger);
611 break;
612 #endif
613 default:
614 goto bad;
615 }
616 __raw_writel(l, reg);
617 return 0;
618 bad:
619 return -EINVAL;
620 }
621
622 static int gpio_irq_type(unsigned irq, unsigned type)
623 {
624 struct gpio_bank *bank;
625 unsigned gpio;
626 int retval;
627
628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
630 else
631 gpio = irq - IH_GPIO_BASE;
632
633 if (check_gpio(gpio) < 0)
634 return -EINVAL;
635
636 if (type & ~IRQ_TYPE_SENSE_MASK)
637 return -EINVAL;
638
639 /* OMAP1 allows only only edge triggering */
640 if (!cpu_class_is_omap2()
641 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
642 return -EINVAL;
643
644 bank = get_irq_chip_data(irq);
645 spin_lock(&bank->lock);
646 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
647 if (retval == 0) {
648 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
649 irq_desc[irq].status |= type;
650 }
651 spin_unlock(&bank->lock);
652 return retval;
653 }
654
655 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656 {
657 void __iomem *reg = bank->base;
658
659 switch (bank->method) {
660 #ifdef CONFIG_ARCH_OMAP1
661 case METHOD_MPUIO:
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
664 return;
665 #endif
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510:
668 reg += OMAP1510_GPIO_INT_STATUS;
669 break;
670 #endif
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610:
673 reg += OMAP1610_GPIO_IRQSTATUS1;
674 break;
675 #endif
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_STATUS;
679 break;
680 #endif
681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1;
684 break;
685 #endif
686 default:
687 WARN_ON(1);
688 return;
689 }
690 __raw_writel(gpio_mask, reg);
691
692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
696 #endif
697 }
698
699 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
700 {
701 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
702 }
703
704 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
705 {
706 void __iomem *reg = bank->base;
707 int inv = 0;
708 u32 l;
709 u32 mask;
710
711 switch (bank->method) {
712 #ifdef CONFIG_ARCH_OMAP1
713 case METHOD_MPUIO:
714 reg += OMAP_MPUIO_GPIO_MASKIT;
715 mask = 0xffff;
716 inv = 1;
717 break;
718 #endif
719 #ifdef CONFIG_ARCH_OMAP15XX
720 case METHOD_GPIO_1510:
721 reg += OMAP1510_GPIO_INT_MASK;
722 mask = 0xffff;
723 inv = 1;
724 break;
725 #endif
726 #ifdef CONFIG_ARCH_OMAP16XX
727 case METHOD_GPIO_1610:
728 reg += OMAP1610_GPIO_IRQENABLE1;
729 mask = 0xffff;
730 break;
731 #endif
732 #ifdef CONFIG_ARCH_OMAP730
733 case METHOD_GPIO_730:
734 reg += OMAP730_GPIO_INT_MASK;
735 mask = 0xffffffff;
736 inv = 1;
737 break;
738 #endif
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1;
742 mask = 0xffffffff;
743 break;
744 #endif
745 default:
746 WARN_ON(1);
747 return 0;
748 }
749
750 l = __raw_readl(reg);
751 if (inv)
752 l = ~l;
753 l &= mask;
754 return l;
755 }
756
757 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
758 {
759 void __iomem *reg = bank->base;
760 u32 l;
761
762 switch (bank->method) {
763 #ifdef CONFIG_ARCH_OMAP1
764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_MASKIT;
766 l = __raw_readl(reg);
767 if (enable)
768 l &= ~(gpio_mask);
769 else
770 l |= gpio_mask;
771 break;
772 #endif
773 #ifdef CONFIG_ARCH_OMAP15XX
774 case METHOD_GPIO_1510:
775 reg += OMAP1510_GPIO_INT_MASK;
776 l = __raw_readl(reg);
777 if (enable)
778 l &= ~(gpio_mask);
779 else
780 l |= gpio_mask;
781 break;
782 #endif
783 #ifdef CONFIG_ARCH_OMAP16XX
784 case METHOD_GPIO_1610:
785 if (enable)
786 reg += OMAP1610_GPIO_SET_IRQENABLE1;
787 else
788 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
789 l = gpio_mask;
790 break;
791 #endif
792 #ifdef CONFIG_ARCH_OMAP730
793 case METHOD_GPIO_730:
794 reg += OMAP730_GPIO_INT_MASK;
795 l = __raw_readl(reg);
796 if (enable)
797 l &= ~(gpio_mask);
798 else
799 l |= gpio_mask;
800 break;
801 #endif
802 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX:
804 if (enable)
805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
806 else
807 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
808 l = gpio_mask;
809 break;
810 #endif
811 default:
812 WARN_ON(1);
813 return;
814 }
815 __raw_writel(l, reg);
816 }
817
818 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
819 {
820 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
821 }
822
823 /*
824 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
825 * 1510 does not seem to have a wake-up register. If JTAG is connected
826 * to the target, system will wake up always on GPIO events. While
827 * system is running all registered GPIO interrupts need to have wake-up
828 * enabled. When system is suspended, only selected GPIO interrupts need
829 * to have wake-up enabled.
830 */
831 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
832 {
833 switch (bank->method) {
834 #ifdef CONFIG_ARCH_OMAP16XX
835 case METHOD_MPUIO:
836 case METHOD_GPIO_1610:
837 spin_lock(&bank->lock);
838 if (enable) {
839 bank->suspend_wakeup |= (1 << gpio);
840 enable_irq_wake(bank->irq);
841 } else {
842 disable_irq_wake(bank->irq);
843 bank->suspend_wakeup &= ~(1 << gpio);
844 }
845 spin_unlock(&bank->lock);
846 return 0;
847 #endif
848 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
849 case METHOD_GPIO_24XX:
850 if (bank->non_wakeup_gpios & (1 << gpio)) {
851 printk(KERN_ERR "Unable to modify wakeup on "
852 "non-wakeup GPIO%d\n",
853 (bank - gpio_bank) * 32 + gpio);
854 return -EINVAL;
855 }
856 spin_lock(&bank->lock);
857 if (enable) {
858 bank->suspend_wakeup |= (1 << gpio);
859 enable_irq_wake(bank->irq);
860 } else {
861 disable_irq_wake(bank->irq);
862 bank->suspend_wakeup &= ~(1 << gpio);
863 }
864 spin_unlock(&bank->lock);
865 return 0;
866 #endif
867 default:
868 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
869 bank->method);
870 return -EINVAL;
871 }
872 }
873
874 static void _reset_gpio(struct gpio_bank *bank, int gpio)
875 {
876 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
877 _set_gpio_irqenable(bank, gpio, 0);
878 _clear_gpio_irqstatus(bank, gpio);
879 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
880 }
881
882 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
883 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
884 {
885 unsigned int gpio = irq - IH_GPIO_BASE;
886 struct gpio_bank *bank;
887 int retval;
888
889 if (check_gpio(gpio) < 0)
890 return -ENODEV;
891 bank = get_irq_chip_data(irq);
892 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
893
894 return retval;
895 }
896
897 int omap_request_gpio(int gpio)
898 {
899 struct gpio_bank *bank;
900
901 if (check_gpio(gpio) < 0)
902 return -EINVAL;
903
904 bank = get_gpio_bank(gpio);
905 spin_lock(&bank->lock);
906 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
907 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
908 dump_stack();
909 spin_unlock(&bank->lock);
910 return -1;
911 }
912 bank->reserved_map |= (1 << get_gpio_index(gpio));
913
914 /* Set trigger to none. You need to enable the desired trigger with
915 * request_irq() or set_irq_type().
916 */
917 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
918
919 #ifdef CONFIG_ARCH_OMAP15XX
920 if (bank->method == METHOD_GPIO_1510) {
921 void __iomem *reg;
922
923 /* Claim the pin for MPU */
924 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
925 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
926 }
927 #endif
928 spin_unlock(&bank->lock);
929
930 return 0;
931 }
932
933 void omap_free_gpio(int gpio)
934 {
935 struct gpio_bank *bank;
936
937 if (check_gpio(gpio) < 0)
938 return;
939 bank = get_gpio_bank(gpio);
940 spin_lock(&bank->lock);
941 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
942 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
943 dump_stack();
944 spin_unlock(&bank->lock);
945 return;
946 }
947 #ifdef CONFIG_ARCH_OMAP16XX
948 if (bank->method == METHOD_GPIO_1610) {
949 /* Disable wake-up during idle for dynamic tick */
950 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
951 __raw_writel(1 << get_gpio_index(gpio), reg);
952 }
953 #endif
954 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
955 if (bank->method == METHOD_GPIO_24XX) {
956 /* Disable wake-up during idle for dynamic tick */
957 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
958 __raw_writel(1 << get_gpio_index(gpio), reg);
959 }
960 #endif
961 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
962 _reset_gpio(bank, gpio);
963 spin_unlock(&bank->lock);
964 }
965
966 /*
967 * We need to unmask the GPIO bank interrupt as soon as possible to
968 * avoid missing GPIO interrupts for other lines in the bank.
969 * Then we need to mask-read-clear-unmask the triggered GPIO lines
970 * in the bank to avoid missing nested interrupts for a GPIO line.
971 * If we wait to unmask individual GPIO lines in the bank after the
972 * line's interrupt handler has been run, we may miss some nested
973 * interrupts.
974 */
975 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
976 {
977 void __iomem *isr_reg = NULL;
978 u32 isr;
979 unsigned int gpio_irq;
980 struct gpio_bank *bank;
981 u32 retrigger = 0;
982 int unmasked = 0;
983
984 desc->chip->ack(irq);
985
986 bank = get_irq_data(irq);
987 #ifdef CONFIG_ARCH_OMAP1
988 if (bank->method == METHOD_MPUIO)
989 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
990 #endif
991 #ifdef CONFIG_ARCH_OMAP15XX
992 if (bank->method == METHOD_GPIO_1510)
993 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
994 #endif
995 #if defined(CONFIG_ARCH_OMAP16XX)
996 if (bank->method == METHOD_GPIO_1610)
997 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
998 #endif
999 #ifdef CONFIG_ARCH_OMAP730
1000 if (bank->method == METHOD_GPIO_730)
1001 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1002 #endif
1003 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1004 if (bank->method == METHOD_GPIO_24XX)
1005 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1006 #endif
1007 while(1) {
1008 u32 isr_saved, level_mask = 0;
1009 u32 enabled;
1010
1011 enabled = _get_gpio_irqbank_mask(bank);
1012 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1013
1014 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1015 isr &= 0x0000ffff;
1016
1017 if (cpu_class_is_omap2()) {
1018 level_mask =
1019 __raw_readl(bank->base +
1020 OMAP24XX_GPIO_LEVELDETECT0) |
1021 __raw_readl(bank->base +
1022 OMAP24XX_GPIO_LEVELDETECT1);
1023 level_mask &= enabled;
1024 }
1025
1026 /* clear edge sensitive interrupts before handler(s) are
1027 called so that we don't miss any interrupt occurred while
1028 executing them */
1029 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1030 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1031 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1032
1033 /* if there is only edge sensitive GPIO pin interrupts
1034 configured, we could unmask GPIO bank interrupt immediately */
1035 if (!level_mask && !unmasked) {
1036 unmasked = 1;
1037 desc->chip->unmask(irq);
1038 }
1039
1040 isr |= retrigger;
1041 retrigger = 0;
1042 if (!isr)
1043 break;
1044
1045 gpio_irq = bank->virtual_irq_start;
1046 for (; isr != 0; isr >>= 1, gpio_irq++) {
1047 struct irq_desc *d;
1048 int irq_mask;
1049 if (!(isr & 1))
1050 continue;
1051 d = irq_desc + gpio_irq;
1052 /* Don't run the handler if it's already running
1053 * or was disabled lazely.
1054 */
1055 if (unlikely((d->depth ||
1056 (d->status & IRQ_INPROGRESS)))) {
1057 irq_mask = 1 <<
1058 (gpio_irq - bank->virtual_irq_start);
1059 /* The unmasking will be done by
1060 * enable_irq in case it is disabled or
1061 * after returning from the handler if
1062 * it's already running.
1063 */
1064 _enable_gpio_irqbank(bank, irq_mask, 0);
1065 if (!d->depth) {
1066 /* Level triggered interrupts
1067 * won't ever be reentered
1068 */
1069 BUG_ON(level_mask & irq_mask);
1070 d->status |= IRQ_PENDING;
1071 }
1072 continue;
1073 }
1074
1075 desc_handle_irq(gpio_irq, d);
1076
1077 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1078 irq_mask = 1 <<
1079 (gpio_irq - bank->virtual_irq_start);
1080 d->status &= ~IRQ_PENDING;
1081 _enable_gpio_irqbank(bank, irq_mask, 1);
1082 retrigger |= irq_mask;
1083 }
1084 }
1085
1086 if (cpu_class_is_omap2()) {
1087 /* clear level sensitive interrupts after handler(s) */
1088 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1089 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1090 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1091 }
1092
1093 }
1094 /* if bank has any level sensitive GPIO pin interrupt
1095 configured, we must unmask the bank interrupt only after
1096 handler(s) are executed in order to avoid spurious bank
1097 interrupt */
1098 if (!unmasked)
1099 desc->chip->unmask(irq);
1100
1101 }
1102
1103 static void gpio_irq_shutdown(unsigned int irq)
1104 {
1105 unsigned int gpio = irq - IH_GPIO_BASE;
1106 struct gpio_bank *bank = get_irq_chip_data(irq);
1107
1108 _reset_gpio(bank, gpio);
1109 }
1110
1111 static void gpio_ack_irq(unsigned int irq)
1112 {
1113 unsigned int gpio = irq - IH_GPIO_BASE;
1114 struct gpio_bank *bank = get_irq_chip_data(irq);
1115
1116 _clear_gpio_irqstatus(bank, gpio);
1117 }
1118
1119 static void gpio_mask_irq(unsigned int irq)
1120 {
1121 unsigned int gpio = irq - IH_GPIO_BASE;
1122 struct gpio_bank *bank = get_irq_chip_data(irq);
1123
1124 _set_gpio_irqenable(bank, gpio, 0);
1125 }
1126
1127 static void gpio_unmask_irq(unsigned int irq)
1128 {
1129 unsigned int gpio = irq - IH_GPIO_BASE;
1130 unsigned int gpio_idx = get_gpio_index(gpio);
1131 struct gpio_bank *bank = get_irq_chip_data(irq);
1132
1133 _set_gpio_irqenable(bank, gpio_idx, 1);
1134 }
1135
1136 static struct irq_chip gpio_irq_chip = {
1137 .name = "GPIO",
1138 .shutdown = gpio_irq_shutdown,
1139 .ack = gpio_ack_irq,
1140 .mask = gpio_mask_irq,
1141 .unmask = gpio_unmask_irq,
1142 .set_type = gpio_irq_type,
1143 .set_wake = gpio_wake_enable,
1144 };
1145
1146 /*---------------------------------------------------------------------*/
1147
1148 #ifdef CONFIG_ARCH_OMAP1
1149
1150 /* MPUIO uses the always-on 32k clock */
1151
1152 static void mpuio_ack_irq(unsigned int irq)
1153 {
1154 /* The ISR is reset automatically, so do nothing here. */
1155 }
1156
1157 static void mpuio_mask_irq(unsigned int irq)
1158 {
1159 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1160 struct gpio_bank *bank = get_irq_chip_data(irq);
1161
1162 _set_gpio_irqenable(bank, gpio, 0);
1163 }
1164
1165 static void mpuio_unmask_irq(unsigned int irq)
1166 {
1167 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1168 struct gpio_bank *bank = get_irq_chip_data(irq);
1169
1170 _set_gpio_irqenable(bank, gpio, 1);
1171 }
1172
1173 static struct irq_chip mpuio_irq_chip = {
1174 .name = "MPUIO",
1175 .ack = mpuio_ack_irq,
1176 .mask = mpuio_mask_irq,
1177 .unmask = mpuio_unmask_irq,
1178 .set_type = gpio_irq_type,
1179 #ifdef CONFIG_ARCH_OMAP16XX
1180 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1181 .set_wake = gpio_wake_enable,
1182 #endif
1183 };
1184
1185
1186 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1187
1188
1189 #ifdef CONFIG_ARCH_OMAP16XX
1190
1191 #include <linux/platform_device.h>
1192
1193 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1194 {
1195 struct gpio_bank *bank = platform_get_drvdata(pdev);
1196 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1197
1198 spin_lock(&bank->lock);
1199 bank->saved_wakeup = __raw_readl(mask_reg);
1200 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1201 spin_unlock(&bank->lock);
1202
1203 return 0;
1204 }
1205
1206 static int omap_mpuio_resume_early(struct platform_device *pdev)
1207 {
1208 struct gpio_bank *bank = platform_get_drvdata(pdev);
1209 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1210
1211 spin_lock(&bank->lock);
1212 __raw_writel(bank->saved_wakeup, mask_reg);
1213 spin_unlock(&bank->lock);
1214
1215 return 0;
1216 }
1217
1218 /* use platform_driver for this, now that there's no longer any
1219 * point to sys_device (other than not disturbing old code).
1220 */
1221 static struct platform_driver omap_mpuio_driver = {
1222 .suspend_late = omap_mpuio_suspend_late,
1223 .resume_early = omap_mpuio_resume_early,
1224 .driver = {
1225 .name = "mpuio",
1226 },
1227 };
1228
1229 static struct platform_device omap_mpuio_device = {
1230 .name = "mpuio",
1231 .id = -1,
1232 .dev = {
1233 .driver = &omap_mpuio_driver.driver,
1234 }
1235 /* could list the /proc/iomem resources */
1236 };
1237
1238 static inline void mpuio_init(void)
1239 {
1240 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1241
1242 if (platform_driver_register(&omap_mpuio_driver) == 0)
1243 (void) platform_device_register(&omap_mpuio_device);
1244 }
1245
1246 #else
1247 static inline void mpuio_init(void) {}
1248 #endif /* 16xx */
1249
1250 #else
1251
1252 extern struct irq_chip mpuio_irq_chip;
1253
1254 #define bank_is_mpuio(bank) 0
1255 static inline void mpuio_init(void) {}
1256
1257 #endif
1258
1259 /*---------------------------------------------------------------------*/
1260
1261 static int initialized;
1262 #if !defined(CONFIG_ARCH_OMAP3)
1263 static struct clk * gpio_ick;
1264 #endif
1265
1266 #if defined(CONFIG_ARCH_OMAP2)
1267 static struct clk * gpio_fck;
1268 #endif
1269
1270 #if defined(CONFIG_ARCH_OMAP2430)
1271 static struct clk * gpio5_ick;
1272 static struct clk * gpio5_fck;
1273 #endif
1274
1275 #if defined(CONFIG_ARCH_OMAP3)
1276 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1277 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278 #endif
1279
1280 static int __init _omap_gpio_init(void)
1281 {
1282 int i;
1283 struct gpio_bank *bank;
1284 #if defined(CONFIG_ARCH_OMAP3)
1285 char clk_name[11];
1286 #endif
1287
1288 initialized = 1;
1289
1290 #if defined(CONFIG_ARCH_OMAP1)
1291 if (cpu_is_omap15xx()) {
1292 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1293 if (IS_ERR(gpio_ick))
1294 printk("Could not get arm_gpio_ck\n");
1295 else
1296 clk_enable(gpio_ick);
1297 }
1298 #endif
1299 #if defined(CONFIG_ARCH_OMAP2)
1300 if (cpu_class_is_omap2()) {
1301 gpio_ick = clk_get(NULL, "gpios_ick");
1302 if (IS_ERR(gpio_ick))
1303 printk("Could not get gpios_ick\n");
1304 else
1305 clk_enable(gpio_ick);
1306 gpio_fck = clk_get(NULL, "gpios_fck");
1307 if (IS_ERR(gpio_fck))
1308 printk("Could not get gpios_fck\n");
1309 else
1310 clk_enable(gpio_fck);
1311
1312 /*
1313 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1314 */
1315 #if defined(CONFIG_ARCH_OMAP2430)
1316 if (cpu_is_omap2430()) {
1317 gpio5_ick = clk_get(NULL, "gpio5_ick");
1318 if (IS_ERR(gpio5_ick))
1319 printk("Could not get gpio5_ick\n");
1320 else
1321 clk_enable(gpio5_ick);
1322 gpio5_fck = clk_get(NULL, "gpio5_fck");
1323 if (IS_ERR(gpio5_fck))
1324 printk("Could not get gpio5_fck\n");
1325 else
1326 clk_enable(gpio5_fck);
1327 }
1328 #endif
1329 }
1330 #endif
1331
1332 #if defined(CONFIG_ARCH_OMAP3)
1333 if (cpu_is_omap34xx()) {
1334 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1335 sprintf(clk_name, "gpio%d_ick", i + 1);
1336 gpio_iclks[i] = clk_get(NULL, clk_name);
1337 if (IS_ERR(gpio_iclks[i]))
1338 printk(KERN_ERR "Could not get %s\n", clk_name);
1339 else
1340 clk_enable(gpio_iclks[i]);
1341 sprintf(clk_name, "gpio%d_fck", i + 1);
1342 gpio_fclks[i] = clk_get(NULL, clk_name);
1343 if (IS_ERR(gpio_fclks[i]))
1344 printk(KERN_ERR "Could not get %s\n", clk_name);
1345 else
1346 clk_enable(gpio_fclks[i]);
1347 }
1348 }
1349 #endif
1350
1351
1352 #ifdef CONFIG_ARCH_OMAP15XX
1353 if (cpu_is_omap15xx()) {
1354 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1355 gpio_bank_count = 2;
1356 gpio_bank = gpio_bank_1510;
1357 }
1358 #endif
1359 #if defined(CONFIG_ARCH_OMAP16XX)
1360 if (cpu_is_omap16xx()) {
1361 u32 rev;
1362
1363 gpio_bank_count = 5;
1364 gpio_bank = gpio_bank_1610;
1365 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1366 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1367 (rev >> 4) & 0x0f, rev & 0x0f);
1368 }
1369 #endif
1370 #ifdef CONFIG_ARCH_OMAP730
1371 if (cpu_is_omap730()) {
1372 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1373 gpio_bank_count = 7;
1374 gpio_bank = gpio_bank_730;
1375 }
1376 #endif
1377
1378 #ifdef CONFIG_ARCH_OMAP24XX
1379 if (cpu_is_omap242x()) {
1380 int rev;
1381
1382 gpio_bank_count = 4;
1383 gpio_bank = gpio_bank_242x;
1384 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1385 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1386 (rev >> 4) & 0x0f, rev & 0x0f);
1387 }
1388 if (cpu_is_omap243x()) {
1389 int rev;
1390
1391 gpio_bank_count = 5;
1392 gpio_bank = gpio_bank_243x;
1393 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1394 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1395 (rev >> 4) & 0x0f, rev & 0x0f);
1396 }
1397 #endif
1398 #ifdef CONFIG_ARCH_OMAP34XX
1399 if (cpu_is_omap34xx()) {
1400 int rev;
1401
1402 gpio_bank_count = OMAP34XX_NR_GPIOS;
1403 gpio_bank = gpio_bank_34xx;
1404 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1405 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1406 (rev >> 4) & 0x0f, rev & 0x0f);
1407 }
1408 #endif
1409 for (i = 0; i < gpio_bank_count; i++) {
1410 int j, gpio_count = 16;
1411
1412 bank = &gpio_bank[i];
1413 bank->reserved_map = 0;
1414 bank->base = IO_ADDRESS(bank->base);
1415 spin_lock_init(&bank->lock);
1416 if (bank_is_mpuio(bank))
1417 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1418 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1419 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1420 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1421 }
1422 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1423 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1424 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1425 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1426 }
1427 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1428 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1429 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1430
1431 gpio_count = 32; /* 730 has 32-bit GPIOs */
1432 }
1433
1434 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1435 if (bank->method == METHOD_GPIO_24XX) {
1436 static const u32 non_wakeup_gpios[] = {
1437 0xe203ffc0, 0x08700040
1438 };
1439
1440 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1441 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1442 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1443
1444 /* Initialize interface clock ungated, module enabled */
1445 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1446 if (i < ARRAY_SIZE(non_wakeup_gpios))
1447 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1448 gpio_count = 32;
1449 }
1450 #endif
1451 for (j = bank->virtual_irq_start;
1452 j < bank->virtual_irq_start + gpio_count; j++) {
1453 set_irq_chip_data(j, bank);
1454 if (bank_is_mpuio(bank))
1455 set_irq_chip(j, &mpuio_irq_chip);
1456 else
1457 set_irq_chip(j, &gpio_irq_chip);
1458 set_irq_handler(j, handle_simple_irq);
1459 set_irq_flags(j, IRQF_VALID);
1460 }
1461 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1462 set_irq_data(bank->irq, bank);
1463 }
1464
1465 /* Enable system clock for GPIO module.
1466 * The CAM_CLK_CTRL *is* really the right place. */
1467 if (cpu_is_omap16xx())
1468 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1469
1470 /* Enable autoidle for the OCP interface */
1471 if (cpu_is_omap24xx())
1472 omap_writel(1 << 0, 0x48019010);
1473 if (cpu_is_omap34xx())
1474 omap_writel(1 << 0, 0x48306814);
1475
1476 return 0;
1477 }
1478
1479 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1480 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1481 {
1482 int i;
1483
1484 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1485 return 0;
1486
1487 for (i = 0; i < gpio_bank_count; i++) {
1488 struct gpio_bank *bank = &gpio_bank[i];
1489 void __iomem *wake_status;
1490 void __iomem *wake_clear;
1491 void __iomem *wake_set;
1492
1493 switch (bank->method) {
1494 #ifdef CONFIG_ARCH_OMAP16XX
1495 case METHOD_GPIO_1610:
1496 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1497 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1498 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1499 break;
1500 #endif
1501 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1502 case METHOD_GPIO_24XX:
1503 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1504 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1505 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1506 break;
1507 #endif
1508 default:
1509 continue;
1510 }
1511
1512 spin_lock(&bank->lock);
1513 bank->saved_wakeup = __raw_readl(wake_status);
1514 __raw_writel(0xffffffff, wake_clear);
1515 __raw_writel(bank->suspend_wakeup, wake_set);
1516 spin_unlock(&bank->lock);
1517 }
1518
1519 return 0;
1520 }
1521
1522 static int omap_gpio_resume(struct sys_device *dev)
1523 {
1524 int i;
1525
1526 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1527 return 0;
1528
1529 for (i = 0; i < gpio_bank_count; i++) {
1530 struct gpio_bank *bank = &gpio_bank[i];
1531 void __iomem *wake_clear;
1532 void __iomem *wake_set;
1533
1534 switch (bank->method) {
1535 #ifdef CONFIG_ARCH_OMAP16XX
1536 case METHOD_GPIO_1610:
1537 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1538 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1539 break;
1540 #endif
1541 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1542 case METHOD_GPIO_24XX:
1543 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1544 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1545 break;
1546 #endif
1547 default:
1548 continue;
1549 }
1550
1551 spin_lock(&bank->lock);
1552 __raw_writel(0xffffffff, wake_clear);
1553 __raw_writel(bank->saved_wakeup, wake_set);
1554 spin_unlock(&bank->lock);
1555 }
1556
1557 return 0;
1558 }
1559
1560 static struct sysdev_class omap_gpio_sysclass = {
1561 .name = "gpio",
1562 .suspend = omap_gpio_suspend,
1563 .resume = omap_gpio_resume,
1564 };
1565
1566 static struct sys_device omap_gpio_device = {
1567 .id = 0,
1568 .cls = &omap_gpio_sysclass,
1569 };
1570
1571 #endif
1572
1573 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1574
1575 static int workaround_enabled;
1576
1577 void omap2_gpio_prepare_for_retention(void)
1578 {
1579 int i, c = 0;
1580
1581 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1582 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1583 for (i = 0; i < gpio_bank_count; i++) {
1584 struct gpio_bank *bank = &gpio_bank[i];
1585 u32 l1, l2;
1586
1587 if (!(bank->enabled_non_wakeup_gpios))
1588 continue;
1589 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1590 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1591 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1592 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1593 #endif
1594 bank->saved_fallingdetect = l1;
1595 bank->saved_risingdetect = l2;
1596 l1 &= ~bank->enabled_non_wakeup_gpios;
1597 l2 &= ~bank->enabled_non_wakeup_gpios;
1598 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1599 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1600 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1601 #endif
1602 c++;
1603 }
1604 if (!c) {
1605 workaround_enabled = 0;
1606 return;
1607 }
1608 workaround_enabled = 1;
1609 }
1610
1611 void omap2_gpio_resume_after_retention(void)
1612 {
1613 int i;
1614
1615 if (!workaround_enabled)
1616 return;
1617 for (i = 0; i < gpio_bank_count; i++) {
1618 struct gpio_bank *bank = &gpio_bank[i];
1619 u32 l;
1620
1621 if (!(bank->enabled_non_wakeup_gpios))
1622 continue;
1623 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1624 __raw_writel(bank->saved_fallingdetect,
1625 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1626 __raw_writel(bank->saved_risingdetect,
1627 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1628 #endif
1629 /* Check if any of the non-wakeup interrupt GPIOs have changed
1630 * state. If so, generate an IRQ by software. This is
1631 * horribly racy, but it's the best we can do to work around
1632 * this silicon bug. */
1633 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1634 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1635 #endif
1636 l ^= bank->saved_datain;
1637 l &= bank->non_wakeup_gpios;
1638 if (l) {
1639 u32 old0, old1;
1640 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1641 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1642 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1643 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1644 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1645 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1646 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1647 #endif
1648 }
1649 }
1650
1651 }
1652
1653 #endif
1654
1655 /*
1656 * This may get called early from board specific init
1657 * for boards that have interrupts routed via FPGA.
1658 */
1659 int __init omap_gpio_init(void)
1660 {
1661 if (!initialized)
1662 return _omap_gpio_init();
1663 else
1664 return 0;
1665 }
1666
1667 static int __init omap_gpio_sysinit(void)
1668 {
1669 int ret = 0;
1670
1671 if (!initialized)
1672 ret = _omap_gpio_init();
1673
1674 mpuio_init();
1675
1676 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1677 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1678 if (ret == 0) {
1679 ret = sysdev_class_register(&omap_gpio_sysclass);
1680 if (ret == 0)
1681 ret = sysdev_register(&omap_gpio_device);
1682 }
1683 }
1684 #endif
1685
1686 return ret;
1687 }
1688
1689 EXPORT_SYMBOL(omap_request_gpio);
1690 EXPORT_SYMBOL(omap_free_gpio);
1691 EXPORT_SYMBOL(omap_set_gpio_direction);
1692 EXPORT_SYMBOL(omap_set_gpio_dataout);
1693 EXPORT_SYMBOL(omap_get_gpio_datain);
1694
1695 arch_initcall(omap_gpio_sysinit);
1696
1697
1698 #ifdef CONFIG_DEBUG_FS
1699
1700 #include <linux/debugfs.h>
1701 #include <linux/seq_file.h>
1702
1703 static int gpio_is_input(struct gpio_bank *bank, int mask)
1704 {
1705 void __iomem *reg = bank->base;
1706
1707 switch (bank->method) {
1708 case METHOD_MPUIO:
1709 reg += OMAP_MPUIO_IO_CNTL;
1710 break;
1711 case METHOD_GPIO_1510:
1712 reg += OMAP1510_GPIO_DIR_CONTROL;
1713 break;
1714 case METHOD_GPIO_1610:
1715 reg += OMAP1610_GPIO_DIRECTION;
1716 break;
1717 case METHOD_GPIO_730:
1718 reg += OMAP730_GPIO_DIR_CONTROL;
1719 break;
1720 case METHOD_GPIO_24XX:
1721 reg += OMAP24XX_GPIO_OE;
1722 break;
1723 }
1724 return __raw_readl(reg) & mask;
1725 }
1726
1727
1728 static int dbg_gpio_show(struct seq_file *s, void *unused)
1729 {
1730 unsigned i, j, gpio;
1731
1732 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1733 struct gpio_bank *bank = gpio_bank + i;
1734 unsigned bankwidth = 16;
1735 u32 mask = 1;
1736
1737 if (bank_is_mpuio(bank))
1738 gpio = OMAP_MPUIO(0);
1739 else if (cpu_class_is_omap2() || cpu_is_omap730())
1740 bankwidth = 32;
1741
1742 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1743 unsigned irq, value, is_in, irqstat;
1744
1745 if (!(bank->reserved_map & mask))
1746 continue;
1747
1748 irq = bank->virtual_irq_start + j;
1749 value = omap_get_gpio_datain(gpio);
1750 is_in = gpio_is_input(bank, mask);
1751
1752 if (bank_is_mpuio(bank))
1753 seq_printf(s, "MPUIO %2d: ", j);
1754 else
1755 seq_printf(s, "GPIO %3d: ", gpio);
1756 seq_printf(s, "%s %s",
1757 is_in ? "in " : "out",
1758 value ? "hi" : "lo");
1759
1760 irqstat = irq_desc[irq].status;
1761 if (is_in && ((bank->suspend_wakeup & mask)
1762 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1763 char *trigger = NULL;
1764
1765 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1766 case IRQ_TYPE_EDGE_FALLING:
1767 trigger = "falling";
1768 break;
1769 case IRQ_TYPE_EDGE_RISING:
1770 trigger = "rising";
1771 break;
1772 case IRQ_TYPE_EDGE_BOTH:
1773 trigger = "bothedge";
1774 break;
1775 case IRQ_TYPE_LEVEL_LOW:
1776 trigger = "low";
1777 break;
1778 case IRQ_TYPE_LEVEL_HIGH:
1779 trigger = "high";
1780 break;
1781 case IRQ_TYPE_NONE:
1782 trigger = "(unspecified)";
1783 break;
1784 }
1785 seq_printf(s, ", irq-%d %s%s",
1786 irq, trigger,
1787 (bank->suspend_wakeup & mask)
1788 ? " wakeup" : "");
1789 }
1790 seq_printf(s, "\n");
1791 }
1792
1793 if (bank_is_mpuio(bank)) {
1794 seq_printf(s, "\n");
1795 gpio = 0;
1796 }
1797 }
1798 return 0;
1799 }
1800
1801 static int dbg_gpio_open(struct inode *inode, struct file *file)
1802 {
1803 return single_open(file, dbg_gpio_show, &inode->i_private);
1804 }
1805
1806 static const struct file_operations debug_fops = {
1807 .open = dbg_gpio_open,
1808 .read = seq_read,
1809 .llseek = seq_lseek,
1810 .release = single_release,
1811 };
1812
1813 static int __init omap_gpio_debuginit(void)
1814 {
1815 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1816 NULL, NULL, &debug_fops);
1817 return 0;
1818 }
1819 late_initcall(omap_gpio_debuginit);
1820 #endif
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