arch/blackfin/kernel/cplb-mpu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplb.h>
  27 #include <asm/cplbinit.h>
  28
  29 #if ANOMALY_05000263
  30 # error the MPU will not function safely while Anomaly 05000263 applies
  31 #endif
  32
  33 struct cplb_entry icplb_tbl[MAX_CPLBS];
  34 struct cplb_entry dcplb_tbl[MAX_CPLBS];
  35
  36 int first_switched_icplb, first_switched_dcplb;
  37 int first_mask_dcplb;
  38
  39 void __init generate_cpl_tables(void)
  40 {
  41         int i_d, i_i;
  42         unsigned long addr;
  43         unsigned long d_data, i_data;
  44         unsigned long d_cache = 0, i_cache = 0;
  45
  46 #ifdef CONFIG_BFIN_ICACHE
  47         i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
  48 #endif
  49
  50 #ifdef CONFIG_BFIN_DCACHE
  51         d_cache = CPLB_L1_CHBL;
  52 #ifdef CONFIG_BLKFIN_WT
  53         d_cache |= CPLB_L1_AOW | CPLB_WT;
  54 #endif
  55 #endif
  56         i_d = i_i = 0;
  57
  58         /* Set up the zero page.  */
  59         dcplb_tbl[i_d].addr = 0;
  60         dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
  61
  62 #if 0
  63         icplb_tbl[i_i].addr = 0;
  64         icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
  65 #endif
  66
  67         /* Cover kernel memory with 4M pages.  */
  68         addr = 0;
  69         d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
  70         i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
  71
  72         for (; addr < memory_start; addr += 4 * 1024 * 1024) {
  73                 dcplb_tbl[i_d].addr = addr;
  74                 dcplb_tbl[i_d++].data = d_data;
  75                 icplb_tbl[i_i].addr = addr;
  76                 icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
  77         }
  78
  79         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
  80 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
  81         dcplb_tbl[i_d].addr = L1_DATA_A_START;
  82         dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
  83 #endif
  84         icplb_tbl[i_i].addr = L1_CODE_START;
  85         icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
  86
  87         first_mask_dcplb = i_d;
  88         first_switched_dcplb = i_d + (1 << page_mask_order);
  89         first_switched_icplb = i_i;
  90
  91         while (i_d < MAX_CPLBS)
  92                 dcplb_tbl[i_d++].data = 0;
  93         while (i_i < MAX_CPLBS)
  94                 icplb_tbl[i_i++].data = 0;
  95 }