arch/mips/kernel/i8253.c

   1 /*
   2  * i8253.c  8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/spinlock.h>
  11
  12 #include <asm/delay.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15 #include <asm/time.h>
  16
  17 DEFINE_SPINLOCK(i8253_lock);
  18
  19 /*
  20  * Initialize the PIT timer.
  21  *
  22  * This is also called after resume to bring the PIT into operation again.
  23  */
  24 static void init_pit_timer(enum clock_event_mode mode,
  25                            struct clock_event_device *evt)
  26 {
  27         spin_lock(&i8253_lock);
  28
  29         switch(mode) {
  30         case CLOCK_EVT_MODE_PERIODIC:
  31                 /* binary, mode 2, LSB/MSB, ch 0 */
  32                 outb_p(0x34, PIT_MODE);
  33                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
  34                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
  35                 break;
  36
  37         case CLOCK_EVT_MODE_SHUTDOWN:
  38         case CLOCK_EVT_MODE_UNUSED:
  39                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  40                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  41                         outb_p(0x30, PIT_MODE);
  42                         outb_p(0, PIT_CH0);
  43                         outb_p(0, PIT_CH0);
  44                 }
  45                 break;
  46
  47         case CLOCK_EVT_MODE_ONESHOT:
  48                 /* One shot setup */
  49                 outb_p(0x38, PIT_MODE);
  50                 break;
  51
  52         case CLOCK_EVT_MODE_RESUME:
  53                 /* Nothing to do here */
  54                 break;
  55         }
  56         spin_unlock(&i8253_lock);
  57 }
  58
  59 /*
  60  * Program the next event in oneshot mode
  61  *
  62  * Delta is given in PIT ticks
  63  */
  64 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  65 {
  66         spin_lock(&i8253_lock);
  67         outb_p(delta & 0xff , PIT_CH0); /* LSB */
  68         outb(delta >> 8 , PIT_CH0);     /* MSB */
  69         spin_unlock(&i8253_lock);
  70
  71         return 0;
  72 }
  73
  74 /*
  75  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  76  * it can be solely used for the global tick.
  77  *
  78  * The profiling and update capabilites are switched off once the local apic is
  79  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  80  * !using_apic_timer decisions in do_timer_interrupt_hook()
  81  */
  82 struct clock_event_device pit_clockevent = {
  83         .name           = "pit",
  84         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  85         .set_mode       = init_pit_timer,
  86         .set_next_event = pit_next_event,
  87         .irq            = 0,
  88 };
  89
  90 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  91 {
  92         pit_clockevent.event_handler(&pit_clockevent);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 static struct irqaction irq0  = {
  98         .handler = timer_interrupt,
  99         .flags = IRQF_DISABLED | IRQF_NOBALANCING,
 100         .mask = CPU_MASK_NONE,
 101         .name = "timer"
 102 };
 103
 104 /*
 105  * Initialize the conversion factor and the min/max deltas of the clock event
 106  * structure and register the clock event source with the framework.
 107  */
 108 void __init setup_pit_timer(void)
 109 {
 110         struct clock_event_device *cd = &pit_clockevent;
 111         unsigned int cpu = smp_processor_id();
 112
 113         /*
 114          * Start pit with the boot cpu mask and make it global after the
 115          * IO_APIC has been initialized.
 116          */
 117         cd->cpumask = cpumask_of_cpu(cpu);
 118         clockevent_set_clock(cd, CLOCK_TICK_RATE);
 119         cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
 120         cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
 121         clockevents_register_device(cd);
 122
 123         irq0.mask = cpumask_of_cpu(cpu);
 124         setup_irq(0, &irq0);
 125 }
 126
 127 /*
 128  * Since the PIT overflows every tick, its not very useful
 129  * to just read by itself. So use jiffies to emulate a free
 130  * running counter:
 131  */
 132 static cycle_t pit_read(void)
 133 {
 134         unsigned long flags;
 135         int count;
 136         u32 jifs;
 137         static int old_count;
 138         static u32 old_jifs;
 139
 140         spin_lock_irqsave(&i8253_lock, flags);
 141         /*
 142          * Although our caller may have the read side of xtime_lock,
 143          * this is now a seqlock, and we are cheating in this routine
 144          * by having side effects on state that we cannot undo if
 145          * there is a collision on the seqlock and our caller has to
 146          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 147          * jiffies as volatile despite the lock.  We read jiffies
 148          * before latching the timer count to guarantee that although
 149          * the jiffies value might be older than the count (that is,
 150          * the counter may underflow between the last point where
 151          * jiffies was incremented and the point where we latch the
 152          * count), it cannot be newer.
 153          */
 154         jifs = jiffies;
 155         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
 156         count = inb_p(PIT_CH0); /* read the latched count */
 157         count |= inb_p(PIT_CH0) << 8;
 158
 159         /* VIA686a test code... reset the latch if count > max + 1 */
 160         if (count > LATCH) {
 161                 outb_p(0x34, PIT_MODE);
 162                 outb_p(LATCH & 0xff, PIT_CH0);
 163                 outb(LATCH >> 8, PIT_CH0);
 164                 count = LATCH - 1;
 165         }
 166
 167         /*
 168          * It's possible for count to appear to go the wrong way for a
 169          * couple of reasons:
 170          *
 171          *  1. The timer counter underflows, but we haven't handled the
 172          *     resulting interrupt and incremented jiffies yet.
 173          *  2. Hardware problem with the timer, not giving us continuous time,
 174          *     the counter does small "jumps" upwards on some Pentium systems,
 175          *     (see c't 95/10 page 335 for Neptun bug.)
 176          *
 177          * Previous attempts to handle these cases intelligently were
 178          * buggy, so we just do the simple thing now.
 179          */
 180         if (count > old_count && jifs == old_jifs) {
 181                 count = old_count;
 182         }
 183         old_count = count;
 184         old_jifs = jifs;
 185
 186         spin_unlock_irqrestore(&i8253_lock, flags);
 187
 188         count = (LATCH - 1) - count;
 189
 190         return (cycle_t)(jifs * LATCH) + count;
 191 }
 192
 193 static struct clocksource clocksource_pit = {
 194         .name   = "pit",
 195         .rating = 110,
 196         .read   = pit_read,
 197         .mask   = CLOCKSOURCE_MASK(32),
 198         .mult   = 0,
 199         .shift  = 20,
 200 };
 201
 202 static int __init init_pit_clocksource(void)
 203 {
 204         if (num_possible_cpus() > 1) /* PIT does not scale! */
 205                 return 0;
 206
 207         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
 208         return clocksource_register(&clocksource_pit);
 209 }
 210 arch_initcall(init_pit_clocksource);