arch/ppc/mm/44x_mmu.c

   1 /*
   2  * Modifications by Matt Porter (mporter@mvista.com) to support
   3  * PPC44x Book E processors.
   4  *
   5  * This file contains the routines for initializing the MMU
   6  * on the 4xx series of chips.
   7  *  -- paulus
   8  *
   9  *  Derived from arch/ppc/mm/init.c:
  10  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  11  *
  12  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  13  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  14  *    Copyright (C) 1996 Paul Mackerras
  15  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  16  *
  17  *  Derived from "arch/i386/mm/init.c"
  18  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  19  *
  20  *  This program is free software; you can redistribute it and/or
  21  *  modify it under the terms of the GNU General Public License
  22  *  as published by the Free Software Foundation; either version
  23  *  2 of the License, or (at your option) any later version.
  24  *
  25  */
  26
  27 #include <linux/signal.h>
  28 #include <linux/sched.h>
  29 #include <linux/kernel.h>
  30 #include <linux/errno.h>
  31 #include <linux/string.h>
  32 #include <linux/types.h>
  33 #include <linux/ptrace.h>
  34 #include <linux/mman.h>
  35 #include <linux/mm.h>
  36 #include <linux/swap.h>
  37 #include <linux/stddef.h>
  38 #include <linux/vmalloc.h>
  39 #include <linux/init.h>
  40 #include <linux/delay.h>
  41 #include <linux/highmem.h>
  42
  43 #include <asm/pgalloc.h>
  44 #include <asm/prom.h>
  45 #include <asm/io.h>
  46 #include <asm/mmu_context.h>
  47 #include <asm/pgtable.h>
  48 #include <asm/mmu.h>
  49 #include <asm/uaccess.h>
  50 #include <asm/smp.h>
  51 #include <asm/bootx.h>
  52 #include <asm/machdep.h>
  53 #include <asm/setup.h>
  54
  55 #include "mmu_decl.h"
  56
  57 extern char etext[], _stext[];
  58
  59 /* Used by the 44x TLB replacement exception handler.
  60  * Just needed it declared someplace.
  61  */
  62 unsigned int tlb_44x_index = 0;
  63 unsigned int tlb_44x_hwater = PPC4XX_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
  64 int icache_44x_need_flush;
  65
  66 /*
  67  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
  68  */
  69 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
  70 {
  71         __asm__ __volatile__(
  72                 "tlbwe  %2,%3,%4\n"
  73                 "tlbwe  %1,%3,%5\n"
  74                 "tlbwe  %0,%3,%6\n"
  75         :
  76         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
  77           "r" (phys),
  78           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
  79           "r" (tlb_44x_hwater--), /* slot for this TLB entry */
  80           "i" (PPC44x_TLB_PAGEID),
  81           "i" (PPC44x_TLB_XLAT),
  82           "i" (PPC44x_TLB_ATTRIB));
  83 }
  84
  85 void __init MMU_init_hw(void)
  86 {
  87         flush_instruction_cache();
  88 }
  89
  90 unsigned long __init mmu_mapin_ram(void)
  91 {
  92         unsigned long addr;
  93
  94         /* Pin in enough TLBs to cover any lowmem not covered by the
  95          * initial 256M mapping established in head_44x.S */
  96         for (addr = PPC_PIN_SIZE; addr < total_lowmem;
  97              addr += PPC_PIN_SIZE)
  98                 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
  99
 100         return total_lowmem;
 101 }