arch/ppc/platforms/4xx/taishan.c

   1 /*
   2  * arch/ppc/platforms/4xx/taishan.c
   3  *
   4  * AMCC Taishan board specific routines
   5  *
   6  * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/types.h>
  22 #include <linux/major.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/ide.h>
  27 #include <linux/initrd.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/root_dev.h>
  30 #include <linux/tty.h>
  31 #include <linux/serial.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial_8250.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/mtd/nand.h>
  37 #include <linux/mtd/ndfc.h>
  38 #include <linux/mtd/physmap.h>
  39
  40 #include <asm/machdep.h>
  41 #include <asm/ocp.h>
  42 #include <asm/bootinfo.h>
  43 #include <asm/ppcboot.h>
  44
  45 #include <syslib/gen550.h>
  46 #include <syslib/ibm440gx_common.h>
  47
  48 extern bd_t __res;
  49
  50 static struct ibm44x_clocks clocks __initdata;
  51
  52 /*
  53  * NOR FLASH configuration (using mtd physmap driver)
  54  */
  55
  56 /* start will be added dynamically, end is always fixed */
  57 static struct resource taishan_nor_resource = {
  58         .start = TAISHAN_FLASH_ADDR,
  59         .end   = 0x1ffffffffULL,
  60         .flags = IORESOURCE_MEM,
  61 };
  62
  63 #define RW_PART0_OF     0
  64 #define RW_PART0_SZ     0x180000
  65 #define RW_PART1_SZ     0x200000
  66 /* Partition 2 will be autosized dynamically... */
  67 #define RW_PART3_SZ     0x80000
  68 #define RW_PART4_SZ     0x40000
  69
  70 static struct mtd_partition taishan_nor_parts[] = {
  71         {
  72                 .name = "kernel",
  73                 .offset = 0,
  74                 .size = RW_PART0_SZ
  75         },
  76         {
  77                 .name = "root",
  78                 .offset = MTDPART_OFS_APPEND,
  79                 .size = RW_PART1_SZ,
  80         },
  81         {
  82                 .name = "user",
  83                 .offset = MTDPART_OFS_APPEND,
  84 /*              .size = RW_PART2_SZ */ /* will be adjusted dynamically */
  85         },
  86         {
  87                 .name = "env",
  88                 .offset = MTDPART_OFS_APPEND,
  89                 .size = RW_PART3_SZ,
  90         },
  91         {
  92                 .name = "u-boot",
  93                 .offset = MTDPART_OFS_APPEND,
  94                 .size = RW_PART4_SZ,
  95         }
  96 };
  97
  98 static struct physmap_flash_data taishan_nor_data = {
  99         .width          = 4,
 100         .parts          = taishan_nor_parts,
 101         .nr_parts       = ARRAY_SIZE(taishan_nor_parts),
 102 };
 103
 104 static struct platform_device taishan_nor_device = {
 105         .name           = "physmap-flash",
 106         .id             = 0,
 107         .dev = {
 108                         .platform_data = &taishan_nor_data,
 109                 },
 110         .num_resources  = 1,
 111         .resource       = &taishan_nor_resource,
 112 };
 113
 114 static int taishan_setup_flash(void)
 115 {
 116         /*
 117          * Adjust partition 2 to flash size
 118          */
 119         taishan_nor_parts[2].size = __res.bi_flashsize -
 120                 RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
 121
 122         platform_device_register(&taishan_nor_device);
 123
 124         return 0;
 125 }
 126 arch_initcall(taishan_setup_flash);
 127
 128 static void __init
 129 taishan_calibrate_decr(void)
 130 {
 131         unsigned int freq;
 132
 133         if (mfspr(SPRN_CCR1) & CCR1_TCS)
 134                 freq = TAISHAN_TMR_CLK;
 135         else
 136                 freq = clocks.cpu;
 137
 138         ibm44x_calibrate_decr(freq);
 139 }
 140
 141 static int
 142 taishan_show_cpuinfo(struct seq_file *m)
 143 {
 144         seq_printf(m, "vendor\t\t: AMCC\n");
 145         seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
 146         ibm440gx_show_cpuinfo(m);
 147         return 0;
 148 }
 149
 150 static inline int
 151 taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 152 {
 153         static char pci_irq_table[][4] =
 154         /*
 155          *      PCI IDSEL/INTPIN->INTLINE
 156          *         A   B   C   D
 157          */
 158         {
 159                 { 23, 24, 25, 26 },     /* IDSEL 1 - PCI Slot 0 */
 160                 { 24, 25, 26, 23 },     /* IDSEL 2 - PCI Slot 1 */
 161         };
 162
 163         const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
 164         return PCI_IRQ_TABLE_LOOKUP;
 165 }
 166
 167 static void __init taishan_set_emacdata(void)
 168 {
 169         struct ocp_def *def;
 170         struct ocp_func_emac_data *emacdata;
 171         int i;
 172
 173         /* Set phy_map, phy_mode, and mac_addr for each EMAC */
 174         for (i=2; i<4; i++) {
 175                 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 176                 emacdata = def->additions;
 177                 if (i < 2) {
 178                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 179                         emacdata->phy_mode = PHY_MODE_SMII;
 180                 } else {
 181                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 182                         emacdata->phy_mode = PHY_MODE_RGMII;
 183                 }
 184                 if (i == 0)
 185                         memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 186                 else if (i == 1)
 187                         memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 188                 else if (i == 2)
 189                         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 190                 else if (i == 3)
 191                         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 192         }
 193 }
 194
 195 #define PCIX_READW(offset) \
 196         (readw(pcix_reg_base+offset))
 197
 198 #define PCIX_WRITEW(value, offset) \
 199         (writew(value, pcix_reg_base+offset))
 200
 201 #define PCIX_WRITEL(value, offset) \
 202         (writel(value, pcix_reg_base+offset))
 203
 204 /*
 205  * FIXME: This is only here to "make it work".  This will move
 206  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 207  * configuration library. -Matt
 208  */
 209 static void __init
 210 taishan_setup_pcix(void)
 211 {
 212         void *pcix_reg_base;
 213
 214         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 215
 216         /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 217         PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 218
 219         /* Disable all windows */
 220         PCIX_WRITEL(0, PCIX0_POM0SA);
 221         PCIX_WRITEL(0, PCIX0_POM1SA);
 222         PCIX_WRITEL(0, PCIX0_POM2SA);
 223         PCIX_WRITEL(0, PCIX0_PIM0SA);
 224         PCIX_WRITEL(0, PCIX0_PIM0SAH);
 225         PCIX_WRITEL(0, PCIX0_PIM1SA);
 226         PCIX_WRITEL(0, PCIX0_PIM2SA);
 227         PCIX_WRITEL(0, PCIX0_PIM2SAH);
 228
 229         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 230         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 231         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 232         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 233         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 234         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 235
 236         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 237         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 238         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 239         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 240         PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 241
 242         iounmap(pcix_reg_base);
 243
 244         eieio();
 245 }
 246
 247 static void __init
 248 taishan_setup_hose(void)
 249 {
 250         struct pci_controller *hose;
 251
 252         /* Configure windows on the PCI-X host bridge */
 253         taishan_setup_pcix();
 254
 255         hose = pcibios_alloc_controller();
 256
 257         if (!hose)
 258                 return;
 259
 260         hose->first_busno = 0;
 261         hose->last_busno = 0xff;
 262
 263         hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
 264
 265         pci_init_resource(&hose->io_resource,
 266                         TAISHAN_PCI_LOWER_IO,
 267                         TAISHAN_PCI_UPPER_IO,
 268                         IORESOURCE_IO,
 269                         "PCI host bridge");
 270
 271         pci_init_resource(&hose->mem_resources[0],
 272                         TAISHAN_PCI_LOWER_MEM,
 273                         TAISHAN_PCI_UPPER_MEM,
 274                         IORESOURCE_MEM,
 275                         "PCI host bridge");
 276
 277         hose->io_space.start = TAISHAN_PCI_LOWER_IO;
 278         hose->io_space.end = TAISHAN_PCI_UPPER_IO;
 279         hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
 280         hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
 281         hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
 282         isa_io_base = (unsigned long) hose->io_base_virt;
 283
 284         setup_indirect_pci(hose,
 285                         TAISHAN_PCI_CFGA_PLB32,
 286                         TAISHAN_PCI_CFGD_PLB32);
 287         hose->set_cfg_type = 1;
 288
 289         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 290
 291         ppc_md.pci_swizzle = common_swizzle;
 292         ppc_md.pci_map_irq = taishan_map_irq;
 293 }
 294
 295
 296 static void __init
 297 taishan_early_serial_map(void)
 298 {
 299         struct uart_port port;
 300
 301         /* Setup ioremapped serial port access */
 302         memset(&port, 0, sizeof(port));
 303         port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 304         port.irq = UART0_INT;
 305         port.uartclk = clocks.uart0;
 306         port.regshift = 0;
 307         port.iotype = UPIO_MEM;
 308         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 309         port.line = 0;
 310
 311         if (early_serial_setup(&port) != 0)
 312                 printk("Early serial init of port 0 failed\n");
 313
 314 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 315         /* Configure debug serial access */
 316         gen550_init(0, &port);
 317
 318         /* Purge TLB entry added in head_44x.S for early serial access */
 319         _tlbie(UART0_IO_BASE, 0);
 320 #endif
 321
 322         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 323         port.irq = UART1_INT;
 324         port.uartclk = clocks.uart1;
 325         port.line = 1;
 326
 327         if (early_serial_setup(&port) != 0)
 328                 printk("Early serial init of port 1 failed\n");
 329
 330 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 331         /* Configure debug serial access */
 332         gen550_init(1, &port);
 333 #endif
 334 }
 335
 336 static void __init
 337 taishan_setup_arch(void)
 338 {
 339         taishan_set_emacdata();
 340
 341         ibm440gx_tah_enable();
 342
 343         /*
 344          * Determine various clocks.
 345          * To be completely correct we should get SysClk
 346          * from FPGA, because it can be changed by on-board switches
 347          * --ebs
 348          */
 349         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 350         ocp_sys_info.opb_bus_freq = clocks.opb;
 351
 352         /* init to some ~sane value until calibrate_delay() runs */
 353         loops_per_jiffy = 50000000/HZ;
 354
 355         /* Setup PCI host bridge */
 356         taishan_setup_hose();
 357
 358 #ifdef CONFIG_BLK_DEV_INITRD
 359         if (initrd_start)
 360                 ROOT_DEV = Root_RAM0;
 361         else
 362 #endif
 363 #ifdef CONFIG_ROOT_NFS
 364                 ROOT_DEV = Root_NFS;
 365 #else
 366                 ROOT_DEV = Root_HDA1;
 367 #endif
 368
 369         taishan_early_serial_map();
 370
 371         /* Identify the system */
 372         printk("AMCC PowerPC 440GX Taishan Platform\n");
 373 }
 374
 375 static void __init taishan_init(void)
 376 {
 377         ibm440gx_l2c_setup(&clocks);
 378 }
 379
 380 void __init platform_init(unsigned long r3, unsigned long r4,
 381                 unsigned long r5, unsigned long r6, unsigned long r7)
 382 {
 383         ibm44x_platform_init(r3, r4, r5, r6, r7);
 384
 385         ppc_md.setup_arch = taishan_setup_arch;
 386         ppc_md.show_cpuinfo = taishan_show_cpuinfo;
 387         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 388
 389         ppc_md.calibrate_decr = taishan_calibrate_decr;
 390
 391 #ifdef CONFIG_KGDB
 392         ppc_md.early_serial_map = taishan_early_serial_map;
 393 #endif
 394         ppc_md.init = taishan_init;
 395 }
 396