arch/ppc/syslib/gt64260_pic.c

   1 /*
   2  * Interrupt controller support for Galileo's GT64260.
   3  *
   4  * Author: Chris Zankel <source@mvista.com>
   5  * Modified by: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * Based on sources from Rabeeh Khoury / Galileo Technology
   8  *
   9  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file contains the specific functions to support the GT64260
  17  * interrupt controller.
  18  *
  19  * The GT64260 has two main interrupt registers (high and low) that
  20  * summarizes the interrupts generated by the units of the GT64260.
  21  * Each bit is assigned to an interrupt number, where the low register
  22  * are assigned from IRQ0 to IRQ31 and the high cause register
  23  * from IRQ32 to IRQ63
  24  * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
  25  * to IRQ95 (GPP31).
  26  * get_irq() returns the lowest interrupt number that is currently asserted.
  27  *
  28  * Note:
  29  *  - This driver does not initialize the GPP when used as an interrupt
  30  *    input.
  31  */
  32
  33 #include <linux/stddef.h>
  34 #include <linux/init.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/sched.h>
  37 #include <linux/signal.h>
  38 #include <linux/delay.h>
  39 #include <linux/irq.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/system.h>
  43 #include <asm/irq.h>
  44 #include <asm/mv64x60.h>
  45 #include <asm/machdep.h>
  46
  47 #define CPU_INTR_STR    "gt64260 cpu interface error"
  48 #define PCI0_INTR_STR   "gt64260 pci 0 error"
  49 #define PCI1_INTR_STR   "gt64260 pci 1 error"
  50
  51 /* ========================== forward declaration ========================== */
  52
  53 static void gt64260_unmask_irq(unsigned int);
  54 static void gt64260_mask_irq(unsigned int);
  55
  56 /* ========================== local declarations =========================== */
  57
  58 struct hw_interrupt_type gt64260_pic = {
  59         .typename = " gt64260_pic ",
  60         .enable   = gt64260_unmask_irq,
  61         .disable  = gt64260_mask_irq,
  62         .ack      = gt64260_mask_irq,
  63         .end      = gt64260_unmask_irq,
  64 };
  65
  66 u32 gt64260_irq_base = 0;       /* GT64260 handles the next 96 IRQs from here */
  67
  68 static struct mv64x60_handle bh;
  69
  70 /* gt64260_init_irq()
  71  *
  72  *  This function initializes the interrupt controller. It assigns
  73  *  all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
  74  *
  75  * Note:
  76  *  We register all GPP inputs as interrupt source, but disable them.
  77  */
  78 void __init
  79 gt64260_init_irq(void)
  80 {
  81         int i;
  82
  83         if (ppc_md.progress)
  84                 ppc_md.progress("gt64260_init_irq: enter", 0x0);
  85
  86         bh.v_base = mv64x60_get_bridge_vbase();
  87
  88         ppc_cached_irq_mask[0] = 0;
  89         ppc_cached_irq_mask[1] = 0x0f000000;    /* Enable GPP intrs */
  90         ppc_cached_irq_mask[2] = 0;
  91
  92         /* disable all interrupts and clear current interrupts */
  93         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
  94         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
  95         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
  96         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
  97
  98         /* use the gt64260 for all (possible) interrupt sources */
  99         for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
 100                 irq_desc[i].chip = &gt64260_pic;
 101
 102         if (ppc_md.progress)
 103                 ppc_md.progress("gt64260_init_irq: exit", 0x0);
 104 }
 105
 106 /*
 107  * gt64260_get_irq()
 108  *
 109  *  This function returns the lowest interrupt number of all interrupts that
 110  *  are currently asserted.
 111  *
 112  * Output Variable(s):
 113  *  None.
 114  *
 115  * Returns:
 116  *  int <interrupt number> or -2 (bogus interrupt)
 117  */
 118 int
 119 gt64260_get_irq(void)
 120 {
 121         int irq;
 122         int irq_gpp;
 123
 124         irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO);
 125         irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
 126
 127         if (irq == -1) {
 128                 irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI);
 129                 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
 130
 131                 if (irq == -1)
 132                         irq = -2; /* bogus interrupt, should never happen */
 133                 else {
 134                         if (irq >= 24) {
 135                                 irq_gpp = mv64x60_read(&bh,
 136                                         MV64x60_GPP_INTR_CAUSE);
 137                                 irq_gpp = __ilog2(irq_gpp &
 138                                         ppc_cached_irq_mask[2]);
 139
 140                                 if (irq_gpp == -1)
 141                                         irq = -2;
 142                                 else {
 143                                         irq = irq_gpp + 64;
 144                                         mv64x60_write(&bh,
 145                                                 MV64x60_GPP_INTR_CAUSE,
 146                                                 ~(1 << (irq - 64)));
 147                                 }
 148                         } else
 149                                 irq += 32;
 150                 }
 151         }
 152
 153         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
 154
 155         if (irq < 0)
 156                 return (irq);
 157         else
 158                 return (gt64260_irq_base + irq);
 159 }
 160
 161 /* gt64260_unmask_irq()
 162  *
 163  *  This function enables an interrupt.
 164  *
 165  * Input Variable(s):
 166  *  unsigned int        interrupt number (IRQ0...IRQ95).
 167  *
 168  * Output Variable(s):
 169  *  None.
 170  *
 171  * Returns:
 172  *  void
 173  */
 174 static void
 175 gt64260_unmask_irq(unsigned int irq)
 176 {
 177         irq -= gt64260_irq_base;
 178
 179         if (irq > 31)
 180                 if (irq > 63) /* unmask GPP irq */
 181                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 182                                 ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
 183                 else /* mask high interrupt register */
 184                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 185                                 ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
 186         else /* mask low interrupt register */
 187                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 188                         ppc_cached_irq_mask[0] |= (1 << irq));
 189
 190         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 191         return;
 192 }
 193
 194 /* gt64260_mask_irq()
 195  *
 196  *  This function disables the requested interrupt.
 197  *
 198  * Input Variable(s):
 199  *  unsigned int        interrupt number (IRQ0...IRQ95).
 200  *
 201  * Output Variable(s):
 202  *  None.
 203  *
 204  * Returns:
 205  *  void
 206  */
 207 static void
 208 gt64260_mask_irq(unsigned int irq)
 209 {
 210         irq -= gt64260_irq_base;
 211
 212         if (irq > 31)
 213                 if (irq > 63) /* mask GPP irq */
 214                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 215                                 ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
 216                 else /* mask high interrupt register */
 217                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 218                                 ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
 219         else /* mask low interrupt register */
 220                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 221                         ppc_cached_irq_mask[0] &= ~(1 << irq));
 222
 223         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 224         return;
 225 }
 226
 227 static irqreturn_t
 228 gt64260_cpu_error_int_handler(int irq, void *dev_id)
 229 {
 230         printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n",
 231                 "Error on CPU interface - Cause regiser",
 232                 mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
 233         printk(KERN_ERR "\tCPU error register dump:\n");
 234         printk(KERN_ERR "\tAddress low  0x%08x\n",
 235                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
 236         printk(KERN_ERR "\tAddress high 0x%08x\n",
 237                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
 238         printk(KERN_ERR "\tData low     0x%08x\n",
 239                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
 240         printk(KERN_ERR "\tData high    0x%08x\n",
 241                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
 242         printk(KERN_ERR "\tParity       0x%08x\n",
 243                mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
 244         mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
 245         return IRQ_HANDLED;
 246 }
 247
 248 static irqreturn_t
 249 gt64260_pci_error_int_handler(int irq, void *dev_id)
 250 {
 251         u32 val;
 252         unsigned int pci_bus = (unsigned int)dev_id;
 253
 254         if (pci_bus == 0) {     /* Error on PCI 0 */
 255                 val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
 256                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 257                         "gt64260_pci_error_int_handler", pci_bus);
 258                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 259                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 260                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 261                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
 262                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 263                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
 264                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 265                        mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
 266                 printk(KERN_ERR "\tCommand        0x%08x\n",
 267                        mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
 268                 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
 269         }
 270         if (pci_bus == 1) {     /* Error on PCI 1 */
 271                 val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
 272                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 273                         "gt64260_pci_error_int_handler", pci_bus);
 274                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 275                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 276                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 277                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
 278                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 279                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
 280                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 281                        mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
 282                 printk(KERN_ERR "\tCommand        0x%08x\n",
 283                        mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
 284                 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
 285         }
 286         return IRQ_HANDLED;
 287 }
 288
 289 static int __init
 290 gt64260_register_hdlrs(void)
 291 {
 292         int rc;
 293
 294         /* Register CPU interface error interrupt handler */
 295         if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
 296                 gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
 297                 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
 298
 299         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
 300         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
 301
 302         /* Register PCI 0 error interrupt handler */
 303         if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
 304                     IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
 305                 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
 306                         rc);
 307
 308         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
 309         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
 310
 311         /* Register PCI 1 error interrupt handler */
 312         if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
 313                     IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
 314                 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
 315                         rc);
 316
 317         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
 318         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
 319
 320         return 0;
 321 }
 322
 323 arch_initcall(gt64260_register_hdlrs);