arch/ppc/syslib/ibm44x_common.c

   1 /*
   2  * PPC44x system library
   3  *
   4  * Matt Porter <mporter@kernel.crashing.org>
   5  * Copyright 2002-2005 MontaVista Software Inc.
   6  *
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  * Copyright (c) 2003, 2004 Zultys Technologies
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16 #include <linux/time.h>
  17 #include <linux/types.h>
  18 #include <linux/serial.h>
  19 #include <linux/module.h>
  20 #include <linux/initrd.h>
  21
  22 #include <asm/ibm44x.h>
  23 #include <asm/mmu.h>
  24 #include <asm/machdep.h>
  25 #include <asm/time.h>
  26 #include <asm/ppc4xx_pic.h>
  27 #include <asm/param.h>
  28 #include <asm/bootinfo.h>
  29 #include <asm/ppcboot.h>
  30
  31 #include <syslib/gen550.h>
  32
  33 /* Global Variables */
  34 bd_t __res;
  35
  36 phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
  37 {
  38         phys_addr_t page_4gb = 0;
  39
  40         /*
  41          * Trap the least significant 32-bit portions of an
  42          * address in the 440's 36-bit address space.  Fix
  43          * them up with the appropriate ERPN
  44          */
  45         if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
  46                 page_4gb = PPC44x_IO_PAGE;
  47         else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
  48                 page_4gb = PPC44x_PCICFG_PAGE;
  49 #ifdef CONFIG_440SP
  50         else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
  51                 page_4gb = PPC44x_PCICFG_PAGE;
  52         else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
  53                 page_4gb = PPC44x_PCICFG_PAGE;
  54 #endif
  55         else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
  56                 page_4gb = PPC44x_PCIMEM_PAGE;
  57
  58         return (page_4gb | addr);
  59 };
  60 EXPORT_SYMBOL(fixup_bigphys_addr);
  61
  62 void __init ibm44x_calibrate_decr(unsigned int freq)
  63 {
  64         tb_ticks_per_jiffy = freq / HZ;
  65         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  66
  67         /* Set the time base to zero */
  68         mtspr(SPRN_TBWL, 0);
  69         mtspr(SPRN_TBWU, 0);
  70
  71         /* Clear any pending timer interrupts */
  72         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  73
  74         /* Enable decrementer interrupt */
  75         mtspr(SPRN_TCR, TCR_DIE);
  76 }
  77
  78 extern void abort(void);
  79
  80 static void ibm44x_restart(char *cmd)
  81 {
  82         local_irq_disable();
  83         abort();
  84 }
  85
  86 static void ibm44x_power_off(void)
  87 {
  88         local_irq_disable();
  89         for(;;);
  90 }
  91
  92 static void ibm44x_halt(void)
  93 {
  94         local_irq_disable();
  95         for(;;);
  96 }
  97
  98 /*
  99  * Read the 44x memory controller to get size of system memory.
 100  */
 101 static unsigned long __init ibm44x_find_end_of_memory(void)
 102 {
 103         u32 i, bank_config;
 104         u32 mem_size = 0;
 105
 106         for (i=0; i<4; i++)
 107         {
 108                 switch (i)
 109                 {
 110                         case 0:
 111                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
 112                                 break;
 113                         case 1:
 114                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
 115                                 break;
 116                         case 2:
 117                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
 118                                 break;
 119                         case 3:
 120                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
 121                                 break;
 122                 }
 123
 124                 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
 125
 126                 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
 127                         continue;
 128                 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
 129                 {
 130                         case SDRAM_CONFIG_SIZE_8M:
 131                                 mem_size += PPC44x_MEM_SIZE_8M;
 132                                 break;
 133                         case SDRAM_CONFIG_SIZE_16M:
 134                                 mem_size += PPC44x_MEM_SIZE_16M;
 135                                 break;
 136                         case SDRAM_CONFIG_SIZE_32M:
 137                                 mem_size += PPC44x_MEM_SIZE_32M;
 138                                 break;
 139                         case SDRAM_CONFIG_SIZE_64M:
 140                                 mem_size += PPC44x_MEM_SIZE_64M;
 141                                 break;
 142                         case SDRAM_CONFIG_SIZE_128M:
 143                                 mem_size += PPC44x_MEM_SIZE_128M;
 144                                 break;
 145                         case SDRAM_CONFIG_SIZE_256M:
 146                                 mem_size += PPC44x_MEM_SIZE_256M;
 147                                 break;
 148                         case SDRAM_CONFIG_SIZE_512M:
 149                                 mem_size += PPC44x_MEM_SIZE_512M;
 150                                 break;
 151                 }
 152         }
 153         return mem_size;
 154 }
 155
 156 void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 157                                  unsigned long r6, unsigned long r7)
 158 {
 159         parse_bootinfo(find_bootinfo());
 160
 161         /*
 162          * If we were passed in a board information, copy it into the
 163          * residual data area.
 164          */
 165         if (r3)
 166                 __res = *(bd_t *)(r3 + KERNELBASE);
 167
 168 #if defined(CONFIG_BLK_DEV_INITRD)
 169         /*
 170          * If the init RAM disk has been configured in, and there's a valid
 171          * starting address for it, set it up.
 172          */
 173         if (r4) {
 174                 initrd_start = r4 + KERNELBASE;
 175                 initrd_end = r5 + KERNELBASE;
 176         }
 177 #endif  /* CONFIG_BLK_DEV_INITRD */
 178
 179         /* Copy the kernel command line arguments to a safe place. */
 180
 181         if (r6) {
 182                 *(char *) (r7 + KERNELBASE) = 0;
 183                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 184         }
 185
 186         ppc_md.init_IRQ = ppc4xx_pic_init;
 187         ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
 188         ppc_md.restart = ibm44x_restart;
 189         ppc_md.power_off = ibm44x_power_off;
 190         ppc_md.halt = ibm44x_halt;
 191
 192 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 193         ppc_md.progress = gen550_progress;
 194 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
 195 #ifdef CONFIG_KGDB
 196         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 197 #endif
 198
 199         /*
 200          * The Abatron BDI JTAG debugger does not tolerate others
 201          * mucking with the debug registers.
 202          */
 203 #if !defined(CONFIG_BDI_SWITCH)
 204         /* Enable internal debug mode */
 205         mtspr(SPRN_DBCR0, (DBCR0_IDM));
 206
 207         /* Clear any residual debug events */
 208         mtspr(SPRN_DBSR, 0xffffffff);
 209 #endif
 210 }
 211
 212 /* Called from machine_check_exception */
 213 void platform_machine_check(struct pt_regs *regs)
 214 {
 215 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 216         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
 217                mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
 218                mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
 219                mfdcr(DCRN_PLB0_BESRL));
 220         printk("PLB1: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
 221                mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
 222                mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
 223                mfdcr(DCRN_PLB1_BESRL));
 224 #else
 225         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x\n",
 226                 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
 227                 mfdcr(DCRN_PLB0_ACR),  mfdcr(DCRN_PLB0_BESR));
 228 #endif
 229         printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
 230                 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
 231                 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
 232         printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
 233                 mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
 234                 mfdcr(DCRN_OPB0_BSTAT));
 235 }