arch/powerpc/platforms/cell/beat_spu_priv1.c

   1 /*
   2  * spu hypervisor abstraction for Beat
   3  *
   4  * (C) Copyright 2006-2007 TOSHIBA CORPORATION
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include <asm/types.h>
  22 #include <asm/spu.h>
  23 #include <asm/spu_priv1.h>
  24
  25 #include "beat_wrapper.h"
  26
  27 static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
  28 {
  29         spu->shadow_int_mask_RW[class] = mask;
  30         beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
  31 }
  32
  33 static inline u64 _int_mask_get(struct spu *spu, int class)
  34 {
  35         return spu->shadow_int_mask_RW[class];
  36 }
  37
  38 static void int_mask_set(struct spu *spu, int class, u64 mask)
  39 {
  40         _int_mask_set(spu, class, mask);
  41 }
  42
  43 static u64 int_mask_get(struct spu *spu, int class)
  44 {
  45         return _int_mask_get(spu, class);
  46 }
  47
  48 static void int_mask_and(struct spu *spu, int class, u64 mask)
  49 {
  50         u64 old_mask;
  51         old_mask = _int_mask_get(spu, class);
  52         _int_mask_set(spu, class, old_mask & mask);
  53 }
  54
  55 static void int_mask_or(struct spu *spu, int class, u64 mask)
  56 {
  57         u64 old_mask;
  58         old_mask = _int_mask_get(spu, class);
  59         _int_mask_set(spu, class, old_mask | mask);
  60 }
  61
  62 static void int_stat_clear(struct spu *spu, int class, u64 stat)
  63 {
  64         beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
  65 }
  66
  67 static u64 int_stat_get(struct spu *spu, int class)
  68 {
  69         u64 int_stat;
  70         beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
  71         return int_stat;
  72 }
  73
  74 static void cpu_affinity_set(struct spu *spu, int cpu)
  75 {
  76         return;
  77 }
  78
  79 static u64 mfc_dar_get(struct spu *spu)
  80 {
  81         u64 dar;
  82         beat_get_spe_privileged_state_1_registers(
  83                 spu->spe_id,
  84                 offsetof(struct spu_priv1, mfc_dar_RW), &dar);
  85         return dar;
  86 }
  87
  88 static u64 mfc_dsisr_get(struct spu *spu)
  89 {
  90         u64 dsisr;
  91         beat_get_spe_privileged_state_1_registers(
  92                 spu->spe_id,
  93                 offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
  94         return dsisr;
  95 }
  96
  97 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
  98 {
  99         beat_set_spe_privileged_state_1_registers(
 100                 spu->spe_id,
 101                 offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
 102 }
 103
 104 static void mfc_sdr_setup(struct spu *spu)
 105 {
 106         return;
 107 }
 108
 109 static void mfc_sr1_set(struct spu *spu, u64 sr1)
 110 {
 111         beat_set_spe_privileged_state_1_registers(
 112                 spu->spe_id,
 113                 offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
 114 }
 115
 116 static u64 mfc_sr1_get(struct spu *spu)
 117 {
 118         u64 sr1;
 119         beat_get_spe_privileged_state_1_registers(
 120                 spu->spe_id,
 121                 offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
 122         return sr1;
 123 }
 124
 125 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
 126 {
 127         beat_set_spe_privileged_state_1_registers(
 128                 spu->spe_id,
 129                 offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
 130 }
 131
 132 static u64 mfc_tclass_id_get(struct spu *spu)
 133 {
 134         u64 tclass_id;
 135         beat_get_spe_privileged_state_1_registers(
 136                 spu->spe_id,
 137                 offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
 138         return tclass_id;
 139 }
 140
 141 static void tlb_invalidate(struct spu *spu)
 142 {
 143         beat_set_spe_privileged_state_1_registers(
 144                 spu->spe_id,
 145                 offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
 146 }
 147
 148 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
 149 {
 150         beat_set_spe_privileged_state_1_registers(
 151                 spu->spe_id,
 152                 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
 153                 id);
 154 }
 155
 156 static u64 resource_allocation_groupID_get(struct spu *spu)
 157 {
 158         u64 id;
 159         beat_get_spe_privileged_state_1_registers(
 160                 spu->spe_id,
 161                 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
 162                 &id);
 163         return id;
 164 }
 165
 166 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
 167 {
 168         beat_set_spe_privileged_state_1_registers(
 169                 spu->spe_id,
 170                 offsetof(struct spu_priv1, resource_allocation_enable_RW),
 171                 enable);
 172 }
 173
 174 static u64 resource_allocation_enable_get(struct spu *spu)
 175 {
 176         u64 enable;
 177         beat_get_spe_privileged_state_1_registers(
 178                 spu->spe_id,
 179                 offsetof(struct spu_priv1, resource_allocation_enable_RW),
 180                 &enable);
 181         return enable;
 182 }
 183
 184 const struct spu_priv1_ops spu_priv1_beat_ops = {
 185         .int_mask_and = int_mask_and,
 186         .int_mask_or = int_mask_or,
 187         .int_mask_set = int_mask_set,
 188         .int_mask_get = int_mask_get,
 189         .int_stat_clear = int_stat_clear,
 190         .int_stat_get = int_stat_get,
 191         .cpu_affinity_set = cpu_affinity_set,
 192         .mfc_dar_get = mfc_dar_get,
 193         .mfc_dsisr_get = mfc_dsisr_get,
 194         .mfc_dsisr_set = mfc_dsisr_set,
 195         .mfc_sdr_setup = mfc_sdr_setup,
 196         .mfc_sr1_set = mfc_sr1_set,
 197         .mfc_sr1_get = mfc_sr1_get,
 198         .mfc_tclass_id_set = mfc_tclass_id_set,
 199         .mfc_tclass_id_get = mfc_tclass_id_get,
 200         .tlb_invalidate = tlb_invalidate,
 201         .resource_allocation_groupID_set = resource_allocation_groupID_set,
 202         .resource_allocation_groupID_get = resource_allocation_groupID_get,
 203         .resource_allocation_enable_set = resource_allocation_enable_set,
 204         .resource_allocation_enable_get = resource_allocation_enable_get,
 205 };