2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
37 #include <asm/ptrace.h>
38 #include <linux/atomic.h>
39 #include <asm/code-patching.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
61 #define DBG(fmt...) udbg_printf(fmt)
66 extern void __secondary_start_pmac_0(void);
67 extern int pmac_pfunc_base_install(void);
69 static void (*pmac_tb_freeze
)(int freeze
);
73 #ifdef CONFIG_PPC_PMAC32_PSURGE
76 * Powersurge (old powermac SMP) support.
79 /* Addresses for powersurge registers */
80 #define HAMMERHEAD_BASE 0xf8000000
81 #define HHEAD_CONFIG 0x90
82 #define HHEAD_SEC_INTR 0xc0
84 /* register for interrupting the primary processor on the powersurge */
85 /* N.B. this is actually the ethernet ROM! */
86 #define PSURGE_PRI_INTR 0xf3019000
88 /* register for storing the start address for the secondary processor */
89 /* N.B. this is the PCI config space address register for the 1st bridge */
90 #define PSURGE_START 0xf2800000
92 /* Daystar/XLR8 4-CPU card */
93 #define PSURGE_QUAD_REG_ADDR 0xf8800000
95 #define PSURGE_QUAD_IRQ_SET 0
96 #define PSURGE_QUAD_IRQ_CLR 1
97 #define PSURGE_QUAD_IRQ_PRIMARY 2
98 #define PSURGE_QUAD_CKSTOP_CTL 3
99 #define PSURGE_QUAD_PRIMARY_ARB 4
100 #define PSURGE_QUAD_BOARD_ID 6
101 #define PSURGE_QUAD_WHICH_CPU 7
102 #define PSURGE_QUAD_CKSTOP_RDBK 8
103 #define PSURGE_QUAD_RESET_CTL 11
105 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
107 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
108 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
110 /* virtual addresses for the above */
111 static volatile u8 __iomem
*hhead_base
;
112 static volatile u8 __iomem
*quad_base
;
113 static volatile u32 __iomem
*psurge_pri_intr
;
114 static volatile u8 __iomem
*psurge_sec_intr
;
115 static volatile u32 __iomem
*psurge_start
;
117 /* values for psurge_type */
118 #define PSURGE_NONE -1
119 #define PSURGE_DUAL 0
120 #define PSURGE_QUAD_OKEE 1
121 #define PSURGE_QUAD_COTTON 2
122 #define PSURGE_QUAD_ICEGRASS 3
124 /* what sort of powersurge board we have */
125 static int psurge_type
= PSURGE_NONE
;
127 /* irq for secondary cpus to report */
128 static struct irq_host
*psurge_host
;
129 int psurge_secondary_virq
;
132 * Set and clear IPIs for powersurge.
134 static inline void psurge_set_ipi(int cpu
)
136 if (psurge_type
== PSURGE_NONE
)
139 in_be32(psurge_pri_intr
);
140 else if (psurge_type
== PSURGE_DUAL
)
141 out_8(psurge_sec_intr
, 0);
143 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET
, 1 << cpu
);
146 static inline void psurge_clr_ipi(int cpu
)
149 switch(psurge_type
) {
151 out_8(psurge_sec_intr
, ~0);
155 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, 1 << cpu
);
161 * On powersurge (old SMP powermac architecture) we don't have
162 * separate IPIs for separate messages like openpic does. Instead
163 * use the generic demux helpers
166 static irqreturn_t
psurge_ipi_intr(int irq
, void *d
)
168 psurge_clr_ipi(smp_processor_id());
174 static void smp_psurge_cause_ipi(int cpu
, unsigned long data
)
179 static int psurge_host_map(struct irq_host
*h
, unsigned int virq
,
182 irq_set_chip_and_handler(virq
, &dummy_irq_chip
, handle_percpu_irq
);
187 struct irq_host_ops psurge_host_ops
= {
188 .map
= psurge_host_map
,
191 static int psurge_secondary_ipi_init(void)
195 psurge_host
= irq_alloc_host(NULL
, IRQ_HOST_MAP_NOMAP
, 0,
196 &psurge_host_ops
, 0);
199 psurge_secondary_virq
= irq_create_direct_mapping(psurge_host
);
201 if (psurge_secondary_virq
)
202 rc
= request_irq(psurge_secondary_virq
, psurge_ipi_intr
,
203 IRQF_DISABLED
|IRQF_PERCPU
, "IPI", NULL
);
206 pr_err("Failed to setup secondary cpu IPI\n");
212 * Determine a quad card presence. We read the board ID register, we
213 * force the data bus to change to something else, and we read it again.
214 * It it's stable, then the register probably exist (ugh !)
216 static int __init
psurge_quad_probe(void)
221 type
= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
);
222 if (type
< PSURGE_QUAD_OKEE
|| type
> PSURGE_QUAD_ICEGRASS
223 || type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
226 /* looks OK, try a slightly more rigorous test */
227 /* bogus is not necessarily cacheline-aligned,
228 though I don't suppose that really matters. -- paulus */
229 for (i
= 0; i
< 100; i
++) {
230 volatile u32 bogus
[8];
231 bogus
[(0+i
)%8] = 0x00000000;
232 bogus
[(1+i
)%8] = 0x55555555;
233 bogus
[(2+i
)%8] = 0xFFFFFFFF;
234 bogus
[(3+i
)%8] = 0xAAAAAAAA;
235 bogus
[(4+i
)%8] = 0x33333333;
236 bogus
[(5+i
)%8] = 0xCCCCCCCC;
237 bogus
[(6+i
)%8] = 0xCCCCCCCC;
238 bogus
[(7+i
)%8] = 0x33333333;
240 asm volatile("dcbf 0,%0" : : "r" (bogus
) : "memory");
242 if (type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
248 static void __init
psurge_quad_init(void)
252 if (ppc_md
.progress
) ppc_md
.progress("psurge_quad_init", 0x351);
253 procbits
= ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU
);
254 if (psurge_type
== PSURGE_QUAD_ICEGRASS
)
255 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
257 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
259 out_8(psurge_sec_intr
, ~0);
260 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, procbits
);
261 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
262 if (psurge_type
!= PSURGE_QUAD_ICEGRASS
)
263 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
264 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
266 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL
, procbits
);
268 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
272 static int __init
smp_psurge_probe(void)
275 struct device_node
*dn
;
277 /* We don't do SMP on the PPC601 -- paulus */
278 if (PVR_VER(mfspr(SPRN_PVR
)) == 1)
282 * The powersurge cpu board can be used in the generation
283 * of powermacs that have a socket for an upgradeable cpu card,
284 * including the 7500, 8500, 9500, 9600.
285 * The device tree doesn't tell you if you have 2 cpus because
286 * OF doesn't know anything about the 2nd processor.
287 * Instead we look for magic bits in magic registers,
288 * in the hammerhead memory controller in the case of the
289 * dual-cpu powersurge board. -- paulus.
291 dn
= of_find_node_by_name(NULL
, "hammerhead");
296 hhead_base
= ioremap(HAMMERHEAD_BASE
, 0x800);
297 quad_base
= ioremap(PSURGE_QUAD_REG_ADDR
, 1024);
298 psurge_sec_intr
= hhead_base
+ HHEAD_SEC_INTR
;
300 psurge_type
= psurge_quad_probe();
301 if (psurge_type
!= PSURGE_DUAL
) {
303 /* All released cards using this HW design have 4 CPUs */
305 /* No sure how timebase sync works on those, let's use SW */
306 smp_ops
->give_timebase
= smp_generic_give_timebase
;
307 smp_ops
->take_timebase
= smp_generic_take_timebase
;
310 if ((in_8(hhead_base
+ HHEAD_CONFIG
) & 0x02) == 0) {
311 /* not a dual-cpu card */
313 psurge_type
= PSURGE_NONE
;
319 if (psurge_secondary_ipi_init())
322 psurge_start
= ioremap(PSURGE_START
, 4);
323 psurge_pri_intr
= ioremap(PSURGE_PRI_INTR
, 4);
325 /* This is necessary because OF doesn't know about the
326 * secondary cpu(s), and thus there aren't nodes in the
327 * device tree for them, and smp_setup_cpu_maps hasn't
328 * set their bits in cpu_present_mask.
332 for (i
= 1; i
< ncpus
; ++i
)
333 set_cpu_present(i
, true);
335 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_probe - done", 0x352);
340 static int __init
smp_psurge_kick_cpu(int nr
)
342 unsigned long start
= __pa(__secondary_start_pmac_0
) + nr
* 8;
343 unsigned long a
, flags
;
346 /* Defining this here is evil ... but I prefer hiding that
347 * crap to avoid giving people ideas that they can do the
350 extern volatile unsigned int cpu_callin_map
[NR_CPUS
];
352 /* may need to flush here if secondary bats aren't setup */
353 for (a
= KERNELBASE
; a
< KERNELBASE
+ 0x800000; a
+= 32)
354 asm volatile("dcbf 0,%0" : : "r" (a
) : "memory");
355 asm volatile("sync");
357 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu", 0x353);
359 /* This is going to freeze the timeebase, we disable interrupts */
360 local_irq_save(flags
);
362 out_be32(psurge_start
, start
);
368 * We can't use udelay here because the timebase is now frozen.
370 for (i
= 0; i
< 2000; ++i
)
371 asm volatile("nop" : : : "memory");
375 * Also, because the timebase is frozen, we must not return to the
376 * caller which will try to do udelay's etc... Instead, we wait -here-
377 * for the CPU to callin.
379 for (i
= 0; i
< 100000 && !cpu_callin_map
[nr
]; ++i
) {
380 for (j
= 1; j
< 10000; j
++)
381 asm volatile("nop" : : : "memory");
382 asm volatile("sync" : : : "memory");
384 if (!cpu_callin_map
[nr
])
387 /* And we do the TB sync here too for standard dual CPU cards */
388 if (psurge_type
== PSURGE_DUAL
) {
400 /* now interrupt the secondary, restarting both TBs */
401 if (psurge_type
== PSURGE_DUAL
)
404 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu - done", 0x354);
409 static struct irqaction psurge_irqaction
= {
410 .handler
= psurge_ipi_intr
,
411 .flags
= IRQF_DISABLED
|IRQF_PERCPU
,
412 .name
= "primary IPI",
415 static void __init
smp_psurge_setup_cpu(int cpu_nr
)
420 /* reset the entry point so if we get another intr we won't
421 * try to startup again */
422 out_be32(psurge_start
, 0x100);
423 if (setup_irq(irq_create_mapping(NULL
, 30), &psurge_irqaction
))
424 printk(KERN_ERR
"Couldn't get primary IPI interrupt");
427 void __init
smp_psurge_take_timebase(void)
429 if (psurge_type
!= PSURGE_DUAL
)
437 set_tb(timebase
>> 32, timebase
& 0xffffffff);
440 set_dec(tb_ticks_per_jiffy
/2);
443 void __init
smp_psurge_give_timebase(void)
445 /* Nothing to do here */
448 /* PowerSurge-style Macs */
449 struct smp_ops_t psurge_smp_ops
= {
450 .message_pass
= NULL
, /* Use smp_muxed_ipi_message_pass */
451 .cause_ipi
= smp_psurge_cause_ipi
,
452 .probe
= smp_psurge_probe
,
453 .kick_cpu
= smp_psurge_kick_cpu
,
454 .setup_cpu
= smp_psurge_setup_cpu
,
455 .give_timebase
= smp_psurge_give_timebase
,
456 .take_timebase
= smp_psurge_take_timebase
,
458 #endif /* CONFIG_PPC_PMAC32_PSURGE */
461 * Core 99 and later support
465 static void smp_core99_give_timebase(void)
469 local_irq_save(flags
);
474 (*pmac_tb_freeze
)(1);
481 (*pmac_tb_freeze
)(0);
484 local_irq_restore(flags
);
488 static void __devinit
smp_core99_take_timebase(void)
492 local_irq_save(flags
);
499 set_tb(timebase
>> 32, timebase
& 0xffffffff);
503 local_irq_restore(flags
);
508 * G5s enable/disable the timebase via an i2c-connected clock chip.
510 static struct pmac_i2c_bus
*pmac_tb_clock_chip_host
;
511 static u8 pmac_tb_pulsar_addr
;
513 static void smp_core99_cypress_tb_freeze(int freeze
)
518 /* Strangely, the device-tree says address is 0xd2, but darwin
521 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
522 pmac_i2c_mode_combined
);
523 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
524 0xd0 | pmac_i2c_read
,
529 data
= (data
& 0xf3) | (freeze
? 0x00 : 0x0c);
531 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
532 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
533 0xd0 | pmac_i2c_write
,
538 printk("Cypress Timebase %s rc: %d\n",
539 freeze
? "freeze" : "unfreeze", rc
);
540 panic("Timebase freeze failed !\n");
545 static void smp_core99_pulsar_tb_freeze(int freeze
)
550 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
551 pmac_i2c_mode_combined
);
552 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
553 pmac_tb_pulsar_addr
| pmac_i2c_read
,
558 data
= (data
& 0x88) | (freeze
? 0x11 : 0x22);
560 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
561 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
562 pmac_tb_pulsar_addr
| pmac_i2c_write
,
566 printk(KERN_ERR
"Pulsar Timebase %s rc: %d\n",
567 freeze
? "freeze" : "unfreeze", rc
);
568 panic("Timebase freeze failed !\n");
572 static void __init
smp_core99_setup_i2c_hwsync(int ncpus
)
574 struct device_node
*cc
= NULL
;
575 struct device_node
*p
;
576 const char *name
= NULL
;
580 /* Look for the clock chip */
581 while ((cc
= of_find_node_by_name(cc
, "i2c-hwclock")) != NULL
) {
582 p
= of_get_parent(cc
);
583 ok
= p
&& of_device_is_compatible(p
, "uni-n-i2c");
588 pmac_tb_clock_chip_host
= pmac_i2c_find_bus(cc
);
589 if (pmac_tb_clock_chip_host
== NULL
)
591 reg
= of_get_property(cc
, "reg", NULL
);
596 if (of_device_is_compatible(cc
,"pulsar-legacy-slewing")) {
597 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
598 pmac_tb_pulsar_addr
= 0xd2;
600 } else if (of_device_is_compatible(cc
, "cy28508")) {
601 pmac_tb_freeze
= smp_core99_cypress_tb_freeze
;
606 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
607 pmac_tb_pulsar_addr
= 0xd4;
611 if (pmac_tb_freeze
!= NULL
)
614 if (pmac_tb_freeze
!= NULL
) {
615 /* Open i2c bus for synchronous access */
616 if (pmac_i2c_open(pmac_tb_clock_chip_host
, 1)) {
617 printk(KERN_ERR
"Failed top open i2c bus for clock"
618 " sync, fallback to software sync !\n");
621 printk(KERN_INFO
"Processor timebase sync using %s i2c clock\n",
626 pmac_tb_freeze
= NULL
;
627 pmac_tb_clock_chip_host
= NULL
;
633 * Newer G5s uses a platform function
636 static void smp_core99_pfunc_tb_freeze(int freeze
)
638 struct device_node
*cpus
;
639 struct pmf_args args
;
641 cpus
= of_find_node_by_path("/cpus");
642 BUG_ON(cpus
== NULL
);
644 args
.u
[0].v
= !freeze
;
645 pmf_call_function(cpus
, "cpu-timebase", &args
);
649 #else /* CONFIG_PPC64 */
652 * SMP G4 use a GPIO to enable/disable the timebase.
655 static unsigned int core99_tb_gpio
; /* Timebase freeze GPIO */
657 static void smp_core99_gpio_tb_freeze(int freeze
)
660 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 4);
662 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 0);
663 pmac_call_feature(PMAC_FTR_READ_GPIO
, NULL
, core99_tb_gpio
, 0);
667 #endif /* !CONFIG_PPC64 */
669 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
670 volatile static long int core99_l2_cache
;
671 volatile static long int core99_l3_cache
;
673 static void __devinit
core99_init_caches(int cpu
)
676 if (!cpu_has_feature(CPU_FTR_L2CR
))
680 core99_l2_cache
= _get_L2CR();
681 printk("CPU0: L2CR is %lx\n", core99_l2_cache
);
683 printk("CPU%d: L2CR was %lx\n", cpu
, _get_L2CR());
685 _set_L2CR(core99_l2_cache
);
686 printk("CPU%d: L2CR set to %lx\n", cpu
, core99_l2_cache
);
689 if (!cpu_has_feature(CPU_FTR_L3CR
))
693 core99_l3_cache
= _get_L3CR();
694 printk("CPU0: L3CR is %lx\n", core99_l3_cache
);
696 printk("CPU%d: L3CR was %lx\n", cpu
, _get_L3CR());
698 _set_L3CR(core99_l3_cache
);
699 printk("CPU%d: L3CR set to %lx\n", cpu
, core99_l3_cache
);
701 #endif /* !CONFIG_PPC64 */
704 static void __init
smp_core99_setup(int ncpus
)
708 /* i2c based HW sync on some G5s */
709 if (of_machine_is_compatible("PowerMac7,2") ||
710 of_machine_is_compatible("PowerMac7,3") ||
711 of_machine_is_compatible("RackMac3,1"))
712 smp_core99_setup_i2c_hwsync(ncpus
);
714 /* pfunc based HW sync on recent G5s */
715 if (pmac_tb_freeze
== NULL
) {
716 struct device_node
*cpus
=
717 of_find_node_by_path("/cpus");
719 of_get_property(cpus
, "platform-cpu-timebase", NULL
)) {
720 pmac_tb_freeze
= smp_core99_pfunc_tb_freeze
;
721 printk(KERN_INFO
"Processor timebase sync using"
722 " platform function\n");
726 #else /* CONFIG_PPC64 */
728 /* GPIO based HW sync on ppc32 Core99 */
729 if (pmac_tb_freeze
== NULL
&& !of_machine_is_compatible("MacRISC4")) {
730 struct device_node
*cpu
;
731 const u32
*tbprop
= NULL
;
733 core99_tb_gpio
= KL_GPIO_TB_ENABLE
; /* default value */
734 cpu
= of_find_node_by_type(NULL
, "cpu");
736 tbprop
= of_get_property(cpu
, "timebase-enable", NULL
);
738 core99_tb_gpio
= *tbprop
;
741 pmac_tb_freeze
= smp_core99_gpio_tb_freeze
;
742 printk(KERN_INFO
"Processor timebase sync using"
743 " GPIO 0x%02x\n", core99_tb_gpio
);
746 #endif /* CONFIG_PPC64 */
748 /* No timebase sync, fallback to software */
749 if (pmac_tb_freeze
== NULL
) {
750 smp_ops
->give_timebase
= smp_generic_give_timebase
;
751 smp_ops
->take_timebase
= smp_generic_take_timebase
;
752 printk(KERN_INFO
"Processor timebase sync using software\n");
759 /* XXX should get this from reg properties */
760 for (i
= 1; i
< ncpus
; ++i
)
761 set_hard_smp_processor_id(i
, i
);
765 /* 32 bits SMP can't NAP */
766 if (!of_machine_is_compatible("MacRISC4"))
770 static int __init
smp_core99_probe(void)
772 struct device_node
*cpus
;
775 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_probe", 0x345);
777 /* Count CPUs in the device-tree */
778 for (cpus
= NULL
; (cpus
= of_find_node_by_type(cpus
, "cpu")) != NULL
;)
781 printk(KERN_INFO
"PowerMac SMP probe found %d cpus\n", ncpus
);
783 /* Nothing more to do if less than 2 of them */
787 /* We need to perform some early initialisations before we can start
788 * setting up SMP as we are running before initcalls
790 pmac_pfunc_base_install();
793 /* Setup various bits like timebase sync method, ability to nap, ... */
794 smp_core99_setup(ncpus
);
799 /* Collect l2cr and l3cr values from CPU 0 */
800 core99_init_caches(0);
805 static int __devinit
smp_core99_kick_cpu(int nr
)
807 unsigned int save_vector
;
808 unsigned long target
, flags
;
809 unsigned int *vector
= (unsigned int *)(PAGE_OFFSET
+0x100);
811 if (nr
< 0 || nr
> 3)
815 ppc_md
.progress("smp_core99_kick_cpu", 0x346);
817 local_irq_save(flags
);
819 /* Save reset vector */
820 save_vector
= *vector
;
822 /* Setup fake reset vector that does
823 * b __secondary_start_pmac_0 + nr*8
825 target
= (unsigned long) __secondary_start_pmac_0
+ nr
* 8;
826 patch_branch(vector
, target
, BRANCH_SET_LINK
);
828 /* Put some life in our friend */
829 pmac_call_feature(PMAC_FTR_RESET_CPU
, NULL
, nr
, 0);
831 /* FIXME: We wait a bit for the CPU to take the exception, I should
832 * instead wait for the entry code to set something for me. Well,
833 * ideally, all that crap will be done in prom.c and the CPU left
834 * in a RAM-based wait loop like CHRP.
838 /* Restore our exception vector */
839 *vector
= save_vector
;
840 flush_icache_range((unsigned long) vector
, (unsigned long) vector
+ 4);
842 local_irq_restore(flags
);
843 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_kick_cpu done", 0x347);
848 static void __devinit
smp_core99_setup_cpu(int cpu_nr
)
852 core99_init_caches(cpu_nr
);
855 mpic_setup_this_cpu();
859 #ifdef CONFIG_HOTPLUG_CPU
860 static int smp_core99_cpu_notify(struct notifier_block
*self
,
861 unsigned long action
, void *hcpu
)
867 case CPU_UP_PREPARE_FROZEN
:
868 /* Open i2c bus if it was used for tb sync */
869 if (pmac_tb_clock_chip_host
) {
870 rc
= pmac_i2c_open(pmac_tb_clock_chip_host
, 1);
872 pr_err("Failed to open i2c bus for time sync\n");
873 return notifier_from_errno(rc
);
878 case CPU_UP_CANCELED
:
879 /* Close i2c bus if it was used for tb sync */
880 if (pmac_tb_clock_chip_host
)
881 pmac_i2c_close(pmac_tb_clock_chip_host
);
889 static struct notifier_block __cpuinitdata smp_core99_cpu_nb
= {
890 .notifier_call
= smp_core99_cpu_notify
,
892 #endif /* CONFIG_HOTPLUG_CPU */
894 static void __init
smp_core99_bringup_done(void)
896 extern void g5_phy_disable_cpu1(void);
898 /* Close i2c bus if it was used for tb sync */
899 if (pmac_tb_clock_chip_host
)
900 pmac_i2c_close(pmac_tb_clock_chip_host
);
902 /* If we didn't start the second CPU, we must take
905 if (of_machine_is_compatible("MacRISC4") &&
906 num_online_cpus() < 2) {
907 set_cpu_present(1, false);
908 g5_phy_disable_cpu1();
910 #ifdef CONFIG_HOTPLUG_CPU
911 register_cpu_notifier(&smp_core99_cpu_nb
);
915 ppc_md
.progress("smp_core99_bringup_done", 0x349);
917 #endif /* CONFIG_PPC64 */
919 #ifdef CONFIG_HOTPLUG_CPU
921 static int smp_core99_cpu_disable(void)
923 int rc
= generic_cpu_disable();
927 mpic_cpu_set_priority(0xf);
934 static void pmac_cpu_die(void)
936 int cpu
= smp_processor_id();
940 pr_debug("CPU%d offline\n", cpu
);
941 generic_set_cpu_dead(cpu
);
947 #else /* CONFIG_PPC32 */
949 static void pmac_cpu_die(void)
951 int cpu
= smp_processor_id();
957 * turn off as much as possible, we'll be
958 * kicked out as this will only be invoked
959 * on core99 platforms for now ...
962 printk(KERN_INFO
"CPU#%d offline\n", cpu
);
963 generic_set_cpu_dead(cpu
);
967 * Re-enable interrupts. The NAP code needs to enable them
968 * anyways, do it now so we deal with the case where one already
969 * happened while soft-disabled.
970 * We shouldn't get any external interrupts, only decrementer, and the
971 * decrementer handler is safe for use on offline CPUs
976 /* let's not take timer interrupts too often ... */
984 #endif /* else CONFIG_PPC32 */
985 #endif /* CONFIG_HOTPLUG_CPU */
987 /* Core99 Macs (dual G4s and G5s) */
988 struct smp_ops_t core99_smp_ops
= {
989 .message_pass
= smp_mpic_message_pass
,
990 .probe
= smp_core99_probe
,
992 .bringup_done
= smp_core99_bringup_done
,
994 .kick_cpu
= smp_core99_kick_cpu
,
995 .setup_cpu
= smp_core99_setup_cpu
,
996 .give_timebase
= smp_core99_give_timebase
,
997 .take_timebase
= smp_core99_take_timebase
,
998 #if defined(CONFIG_HOTPLUG_CPU)
999 .cpu_disable
= smp_core99_cpu_disable
,
1000 .cpu_die
= generic_cpu_die
,
1004 void __init
pmac_setup_smp(void)
1006 struct device_node
*np
;
1008 /* Check for Core99 */
1009 np
= of_find_node_by_name(NULL
, "uni-n");
1011 np
= of_find_node_by_name(NULL
, "u3");
1013 np
= of_find_node_by_name(NULL
, "u4");
1016 smp_ops
= &core99_smp_ops
;
1018 #ifdef CONFIG_PPC_PMAC32_PSURGE
1020 /* We have to set bits in cpu_possible_mask here since the
1021 * secondary CPU(s) aren't in the device tree. Various
1022 * things won't be initialized for CPUs not in the possible
1023 * map, so we really need to fix it up here.
1027 for (cpu
= 1; cpu
< 4 && cpu
< NR_CPUS
; ++cpu
)
1028 set_cpu_possible(cpu
, true);
1029 smp_ops
= &psurge_smp_ops
;
1031 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1033 #ifdef CONFIG_HOTPLUG_CPU
1034 ppc_md
.cpu_die
= pmac_cpu_die
;