arch/sh/boards/mach-cayman/setup.c

   1 /*
   2  * arch/sh/mach-cayman/setup.c
   3  *
   4  * SH5 Cayman support
   5  *
   6  * Copyright (C) 2002  David J. Mckay & Benedict Gaster
   7  * Copyright (C) 2003 - 2007  Paul Mundt
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <cpu/irq.h>
  17
  18 /*
  19  * Platform Dependent Interrupt Priorities.
  20  */
  21
  22 /* Using defaults defined in irq.h */
  23 #define RES NO_PRIORITY         /* Disabled */
  24 #define IR0 IRL0_PRIORITY       /* IRLs */
  25 #define IR1 IRL1_PRIORITY
  26 #define IR2 IRL2_PRIORITY
  27 #define IR3 IRL3_PRIORITY
  28 #define PCA INTA_PRIORITY       /* PCI Ints */
  29 #define PCB INTB_PRIORITY
  30 #define PCC INTC_PRIORITY
  31 #define PCD INTD_PRIORITY
  32 #define SER TOP_PRIORITY
  33 #define ERR TOP_PRIORITY
  34 #define PW0 TOP_PRIORITY
  35 #define PW1 TOP_PRIORITY
  36 #define PW2 TOP_PRIORITY
  37 #define PW3 TOP_PRIORITY
  38 #define DM0 NO_PRIORITY         /* DMA Ints */
  39 #define DM1 NO_PRIORITY
  40 #define DM2 NO_PRIORITY
  41 #define DM3 NO_PRIORITY
  42 #define DAE NO_PRIORITY
  43 #define TU0 TIMER_PRIORITY      /* TMU Ints */
  44 #define TU1 NO_PRIORITY
  45 #define TU2 NO_PRIORITY
  46 #define TI2 NO_PRIORITY
  47 #define ATI NO_PRIORITY         /* RTC Ints */
  48 #define PRI NO_PRIORITY
  49 #define CUI RTC_PRIORITY
  50 #define ERI SCIF_PRIORITY       /* SCIF Ints */
  51 #define RXI SCIF_PRIORITY
  52 #define BRI SCIF_PRIORITY
  53 #define TXI SCIF_PRIORITY
  54 #define ITI TOP_PRIORITY        /* WDT Ints */
  55
  56 /* Setup for the SMSC FDC37C935 */
  57 #define SMSC_SUPERIO_BASE       0x04000000
  58 #define SMSC_CONFIG_PORT_ADDR   0x3f0
  59 #define SMSC_INDEX_PORT_ADDR    SMSC_CONFIG_PORT_ADDR
  60 #define SMSC_DATA_PORT_ADDR     0x3f1
  61
  62 #define SMSC_ENTER_CONFIG_KEY   0x55
  63 #define SMSC_EXIT_CONFIG_KEY    0xaa
  64
  65 #define SMCS_LOGICAL_DEV_INDEX  0x07
  66 #define SMSC_DEVICE_ID_INDEX    0x20
  67 #define SMSC_DEVICE_REV_INDEX   0x21
  68 #define SMSC_ACTIVATE_INDEX     0x30
  69 #define SMSC_PRIMARY_BASE_INDEX  0x60
  70 #define SMSC_SECONDARY_BASE_INDEX 0x62
  71 #define SMSC_PRIMARY_INT_INDEX  0x70
  72 #define SMSC_SECONDARY_INT_INDEX 0x72
  73
  74 #define SMSC_IDE1_DEVICE        1
  75 #define SMSC_KEYBOARD_DEVICE    7
  76 #define SMSC_CONFIG_REGISTERS   8
  77
  78 #define SMSC_SUPERIO_READ_INDEXED(index) ({ \
  79         outb((index), SMSC_INDEX_PORT_ADDR); \
  80         inb(SMSC_DATA_PORT_ADDR); })
  81 #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
  82         outb((index), SMSC_INDEX_PORT_ADDR); \
  83         outb((val),   SMSC_DATA_PORT_ADDR); })
  84
  85 #define IDE1_PRIMARY_BASE       0x01f0
  86 #define IDE1_SECONDARY_BASE     0x03f6
  87
  88 unsigned long smsc_superio_virt;
  89
  90 int platform_int_priority[NR_INTC_IRQS] = {
  91         IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ  0- 7 */
  92         RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ  8-15 */
  93         PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
  94         RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
  95         TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
  96         RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
  97         RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
  98         RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
  99 };
 100
 101 static int __init smsc_superio_setup(void)
 102 {
 103         unsigned char devid, devrev;
 104
 105         smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
 106         if (!smsc_superio_virt) {
 107                 panic("Unable to remap SMSC SuperIO\n");
 108         }
 109
 110         /* Initially the chip is in run state */
 111         /* Put it into configuration state */
 112         outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 113         outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 114
 115         /* Read device ID info */
 116         devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
 117         devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
 118         printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
 119
 120         /* Select the keyboard device */
 121         SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 122
 123         /* enable it */
 124         SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
 125
 126         /* Select the interrupts */
 127         /* On a PC keyboard is IRQ1, mouse is IRQ12 */
 128         SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
 129         SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
 130
 131 #ifdef CONFIG_IDE
 132         /*
 133          * Only IDE1 exists on the Cayman
 134          */
 135
 136         /* Power it on */
 137         SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
 138
 139         SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 140         SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
 141
 142         SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
 143                                    SMSC_PRIMARY_BASE_INDEX + 0);
 144         SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
 145                                    SMSC_PRIMARY_BASE_INDEX + 1);
 146
 147         SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
 148                                    SMSC_SECONDARY_BASE_INDEX + 0);
 149         SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
 150                                    SMSC_SECONDARY_BASE_INDEX + 1);
 151
 152         SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
 153
 154         SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
 155                                    SMCS_LOGICAL_DEV_INDEX);
 156
 157         SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
 158         SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
 159         SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
 160         SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
 161 #endif
 162
 163         /* Exit the configuration state */
 164         outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 165
 166         return 0;
 167 }
 168 device_initcall(smsc_superio_setup);
 169
 170 static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len)
 171 {
 172         if (port < 0x400) {
 173                 extern unsigned long smsc_superio_virt;
 174                 return (void __iomem *)((port << 2) | smsc_superio_virt);
 175         }
 176
 177         return (void __iomem *)port;
 178 }
 179
 180 extern void init_cayman_irq(void);
 181
 182 static struct sh_machine_vector mv_cayman __initmv = {
 183         .mv_name                = "Hitachi Cayman",
 184         .mv_nr_irqs             = 64,
 185         .mv_ioport_map          = cayman_ioport_map,
 186         .mv_init_irq            = init_cayman_irq,
 187 };