2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
37 #include <trace/events/irq_vectors.h>
39 #include <asm/perf_event.h>
40 #include <asm/x86_init.h>
41 #include <asm/pgalloc.h>
42 #include <linux/atomic.h>
43 #include <asm/mpspec.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
47 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
58 unsigned int num_processors
;
60 unsigned disabled_cpus __cpuinitdata
;
62 /* Processor that is doing the boot up */
63 unsigned int boot_cpu_physical_apicid
= -1U;
66 * The highest APIC ID seen during enumeration.
68 unsigned int max_physical_apicid
;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map
;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
79 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
86 * On x86_32, the mapping between cpu and logical apicid may vary
87 * depending on apic in use. The following early percpu variable is
88 * used for the mapping. This is where the behaviors of x86_64 and 32
89 * actually diverge. Let's keep it ugly for now.
91 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
94 * Knob to control our willingness to enable the local APIC.
98 static int force_enable_local_apic __initdata
;
100 * APIC command line parameters
102 static int __init
parse_lapic(char *arg
)
104 force_enable_local_apic
= 1;
107 early_param("lapic", parse_lapic
);
108 /* Local APIC was disabled by the BIOS and enabled by the kernel */
109 static int enabled_via_apicbase
;
112 * Handle interrupt mode configuration register (IMCR).
113 * This register controls whether the interrupt signals
114 * that reach the BSP come from the master PIC or from the
115 * local APIC. Before entering Symmetric I/O Mode, either
116 * the BIOS or the operating system must switch out of
117 * PIC Mode by changing the IMCR.
119 static inline void imcr_pic_to_apic(void)
121 /* select IMCR register */
123 /* NMI and 8259 INTR go through APIC */
127 static inline void imcr_apic_to_pic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go directly to BSP */
137 static int apic_calibrate_pmtmr __initdata
;
138 static __init
int setup_apicpmtimer(char *s
)
140 apic_calibrate_pmtmr
= 1;
144 __setup("apicpmtimer", setup_apicpmtimer
);
148 #ifdef CONFIG_X86_X2APIC
149 /* x2apic enabled before OS handover */
150 static int x2apic_preenabled
;
151 static __init
int setup_nox2apic(char *str
)
153 if (x2apic_enabled()) {
154 pr_warning("Bios already enabled x2apic, "
155 "can't enforce nox2apic");
159 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
162 early_param("nox2apic", setup_nox2apic
);
165 unsigned long mp_lapic_addr
;
167 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
168 static int disable_apic_timer __initdata
;
169 /* Local APIC timer works in C2 */
170 int local_apic_timer_c2_ok
;
171 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
173 int first_system_vector
= 0xfe;
176 * Debug level, exported for io_apic.c
178 unsigned int apic_verbosity
;
182 /* Have we found an MP table */
183 int smp_found_config
;
185 static struct resource lapic_resource
= {
186 .name
= "Local APIC",
187 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
190 static unsigned int calibration_result
;
192 static void apic_pm_activate(void);
194 static unsigned long apic_phys
;
197 * Get the LAPIC version
199 static inline int lapic_get_version(void)
201 return GET_APIC_VERSION(apic_read(APIC_LVR
));
205 * Check, if the APIC is integrated or a separate chip
207 static inline int lapic_is_integrated(void)
212 return APIC_INTEGRATED(lapic_get_version());
217 * Check, whether this is a modern or a first generation APIC
219 static int modern_apic(void)
221 /* AMD systems use old APIC versions, so check the CPU */
222 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
223 boot_cpu_data
.x86
>= 0xf)
225 return lapic_get_version() >= 0x14;
229 * right after this call apic become NOOP driven
230 * so apic->write/read doesn't do anything
232 static void __init
apic_disable(void)
234 pr_info("APIC: switched to apic NOOP\n");
238 void native_apic_wait_icr_idle(void)
240 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
244 u32
native_safe_apic_wait_icr_idle(void)
251 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
255 } while (timeout
++ < 1000);
260 void native_apic_icr_write(u32 low
, u32 id
)
262 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
263 apic_write(APIC_ICR
, low
);
266 u64
native_apic_icr_read(void)
270 icr2
= apic_read(APIC_ICR2
);
271 icr1
= apic_read(APIC_ICR
);
273 return icr1
| ((u64
)icr2
<< 32);
278 * get_physical_broadcast - Get number of physical broadcast IDs
280 int get_physical_broadcast(void)
282 return modern_apic() ? 0xff : 0xf;
287 * lapic_get_maxlvt - get the maximum number of local vector table entries
289 int lapic_get_maxlvt(void)
293 v
= apic_read(APIC_LVR
);
295 * - we always have APIC integrated on 64bit mode
296 * - 82489DXs do not report # of LVT entries
298 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
306 #define APIC_DIVISOR 16
309 * This function sets up the local APIC timer, with a timeout of
310 * 'clocks' APIC bus clock. During calibration we actually call
311 * this function twice on the boot CPU, once with a bogus timeout
312 * value, second time for real. The other (noncalibrating) CPUs
313 * call this function only once, with the real, calibrated value.
315 * We do reads before writes even if unnecessary, to get around the
316 * P5 APIC double write bug.
318 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
320 unsigned int lvtt_value
, tmp_value
;
322 lvtt_value
= LOCAL_TIMER_VECTOR
;
324 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
325 if (!lapic_is_integrated())
326 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
329 lvtt_value
|= APIC_LVT_MASKED
;
331 apic_write(APIC_LVTT
, lvtt_value
);
336 tmp_value
= apic_read(APIC_TDCR
);
337 apic_write(APIC_TDCR
,
338 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
342 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
346 * Setup extended LVT, AMD specific
348 * Software should use the LVT offsets the BIOS provides. The offsets
349 * are determined by the subsystems using it like those for MCE
350 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
351 * are supported. Beginning with family 10h at least 4 offsets are
354 * Since the offsets must be consistent for all cores, we keep track
355 * of the LVT offsets in software and reserve the offset for the same
356 * vector also to be used on other cores. An offset is freed by
357 * setting the entry to APIC_EILVT_MASKED.
359 * If the BIOS is right, there should be no conflicts. Otherwise a
360 * "[Firmware Bug]: ..." error message is generated. However, if
361 * software does not properly determines the offsets, it is not
362 * necessarily a BIOS bug.
365 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
367 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
369 return (old
& APIC_EILVT_MASKED
)
370 || (new == APIC_EILVT_MASKED
)
371 || ((new & ~APIC_EILVT_MASKED
) == old
);
374 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
376 unsigned int rsvd
; /* 0: uninitialized */
378 if (offset
>= APIC_EILVT_NR_MAX
)
381 rsvd
= atomic_read(&eilvt_offsets
[offset
]) & ~APIC_EILVT_MASKED
;
384 !eilvt_entry_is_changeable(rsvd
, new))
385 /* may not change if vectors are different */
387 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
388 } while (rsvd
!= new);
394 * If mask=1, the LVT entry does not generate interrupts while mask=0
395 * enables the vector. See also the BKDGs. Must be called with
396 * preemption disabled.
399 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
401 unsigned long reg
= APIC_EILVTn(offset
);
402 unsigned int new, old
, reserved
;
404 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
405 old
= apic_read(reg
);
406 reserved
= reserve_eilvt_offset(offset
, new);
408 if (reserved
!= new) {
409 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
410 "vector 0x%x, but the register is already in use for "
411 "vector 0x%x on another cpu\n",
412 smp_processor_id(), reg
, offset
, new, reserved
);
416 if (!eilvt_entry_is_changeable(old
, new)) {
417 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
418 "vector 0x%x, but the register is already in use for "
419 "vector 0x%x on this cpu\n",
420 smp_processor_id(), reg
, offset
, new, old
);
424 apic_write(reg
, new);
428 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
431 * Program the next event, relative to now
433 static int lapic_next_event(unsigned long delta
,
434 struct clock_event_device
*evt
)
436 apic_write(APIC_TMICT
, delta
);
441 * Setup the lapic timer in periodic or oneshot mode
443 static void lapic_timer_setup(enum clock_event_mode mode
,
444 struct clock_event_device
*evt
)
449 /* Lapic used as dummy for broadcast ? */
450 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
453 local_irq_save(flags
);
456 case CLOCK_EVT_MODE_PERIODIC
:
457 case CLOCK_EVT_MODE_ONESHOT
:
458 __setup_APIC_LVTT(calibration_result
,
459 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
461 case CLOCK_EVT_MODE_UNUSED
:
462 case CLOCK_EVT_MODE_SHUTDOWN
:
463 v
= apic_read(APIC_LVTT
);
464 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
465 apic_write(APIC_LVTT
, v
);
466 apic_write(APIC_TMICT
, 0);
468 case CLOCK_EVT_MODE_RESUME
:
469 /* Nothing to do here */
473 local_irq_restore(flags
);
477 * Local APIC timer broadcast function
479 static void lapic_timer_broadcast(const struct cpumask
*mask
)
482 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
488 * The local apic timer can be used for any function which is CPU local.
490 static struct clock_event_device lapic_clockevent
= {
492 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
493 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
495 .set_mode
= lapic_timer_setup
,
496 .set_next_event
= lapic_next_event
,
497 .broadcast
= lapic_timer_broadcast
,
501 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
504 * Setup the local APIC timer for this CPU. Copy the initialized values
505 * of the boot CPU and register the clock event in the framework.
507 static void __cpuinit
setup_APIC_timer(void)
509 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
511 if (this_cpu_has(X86_FEATURE_ARAT
)) {
512 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
513 /* Make LAPIC timer preferrable over percpu HPET */
514 lapic_clockevent
.rating
= 150;
517 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
518 levt
->cpumask
= cpumask_of(smp_processor_id());
520 clockevents_register_device(levt
);
524 * In this functions we calibrate APIC bus clocks to the external timer.
526 * We want to do the calibration only once since we want to have local timer
527 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
530 * This was previously done by reading the PIT/HPET and waiting for a wrap
531 * around to find out, that a tick has elapsed. I have a box, where the PIT
532 * readout is broken, so it never gets out of the wait loop again. This was
533 * also reported by others.
535 * Monitoring the jiffies value is inaccurate and the clockevents
536 * infrastructure allows us to do a simple substitution of the interrupt
539 * The calibration routine also uses the pm_timer when possible, as the PIT
540 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
541 * back to normal later in the boot process).
544 #define LAPIC_CAL_LOOPS (HZ/10)
546 static __initdata
int lapic_cal_loops
= -1;
547 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
548 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
549 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
550 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
553 * Temporary interrupt handler.
555 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
557 unsigned long long tsc
= 0;
558 long tapic
= apic_read(APIC_TMCCT
);
559 unsigned long pm
= acpi_pm_read_early();
564 switch (lapic_cal_loops
++) {
566 lapic_cal_t1
= tapic
;
567 lapic_cal_tsc1
= tsc
;
569 lapic_cal_j1
= jiffies
;
572 case LAPIC_CAL_LOOPS
:
573 lapic_cal_t2
= tapic
;
574 lapic_cal_tsc2
= tsc
;
575 if (pm
< lapic_cal_pm1
)
576 pm
+= ACPI_PM_OVRRUN
;
578 lapic_cal_j2
= jiffies
;
584 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
586 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
587 const long pm_thresh
= pm_100ms
/ 100;
591 #ifndef CONFIG_X86_PM_TIMER
595 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
597 /* Check, if the PM timer is available */
601 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
603 if (deltapm
> (pm_100ms
- pm_thresh
) &&
604 deltapm
< (pm_100ms
+ pm_thresh
)) {
605 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
609 res
= (((u64
)deltapm
) * mult
) >> 22;
610 do_div(res
, 1000000);
611 pr_warning("APIC calibration not consistent "
612 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
614 /* Correct the lapic counter value */
615 res
= (((u64
)(*delta
)) * pm_100ms
);
616 do_div(res
, deltapm
);
617 pr_info("APIC delta adjusted to PM-Timer: "
618 "%lu (%ld)\n", (unsigned long)res
, *delta
);
621 /* Correct the tsc counter value */
623 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
624 do_div(res
, deltapm
);
625 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
626 "PM-Timer: %lu (%ld)\n",
627 (unsigned long)res
, *deltatsc
);
628 *deltatsc
= (long)res
;
634 static int __init
calibrate_APIC_clock(void)
636 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
637 void (*real_handler
)(struct clock_event_device
*dev
);
638 unsigned long deltaj
;
639 long delta
, deltatsc
;
640 int pm_referenced
= 0;
644 /* Replace the global interrupt handler */
645 real_handler
= global_clock_event
->event_handler
;
646 global_clock_event
->event_handler
= lapic_cal_handler
;
649 * Setup the APIC counter to maximum. There is no way the lapic
650 * can underflow in the 100ms detection time frame
652 __setup_APIC_LVTT(0xffffffff, 0, 0);
654 /* Let the interrupts run */
657 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
662 /* Restore the real event handler */
663 global_clock_event
->event_handler
= real_handler
;
665 /* Build delta t1-t2 as apic timer counts down */
666 delta
= lapic_cal_t1
- lapic_cal_t2
;
667 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
669 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
671 /* we trust the PM based calibration if possible */
672 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
675 /* Calculate the scaled math multiplication factor */
676 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
677 lapic_clockevent
.shift
);
678 lapic_clockevent
.max_delta_ns
=
679 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
680 lapic_clockevent
.min_delta_ns
=
681 clockevent_delta2ns(0xF, &lapic_clockevent
);
683 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
685 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
686 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
687 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
691 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
693 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
694 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
697 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
699 calibration_result
/ (1000000 / HZ
),
700 calibration_result
% (1000000 / HZ
));
703 * Do a sanity check on the APIC calibration result
705 if (calibration_result
< (1000000 / HZ
)) {
707 pr_warning("APIC frequency too slow, disabling apic timer\n");
711 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
714 * PM timer calibration failed or not turned on
715 * so lets try APIC timer based calibration
717 if (!pm_referenced
) {
718 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
721 * Setup the apic timer manually
723 levt
->event_handler
= lapic_cal_handler
;
724 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
725 lapic_cal_loops
= -1;
727 /* Let the interrupts run */
730 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
733 /* Stop the lapic timer */
734 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
737 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
738 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
740 /* Check, if the jiffies result is consistent */
741 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
742 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
744 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
748 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
749 pr_warning("APIC timer disabled due to verification failure\n");
757 * Setup the boot APIC
759 * Calibrate and verify the result.
761 void __init
setup_boot_APIC_clock(void)
764 * The local apic timer can be disabled via the kernel
765 * commandline or from the CPU detection code. Register the lapic
766 * timer as a dummy clock event source on SMP systems, so the
767 * broadcast mechanism is used. On UP systems simply ignore it.
769 if (disable_apic_timer
) {
770 pr_info("Disabling APIC timer\n");
771 /* No broadcast on UP ! */
772 if (num_possible_cpus() > 1) {
773 lapic_clockevent
.mult
= 1;
779 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
780 "calibrating APIC timer ...\n");
782 if (calibrate_APIC_clock()) {
783 /* No broadcast on UP ! */
784 if (num_possible_cpus() > 1)
790 * If nmi_watchdog is set to IO_APIC, we need the
791 * PIT/HPET going. Otherwise register lapic as a dummy
794 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
796 /* Setup the lapic or request the broadcast */
800 void __cpuinit
setup_secondary_APIC_clock(void)
806 * The guts of the apic timer interrupt
808 static void local_apic_timer_interrupt(void)
810 int cpu
= smp_processor_id();
811 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
814 * Normally we should not be here till LAPIC has been initialized but
815 * in some cases like kdump, its possible that there is a pending LAPIC
816 * timer interrupt from previous kernel's context and is delivered in
817 * new kernel the moment interrupts are enabled.
819 * Interrupts are enabled early and LAPIC is setup much later, hence
820 * its possible that when we get here evt->event_handler is NULL.
821 * Check for event_handler being NULL and discard the interrupt as
824 if (!evt
->event_handler
) {
825 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
827 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
832 * the NMI deadlock-detector uses this.
834 inc_irq_stat(apic_timer_irqs
);
836 evt
->event_handler(evt
);
840 * Local APIC timer interrupt. This is the most natural way for doing
841 * local interrupts, but local timer interrupts can be emulated by
842 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
844 * [ if a single-CPU system runs an SMP kernel then we call the local
845 * interrupt as well. Thus we cannot inline the local irq ... ]
847 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
849 struct pt_regs
*old_regs
= set_irq_regs(regs
);
852 * NOTE! We'd better ACK the irq immediately,
853 * because timer handling can be slow.
857 * update_process_times() expects us to have done irq_enter().
858 * Besides, if we don't timer interrupts ignore the global
859 * interrupt lock, which is the WrongThing (tm) to do.
863 trace_irq_vector_entry(LOCAL_TIMER_VECTOR
);
864 local_apic_timer_interrupt();
865 trace_irq_vector_exit(LOCAL_TIMER_VECTOR
);
868 set_irq_regs(old_regs
);
871 int setup_profiling_timer(unsigned int multiplier
)
877 * Local APIC start and shutdown
881 * clear_local_APIC - shutdown the local APIC
883 * This is called, when a CPU is disabled and before rebooting, so the state of
884 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
885 * leftovers during boot.
887 void clear_local_APIC(void)
892 /* APIC hasn't been mapped yet */
893 if (!x2apic_mode
&& !apic_phys
)
896 maxlvt
= lapic_get_maxlvt();
898 * Masking an LVT entry can trigger a local APIC error
899 * if the vector is zero. Mask LVTERR first to prevent this.
902 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
903 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
906 * Careful: we have to set masks only first to deassert
907 * any level-triggered sources.
909 v
= apic_read(APIC_LVTT
);
910 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
911 v
= apic_read(APIC_LVT0
);
912 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
913 v
= apic_read(APIC_LVT1
);
914 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
916 v
= apic_read(APIC_LVTPC
);
917 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
920 /* lets not touch this if we didn't frob it */
921 #ifdef CONFIG_X86_THERMAL_VECTOR
923 v
= apic_read(APIC_LVTTHMR
);
924 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
927 #ifdef CONFIG_X86_MCE_INTEL
929 v
= apic_read(APIC_LVTCMCI
);
930 if (!(v
& APIC_LVT_MASKED
))
931 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
936 * Clean APIC state for other OSs:
938 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
939 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
940 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
942 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
944 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
946 /* Integrated APIC (!82489DX) ? */
947 if (lapic_is_integrated()) {
949 /* Clear ESR due to Pentium errata 3AP and 11AP */
950 apic_write(APIC_ESR
, 0);
956 * disable_local_APIC - clear and disable the local APIC
958 void disable_local_APIC(void)
962 /* APIC hasn't been mapped yet */
963 if (!x2apic_mode
&& !apic_phys
)
969 * Disable APIC (implies clearing of registers
972 value
= apic_read(APIC_SPIV
);
973 value
&= ~APIC_SPIV_APIC_ENABLED
;
974 apic_write(APIC_SPIV
, value
);
978 * When LAPIC was disabled by the BIOS and enabled by the kernel,
979 * restore the disabled state.
981 if (enabled_via_apicbase
) {
984 rdmsr(MSR_IA32_APICBASE
, l
, h
);
985 l
&= ~MSR_IA32_APICBASE_ENABLE
;
986 wrmsr(MSR_IA32_APICBASE
, l
, h
);
992 * If Linux enabled the LAPIC against the BIOS default disable it down before
993 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
994 * not power-off. Additionally clear all LVT entries before disable_local_APIC
995 * for the case where Linux didn't enable the LAPIC.
997 void lapic_shutdown(void)
1001 if (!cpu_has_apic
&& !apic_from_smp_config())
1004 local_irq_save(flags
);
1006 #ifdef CONFIG_X86_32
1007 if (!enabled_via_apicbase
)
1011 disable_local_APIC();
1014 local_irq_restore(flags
);
1018 * This is to verify that we're looking at a real local APIC.
1019 * Check these against your board if the CPUs aren't getting
1020 * started for no apparent reason.
1022 int __init
verify_local_APIC(void)
1024 unsigned int reg0
, reg1
;
1027 * The version register is read-only in a real APIC.
1029 reg0
= apic_read(APIC_LVR
);
1030 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1031 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1032 reg1
= apic_read(APIC_LVR
);
1033 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1036 * The two version reads above should print the same
1037 * numbers. If the second one is different, then we
1038 * poke at a non-APIC.
1044 * Check if the version looks reasonably.
1046 reg1
= GET_APIC_VERSION(reg0
);
1047 if (reg1
== 0x00 || reg1
== 0xff)
1049 reg1
= lapic_get_maxlvt();
1050 if (reg1
< 0x02 || reg1
== 0xff)
1054 * The ID register is read/write in a real APIC.
1056 reg0
= apic_read(APIC_ID
);
1057 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1058 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1059 reg1
= apic_read(APIC_ID
);
1060 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1061 apic_write(APIC_ID
, reg0
);
1062 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1066 * The next two are just to see if we have sane values.
1067 * They're only really relevant if we're in Virtual Wire
1068 * compatibility mode, but most boxes are anymore.
1070 reg0
= apic_read(APIC_LVT0
);
1071 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1072 reg1
= apic_read(APIC_LVT1
);
1073 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1079 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1081 void __init
sync_Arb_IDs(void)
1084 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1087 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1093 apic_wait_icr_idle();
1095 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1096 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1097 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1101 * An initial setup of the virtual wire mode.
1103 void __init
init_bsp_APIC(void)
1108 * Don't do the setup now if we have a SMP BIOS as the
1109 * through-I/O-APIC virtual wire mode might be active.
1111 if (smp_found_config
|| !cpu_has_apic
)
1115 * Do not trust the local APIC being empty at bootup.
1122 value
= apic_read(APIC_SPIV
);
1123 value
&= ~APIC_VECTOR_MASK
;
1124 value
|= APIC_SPIV_APIC_ENABLED
;
1126 #ifdef CONFIG_X86_32
1127 /* This bit is reserved on P4/Xeon and should be cleared */
1128 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1129 (boot_cpu_data
.x86
== 15))
1130 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1133 value
|= APIC_SPIV_FOCUS_DISABLED
;
1134 value
|= SPURIOUS_APIC_VECTOR
;
1135 apic_write(APIC_SPIV
, value
);
1138 * Set up the virtual wire mode.
1140 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1141 value
= APIC_DM_NMI
;
1142 if (!lapic_is_integrated()) /* 82489DX */
1143 value
|= APIC_LVT_LEVEL_TRIGGER
;
1144 apic_write(APIC_LVT1
, value
);
1147 static void __cpuinit
lapic_setup_esr(void)
1149 unsigned int oldvalue
, value
, maxlvt
;
1151 if (!lapic_is_integrated()) {
1152 pr_info("No ESR for 82489DX.\n");
1156 if (apic
->disable_esr
) {
1158 * Something untraceable is creating bad interrupts on
1159 * secondary quads ... for the moment, just leave the
1160 * ESR disabled - we can't do anything useful with the
1161 * errors anyway - mbligh
1163 pr_info("Leaving ESR disabled.\n");
1167 maxlvt
= lapic_get_maxlvt();
1168 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1169 apic_write(APIC_ESR
, 0);
1170 oldvalue
= apic_read(APIC_ESR
);
1172 /* enables sending errors */
1173 value
= ERROR_APIC_VECTOR
;
1174 apic_write(APIC_LVTERR
, value
);
1177 * spec says clear errors after enabling vector.
1180 apic_write(APIC_ESR
, 0);
1181 value
= apic_read(APIC_ESR
);
1182 if (value
!= oldvalue
)
1183 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1184 "vector: 0x%08x after: 0x%08x\n",
1189 * setup_local_APIC - setup the local APIC
1191 * Used to setup local APIC while initializing BSP or bringin up APs.
1192 * Always called with preemption disabled.
1194 void __cpuinit
setup_local_APIC(void)
1196 int cpu
= smp_processor_id();
1197 unsigned int value
, queued
;
1198 int i
, j
, acked
= 0;
1199 unsigned long long tsc
= 0, ntsc
;
1200 long long max_loops
= cpu_khz
;
1206 disable_ioapic_support();
1210 #ifdef CONFIG_X86_32
1211 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1212 if (lapic_is_integrated() && apic
->disable_esr
) {
1213 apic_write(APIC_ESR
, 0);
1214 apic_write(APIC_ESR
, 0);
1215 apic_write(APIC_ESR
, 0);
1216 apic_write(APIC_ESR
, 0);
1219 perf_events_lapic_init();
1222 * Double-check whether this APIC is really registered.
1223 * This is meaningless in clustered apic mode, so we skip it.
1225 BUG_ON(!apic
->apic_id_registered());
1228 * Intel recommends to set DFR, LDR and TPR before enabling
1229 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1230 * document number 292116). So here it goes...
1232 apic
->init_apic_ldr();
1234 #ifdef CONFIG_X86_32
1236 * APIC LDR is initialized. If logical_apicid mapping was
1237 * initialized during get_smp_config(), make sure it matches the
1240 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1241 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1242 /* always use the value from LDR */
1243 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1244 logical_smp_processor_id();
1247 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1248 * node mapping during NUMA init. Now that logical apicid is
1249 * guaranteed to be known, give it another chance. This is already
1250 * a bit too late - percpu allocation has already happened without
1251 * proper NUMA affinity.
1253 if (apic
->x86_32_numa_cpu_node
)
1254 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid
, cpu
),
1255 apic
->x86_32_numa_cpu_node(cpu
));
1259 * Set Task Priority to 'accept all'. We never change this
1262 value
= apic_read(APIC_TASKPRI
);
1263 value
&= ~APIC_TPRI_MASK
;
1264 apic_write(APIC_TASKPRI
, value
);
1267 * After a crash, we no longer service the interrupts and a pending
1268 * interrupt from previous kernel might still have ISR bit set.
1270 * Most probably by now CPU has serviced that pending interrupt and
1271 * it might not have done the ack_APIC_irq() because it thought,
1272 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1273 * does not clear the ISR bit and cpu thinks it has already serivced
1274 * the interrupt. Hence a vector might get locked. It was noticed
1275 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1279 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1280 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1282 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1283 value
= apic_read(APIC_ISR
+ i
*0x10);
1284 for (j
= 31; j
>= 0; j
--) {
1285 if (value
& (1<<j
)) {
1292 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1298 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1301 } while (queued
&& max_loops
> 0);
1302 WARN_ON(max_loops
<= 0);
1305 * Now that we are all set up, enable the APIC
1307 value
= apic_read(APIC_SPIV
);
1308 value
&= ~APIC_VECTOR_MASK
;
1312 value
|= APIC_SPIV_APIC_ENABLED
;
1314 #ifdef CONFIG_X86_32
1316 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1317 * certain networking cards. If high frequency interrupts are
1318 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1319 * entry is masked/unmasked at a high rate as well then sooner or
1320 * later IOAPIC line gets 'stuck', no more interrupts are received
1321 * from the device. If focus CPU is disabled then the hang goes
1324 * [ This bug can be reproduced easily with a level-triggered
1325 * PCI Ne2000 networking cards and PII/PIII processors, dual
1329 * Actually disabling the focus CPU check just makes the hang less
1330 * frequent as it makes the interrupt distributon model be more
1331 * like LRU than MRU (the short-term load is more even across CPUs).
1332 * See also the comment in end_level_ioapic_irq(). --macro
1336 * - enable focus processor (bit==0)
1337 * - 64bit mode always use processor focus
1338 * so no need to set it
1340 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1344 * Set spurious IRQ vector
1346 value
|= SPURIOUS_APIC_VECTOR
;
1347 apic_write(APIC_SPIV
, value
);
1350 * Set up LVT0, LVT1:
1352 * set up through-local-APIC on the BP's LINT0. This is not
1353 * strictly necessary in pure symmetric-IO mode, but sometimes
1354 * we delegate interrupts to the 8259A.
1357 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1359 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1360 if (!cpu
&& (pic_mode
|| !value
)) {
1361 value
= APIC_DM_EXTINT
;
1362 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1364 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1365 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1367 apic_write(APIC_LVT0
, value
);
1370 * only the BP should see the LINT1 NMI signal, obviously.
1373 value
= APIC_DM_NMI
;
1375 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1376 if (!lapic_is_integrated()) /* 82489DX */
1377 value
|= APIC_LVT_LEVEL_TRIGGER
;
1378 apic_write(APIC_LVT1
, value
);
1380 #ifdef CONFIG_X86_MCE_INTEL
1381 /* Recheck CMCI information after local APIC is up on CPU #0 */
1387 void __cpuinit
end_local_APIC_setup(void)
1391 #ifdef CONFIG_X86_32
1394 /* Disable the local apic timer */
1395 value
= apic_read(APIC_LVTT
);
1396 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1397 apic_write(APIC_LVTT
, value
);
1404 void __init
bsp_end_local_APIC_setup(void)
1406 end_local_APIC_setup();
1409 * Now that local APIC setup is completed for BP, configure the fault
1410 * handling for interrupt remapping.
1412 if (intr_remapping_enabled
)
1413 enable_drhd_fault_handling();
1417 #ifdef CONFIG_X86_X2APIC
1418 void check_x2apic(void)
1420 if (x2apic_enabled()) {
1421 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1422 x2apic_preenabled
= x2apic_mode
= 1;
1426 void enable_x2apic(void)
1433 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1434 if (!(msr
& X2APIC_ENABLE
)) {
1435 printk_once(KERN_INFO
"Enabling x2apic\n");
1436 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, msr2
);
1439 #endif /* CONFIG_X86_X2APIC */
1441 int __init
enable_IR(void)
1443 #ifdef CONFIG_INTR_REMAP
1444 if (!intr_remapping_supported()) {
1445 pr_debug("intr-remapping not supported\n");
1449 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1450 pr_info("Skipped enabling intr-remap because of skipping "
1455 if (enable_intr_remapping(x2apic_supported()))
1458 pr_info("Enabled Interrupt-remapping\n");
1466 void __init
enable_IR_x2apic(void)
1468 unsigned long flags
;
1469 int ret
, x2apic_enabled
= 0;
1470 int dmar_table_init_ret
;
1472 dmar_table_init_ret
= dmar_table_init();
1473 if (dmar_table_init_ret
&& !x2apic_supported())
1476 ret
= save_ioapic_entries();
1478 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1482 local_irq_save(flags
);
1483 legacy_pic
->mask_all();
1484 mask_ioapic_entries();
1486 if (dmar_table_init_ret
)
1492 /* IR is required if there is APIC ID > 255 even when running
1495 if (max_physical_apicid
> 255 ||
1496 !hypervisor_x2apic_available())
1499 * without IR all CPUs can be addressed by IOAPIC/MSI
1500 * only in physical mode
1502 x2apic_force_phys();
1507 if (x2apic_supported() && !x2apic_mode
) {
1510 pr_info("Enabled x2apic\n");
1514 if (!ret
) /* IR enabling failed */
1515 restore_ioapic_entries();
1516 legacy_pic
->restore_mask();
1517 local_irq_restore(flags
);
1523 if (x2apic_preenabled
)
1524 panic("x2apic: enabled by BIOS but kernel init failed.");
1525 else if (cpu_has_x2apic
)
1526 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1529 #ifdef CONFIG_X86_64
1531 * Detect and enable local APICs on non-SMP boards.
1532 * Original code written by Keir Fraser.
1533 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1534 * not correctly set up (usually the APIC timer won't work etc.)
1536 static int __init
detect_init_APIC(void)
1538 if (!cpu_has_apic
) {
1539 pr_info("No local APIC present\n");
1543 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1548 static int __init
apic_verify(void)
1553 * The APIC feature bit should now be enabled
1556 features
= cpuid_edx(1);
1557 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1558 pr_warning("Could not enable APIC!\n");
1561 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1562 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1564 /* The BIOS may have set up the APIC at some other address */
1565 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1566 if (l
& MSR_IA32_APICBASE_ENABLE
)
1567 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1569 pr_info("Found and enabled local APIC!\n");
1573 int __init
apic_force_enable(unsigned long addr
)
1581 * Some BIOSes disable the local APIC in the APIC_BASE
1582 * MSR. This can only be done in software for Intel P6 or later
1583 * and AMD K7 (Model > 1) or later.
1585 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1586 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1587 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1588 l
&= ~MSR_IA32_APICBASE_BASE
;
1589 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1590 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1591 enabled_via_apicbase
= 1;
1593 return apic_verify();
1597 * Detect and initialize APIC
1599 static int __init
detect_init_APIC(void)
1601 /* Disabled by kernel option? */
1605 switch (boot_cpu_data
.x86_vendor
) {
1606 case X86_VENDOR_AMD
:
1607 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1608 (boot_cpu_data
.x86
>= 15))
1611 case X86_VENDOR_INTEL
:
1612 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1613 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1620 if (!cpu_has_apic
) {
1622 * Over-ride BIOS and try to enable the local APIC only if
1623 * "lapic" specified.
1625 if (!force_enable_local_apic
) {
1626 pr_info("Local APIC disabled by BIOS -- "
1627 "you can enable it with \"lapic\"\n");
1630 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1642 pr_info("No local APIC present or hardware disabled\n");
1648 * init_apic_mappings - initialize APIC mappings
1650 void __init
init_apic_mappings(void)
1652 unsigned int new_apicid
;
1655 boot_cpu_physical_apicid
= read_apic_id();
1659 /* If no local APIC can be found return early */
1660 if (!smp_found_config
&& detect_init_APIC()) {
1661 /* lets NOP'ify apic operations */
1662 pr_info("APIC: disable apic facility\n");
1665 apic_phys
= mp_lapic_addr
;
1668 * acpi lapic path already maps that address in
1669 * acpi_register_lapic_address()
1671 if (!acpi_lapic
&& !smp_found_config
)
1672 register_lapic_address(apic_phys
);
1676 * Fetch the APIC ID of the BSP in case we have a
1677 * default configuration (or the MP table is broken).
1679 new_apicid
= read_apic_id();
1680 if (boot_cpu_physical_apicid
!= new_apicid
) {
1681 boot_cpu_physical_apicid
= new_apicid
;
1683 * yeah -- we lie about apic_version
1684 * in case if apic was disabled via boot option
1685 * but it's not a problem for SMP compiled kernel
1686 * since smp_sanity_check is prepared for such a case
1687 * and disable smp mode
1689 apic_version
[new_apicid
] =
1690 GET_APIC_VERSION(apic_read(APIC_LVR
));
1694 void __init
register_lapic_address(unsigned long address
)
1696 mp_lapic_addr
= address
;
1699 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1700 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1701 APIC_BASE
, mp_lapic_addr
);
1703 if (boot_cpu_physical_apicid
== -1U) {
1704 boot_cpu_physical_apicid
= read_apic_id();
1705 apic_version
[boot_cpu_physical_apicid
] =
1706 GET_APIC_VERSION(apic_read(APIC_LVR
));
1711 * This initializes the IO-APIC and APIC hardware if this is
1714 int apic_version
[MAX_LOCAL_APIC
];
1716 int __init
APIC_init_uniprocessor(void)
1719 pr_info("Apic disabled\n");
1722 #ifdef CONFIG_X86_64
1723 if (!cpu_has_apic
) {
1725 pr_info("Apic disabled by BIOS\n");
1729 if (!smp_found_config
&& !cpu_has_apic
)
1733 * Complain if the BIOS pretends there is one.
1735 if (!cpu_has_apic
&&
1736 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1737 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1738 boot_cpu_physical_apicid
);
1743 default_setup_apic_routing();
1745 verify_local_APIC();
1748 #ifdef CONFIG_X86_64
1749 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1752 * Hack: In case of kdump, after a crash, kernel might be booting
1753 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1754 * might be zero if read from MP tables. Get it from LAPIC.
1756 # ifdef CONFIG_CRASH_DUMP
1757 boot_cpu_physical_apicid
= read_apic_id();
1760 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1763 #ifdef CONFIG_X86_IO_APIC
1765 * Now enable IO-APICs, actually call clear_IO_APIC
1766 * We need clear_IO_APIC before enabling error vector
1768 if (!skip_ioapic_setup
&& nr_ioapics
)
1772 bsp_end_local_APIC_setup();
1774 #ifdef CONFIG_X86_IO_APIC
1775 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1782 x86_init
.timers
.setup_percpu_clockev();
1787 * Local APIC interrupts
1791 * This interrupt should _never_ happen with our APIC/SMP architecture
1793 void smp_spurious_interrupt(struct pt_regs
*regs
)
1799 trace_irq_vector_entry(SPURIOUS_APIC_VECTOR
);
1801 * Check if this really is a spurious interrupt and ACK it
1802 * if it is a vectored one. Just in case...
1803 * Spurious interrupts should not be ACKed.
1805 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1806 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1809 inc_irq_stat(irq_spurious_count
);
1811 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1812 pr_info("spurious APIC interrupt on CPU#%d, "
1813 "should never happen.\n", smp_processor_id());
1814 trace_irq_vector_exit(SPURIOUS_APIC_VECTOR
);
1819 * This interrupt should never happen with our APIC/SMP architecture
1821 void smp_error_interrupt(struct pt_regs
*regs
)
1825 static const char * const error_interrupt_reason
[] = {
1826 "Send CS error", /* APIC Error Bit 0 */
1827 "Receive CS error", /* APIC Error Bit 1 */
1828 "Send accept error", /* APIC Error Bit 2 */
1829 "Receive accept error", /* APIC Error Bit 3 */
1830 "Redirectable IPI", /* APIC Error Bit 4 */
1831 "Send illegal vector", /* APIC Error Bit 5 */
1832 "Received illegal vector", /* APIC Error Bit 6 */
1833 "Illegal register address", /* APIC Error Bit 7 */
1838 trace_irq_vector_entry(ERROR_APIC_VECTOR
);
1839 /* First tickle the hardware, only then report what went on. -- REW */
1840 v0
= apic_read(APIC_ESR
);
1841 apic_write(APIC_ESR
, 0);
1842 v1
= apic_read(APIC_ESR
);
1844 atomic_inc(&irq_err_count
);
1846 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)",
1847 smp_processor_id(), v0
, v1
);
1852 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
1857 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
1859 trace_irq_vector_exit(ERROR_APIC_VECTOR
);
1864 * connect_bsp_APIC - attach the APIC to the interrupt system
1866 void __init
connect_bsp_APIC(void)
1868 #ifdef CONFIG_X86_32
1871 * Do not trust the local APIC being empty at bootup.
1875 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1876 * local APIC to INT and NMI lines.
1878 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1879 "enabling APIC mode.\n");
1883 if (apic
->enable_apic_mode
)
1884 apic
->enable_apic_mode();
1888 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1889 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1891 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1894 void disconnect_bsp_APIC(int virt_wire_setup
)
1898 #ifdef CONFIG_X86_32
1901 * Put the board back into PIC mode (has an effect only on
1902 * certain older boards). Note that APIC interrupts, including
1903 * IPIs, won't work beyond this point! The only exception are
1906 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1907 "entering PIC mode.\n");
1913 /* Go back to Virtual Wire compatibility mode */
1915 /* For the spurious interrupt use vector F, and enable it */
1916 value
= apic_read(APIC_SPIV
);
1917 value
&= ~APIC_VECTOR_MASK
;
1918 value
|= APIC_SPIV_APIC_ENABLED
;
1920 apic_write(APIC_SPIV
, value
);
1922 if (!virt_wire_setup
) {
1924 * For LVT0 make it edge triggered, active high,
1925 * external and enabled
1927 value
= apic_read(APIC_LVT0
);
1928 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1929 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1930 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1931 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1932 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1933 apic_write(APIC_LVT0
, value
);
1936 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1940 * For LVT1 make it edge triggered, active high,
1943 value
= apic_read(APIC_LVT1
);
1944 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1945 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1946 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1947 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1948 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1949 apic_write(APIC_LVT1
, value
);
1952 void __cpuinit
generic_processor_info(int apicid
, int version
)
1954 int cpu
, max
= nr_cpu_ids
;
1955 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
1956 phys_cpu_present_map
);
1959 * If boot cpu has not been detected yet, then only allow upto
1960 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1962 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
1963 apicid
!= boot_cpu_physical_apicid
) {
1964 int thiscpu
= max
+ disabled_cpus
- 1;
1967 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
1968 " reached. Keeping one slot for boot cpu."
1969 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1975 if (num_processors
>= nr_cpu_ids
) {
1976 int thiscpu
= max
+ disabled_cpus
;
1979 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1980 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1987 if (apicid
== boot_cpu_physical_apicid
) {
1989 * x86_bios_cpu_apicid is required to have processors listed
1990 * in same order as logical cpu numbers. Hence the first
1991 * entry is BSP, and so on.
1992 * boot_cpu_init() already hold bit 0 in cpu_present_mask
1997 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
2002 if (version
== 0x0) {
2003 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2007 apic_version
[apicid
] = version
;
2009 if (version
!= apic_version
[boot_cpu_physical_apicid
]) {
2010 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2011 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
2014 physid_set(apicid
, phys_cpu_present_map
);
2015 if (apicid
> max_physical_apicid
)
2016 max_physical_apicid
= apicid
;
2018 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2019 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2020 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2022 #ifdef CONFIG_X86_32
2023 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2024 apic
->x86_32_early_logical_apicid(cpu
);
2026 set_cpu_possible(cpu
, true);
2027 set_cpu_present(cpu
, true);
2030 int hard_smp_processor_id(void)
2032 return read_apic_id();
2035 void default_init_apic_ldr(void)
2039 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2040 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2041 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2042 apic_write(APIC_LDR
, val
);
2052 * 'active' is true if the local APIC was enabled by us and
2053 * not the BIOS; this signifies that we are also responsible
2054 * for disabling it before entering apm/acpi suspend
2057 /* r/w apic fields */
2058 unsigned int apic_id
;
2059 unsigned int apic_taskpri
;
2060 unsigned int apic_ldr
;
2061 unsigned int apic_dfr
;
2062 unsigned int apic_spiv
;
2063 unsigned int apic_lvtt
;
2064 unsigned int apic_lvtpc
;
2065 unsigned int apic_lvt0
;
2066 unsigned int apic_lvt1
;
2067 unsigned int apic_lvterr
;
2068 unsigned int apic_tmict
;
2069 unsigned int apic_tdcr
;
2070 unsigned int apic_thmr
;
2073 static int lapic_suspend(void)
2075 unsigned long flags
;
2078 if (!apic_pm_state
.active
)
2081 maxlvt
= lapic_get_maxlvt();
2083 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2084 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2085 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2086 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2087 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2088 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2090 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2091 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2092 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2093 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2094 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2095 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2096 #ifdef CONFIG_X86_THERMAL_VECTOR
2098 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2101 local_irq_save(flags
);
2102 disable_local_APIC();
2104 if (intr_remapping_enabled
)
2105 disable_intr_remapping();
2107 local_irq_restore(flags
);
2111 static void lapic_resume(void)
2114 unsigned long flags
;
2117 if (!apic_pm_state
.active
)
2120 local_irq_save(flags
);
2121 if (intr_remapping_enabled
) {
2123 * IO-APIC and PIC have their own resume routines.
2124 * We just mask them here to make sure the interrupt
2125 * subsystem is completely quiet while we enable x2apic
2126 * and interrupt-remapping.
2128 mask_ioapic_entries();
2129 legacy_pic
->mask_all();
2136 * Make sure the APICBASE points to the right address
2138 * FIXME! This will be wrong if we ever support suspend on
2139 * SMP! We'll need to do this as part of the CPU restore!
2141 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2142 l
&= ~MSR_IA32_APICBASE_BASE
;
2143 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2144 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2147 maxlvt
= lapic_get_maxlvt();
2148 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2149 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2150 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2151 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2152 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2153 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2154 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2155 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2156 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2158 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2161 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2162 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2163 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2164 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2165 apic_write(APIC_ESR
, 0);
2166 apic_read(APIC_ESR
);
2167 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2168 apic_write(APIC_ESR
, 0);
2169 apic_read(APIC_ESR
);
2171 if (intr_remapping_enabled
)
2172 reenable_intr_remapping(x2apic_mode
);
2174 local_irq_restore(flags
);
2178 * This device has no shutdown method - fully functioning local APICs
2179 * are needed on every CPU up until machine_halt/restart/poweroff.
2182 static struct syscore_ops lapic_syscore_ops
= {
2183 .resume
= lapic_resume
,
2184 .suspend
= lapic_suspend
,
2187 static void __cpuinit
apic_pm_activate(void)
2189 apic_pm_state
.active
= 1;
2192 static int __init
init_lapic_sysfs(void)
2194 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2196 register_syscore_ops(&lapic_syscore_ops
);
2201 /* local apic needs to resume before other devices access its registers. */
2202 core_initcall(init_lapic_sysfs
);
2204 #else /* CONFIG_PM */
2206 static void apic_pm_activate(void) { }
2208 #endif /* CONFIG_PM */
2210 #ifdef CONFIG_X86_64
2212 static int __cpuinit
apic_cluster_num(void)
2214 int i
, clusters
, zeros
;
2216 u16
*bios_cpu_apicid
;
2217 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2219 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2220 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2222 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2223 /* are we being called early in kernel startup? */
2224 if (bios_cpu_apicid
) {
2225 id
= bios_cpu_apicid
[i
];
2226 } else if (i
< nr_cpu_ids
) {
2228 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2234 if (id
!= BAD_APICID
)
2235 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2238 /* Problem: Partially populated chassis may not have CPUs in some of
2239 * the APIC clusters they have been allocated. Only present CPUs have
2240 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2241 * Since clusters are allocated sequentially, count zeros only if
2242 * they are bounded by ones.
2246 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2247 if (test_bit(i
, clustermap
)) {
2248 clusters
+= 1 + zeros
;
2257 static int __cpuinitdata multi_checked
;
2258 static int __cpuinitdata multi
;
2260 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2264 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2269 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2271 .callback
= set_multi
,
2272 .ident
= "IBM System Summit2",
2274 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2275 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2281 static void __cpuinit
dmi_check_multi(void)
2286 dmi_check_system(multi_dmi_table
);
2291 * apic_is_clustered_box() -- Check if we can expect good TSC
2293 * Thus far, the major user of this is IBM's Summit2 series:
2294 * Clustered boxes may have unsynced TSC problems if they are
2296 * Use DMI to check them
2298 __cpuinit
int apic_is_clustered_box(void)
2308 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2309 * not guaranteed to be synced between boards
2311 if (apic_cluster_num() > 1)
2319 * APIC command line parameters
2321 static int __init
setup_disableapic(char *arg
)
2324 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2327 early_param("disableapic", setup_disableapic
);
2329 /* same as disableapic, for compatibility */
2330 static int __init
setup_nolapic(char *arg
)
2332 return setup_disableapic(arg
);
2334 early_param("nolapic", setup_nolapic
);
2336 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2338 local_apic_timer_c2_ok
= 1;
2341 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2343 static int __init
parse_disable_apic_timer(char *arg
)
2345 disable_apic_timer
= 1;
2348 early_param("noapictimer", parse_disable_apic_timer
);
2350 static int __init
parse_nolapic_timer(char *arg
)
2352 disable_apic_timer
= 1;
2355 early_param("nolapic_timer", parse_nolapic_timer
);
2357 static int __init
apic_set_verbosity(char *arg
)
2360 #ifdef CONFIG_X86_64
2361 skip_ioapic_setup
= 0;
2367 if (strcmp("debug", arg
) == 0)
2368 apic_verbosity
= APIC_DEBUG
;
2369 else if (strcmp("verbose", arg
) == 0)
2370 apic_verbosity
= APIC_VERBOSE
;
2372 pr_warning("APIC Verbosity level %s not recognised"
2373 " use apic=verbose or apic=debug\n", arg
);
2379 early_param("apic", apic_set_verbosity
);
2381 static int __init
lapic_insert_resource(void)
2386 /* Put local APIC into the resource map. */
2387 lapic_resource
.start
= apic_phys
;
2388 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2389 insert_resource(&iomem_resource
, &lapic_resource
);
2395 * need call insert after e820_reserve_resources()
2396 * that is using request_resource
2398 late_initcall(lapic_insert_resource
);