2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_RAW_SPINLOCK(vector_lock
);
79 static struct ioapic
{
81 * # of IRQ routing registers
85 * Saved state during suspend/resume, or while enabling intr-remap.
87 struct IO_APIC_route_entry
*saved_registers
;
89 struct mpc_ioapic mp_config
;
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi gsi_config
;
92 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
93 } ioapics
[MAX_IO_APICS
];
95 #define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver
97 int mpc_ioapic_id(int id
)
99 return ioapics
[id
].mp_config
.apicid
;
102 unsigned int mpc_ioapic_addr(int id
)
104 return ioapics
[id
].mp_config
.apicaddr
;
107 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int id
)
109 return &ioapics
[id
].gsi_config
;
114 /* The one past the highest gsi number used */
117 /* MP IRQ source entries */
118 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
120 /* # of MP IRQ source entries */
124 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
126 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
127 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
130 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
132 int skip_ioapic_setup
;
135 * disable_ioapic_support() - disables ioapic support at runtime
137 void disable_ioapic_support(void)
141 noioapicreroute
= -1;
143 skip_ioapic_setup
= 1;
146 static int __init
parse_noapic(char *str
)
148 /* disable IO-APIC */
149 disable_ioapic_support();
152 early_param("noapic", parse_noapic
);
154 static int io_apic_setup_irq_pin(unsigned int irq
, int node
,
155 struct io_apic_irq_attr
*attr
);
157 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
158 void mp_save_irq(struct mpc_intsrc
*m
)
162 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
163 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
164 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
165 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
167 for (i
= 0; i
< mp_irq_entries
; i
++) {
168 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
172 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
173 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
174 panic("Max # of irq sources exceeded!!\n");
177 struct irq_pin_list
{
179 struct irq_pin_list
*next
;
182 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
184 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
188 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189 #ifdef CONFIG_SPARSE_IRQ
190 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
192 static struct irq_cfg irq_cfgx
[NR_IRQS
];
195 int __init
arch_early_irq_init(void)
200 if (!legacy_pic
->nr_legacy_irqs
) {
205 for (i
= 0; i
< nr_ioapics
; i
++) {
206 ioapics
[i
].saved_registers
=
207 kzalloc(sizeof(struct IO_APIC_route_entry
) *
208 ioapics
[i
].nr_registers
, GFP_KERNEL
);
209 if (!ioapics
[i
].saved_registers
)
210 pr_err("IOAPIC %d: suspend/resume impossible!\n", i
);
214 count
= ARRAY_SIZE(irq_cfgx
);
215 node
= cpu_to_node(0);
217 /* Make sure the legacy interrupts are marked in the bitmap */
218 irq_reserve_irqs(0, legacy_pic
->nr_legacy_irqs
);
220 for (i
= 0; i
< count
; i
++) {
221 irq_set_chip_data(i
, &cfg
[i
]);
222 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
223 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
225 * For legacy IRQ's, start with assigning irq0 to irq15 to
226 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
228 if (i
< legacy_pic
->nr_legacy_irqs
) {
229 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
230 cpumask_set_cpu(0, cfg
[i
].domain
);
237 #ifdef CONFIG_SPARSE_IRQ
238 static struct irq_cfg
*irq_cfg(unsigned int irq
)
240 return irq_get_chip_data(irq
);
243 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
247 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
250 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
252 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
256 free_cpumask_var(cfg
->domain
);
262 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
266 irq_set_chip_data(at
, NULL
);
267 free_cpumask_var(cfg
->domain
);
268 free_cpumask_var(cfg
->old_domain
);
274 struct irq_cfg
*irq_cfg(unsigned int irq
)
276 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
279 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
281 return irq_cfgx
+ irq
;
284 static inline void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
) { }
288 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
290 int res
= irq_alloc_desc_at(at
, node
);
296 cfg
= irq_get_chip_data(at
);
301 cfg
= alloc_irq_cfg(at
, node
);
303 irq_set_chip_data(at
, cfg
);
309 static int alloc_irq_from(unsigned int from
, int node
)
311 return irq_alloc_desc_from(from
, node
);
314 static void free_irq_at(unsigned int at
, struct irq_cfg
*cfg
)
316 free_irq_cfg(at
, cfg
);
322 unsigned int unused
[3];
324 unsigned int unused2
[11];
328 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
330 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
331 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
334 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
336 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
337 writel(vector
, &io_apic
->eoi
);
340 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
342 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
343 writel(reg
, &io_apic
->index
);
344 return readl(&io_apic
->data
);
347 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
349 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
350 writel(reg
, &io_apic
->index
);
351 writel(value
, &io_apic
->data
);
355 * Re-write a value: to be used for read-modify-write
356 * cycles where the read already set up the index register.
358 * Older SiS APIC requires we rewrite the index register
360 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
362 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
365 writel(reg
, &io_apic
->index
);
366 writel(value
, &io_apic
->data
);
369 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
371 struct irq_pin_list
*entry
;
374 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
375 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
380 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
381 /* Is the remote IRR bit set? */
382 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
383 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
387 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
393 struct { u32 w1
, w2
; };
394 struct IO_APIC_route_entry entry
;
397 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
399 union entry_union eu
;
401 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
402 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
403 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
404 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
409 * When we write a new IO APIC routing entry, we need to write the high
410 * word first! If the mask bit in the low word is clear, we will enable
411 * the interrupt, and we need to make sure the entry is fully populated
412 * before that happens.
415 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
417 union entry_union eu
= {{0, 0}};
420 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
421 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
424 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
427 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
428 __ioapic_write_entry(apic
, pin
, e
);
429 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
433 * When we mask an IO APIC routing entry, we need to write the low
434 * word first, in order to set the mask bit before we change the
437 static void ioapic_mask_entry(int apic
, int pin
)
440 union entry_union eu
= { .entry
.mask
= 1 };
442 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
443 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
444 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
445 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
449 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
450 * shared ISA-space IRQs, so we have to support them. We are super
451 * fast in the common case, and fast for shared ISA-space IRQs.
454 __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
456 struct irq_pin_list
**last
, *entry
;
458 /* don't allow duplicates */
459 last
= &cfg
->irq_2_pin
;
460 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
461 if (entry
->apic
== apic
&& entry
->pin
== pin
)
466 entry
= alloc_irq_pin_list(node
);
468 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
479 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
481 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
482 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
486 * Reroute an IRQ to a different pin.
488 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
489 int oldapic
, int oldpin
,
490 int newapic
, int newpin
)
492 struct irq_pin_list
*entry
;
494 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
495 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
496 entry
->apic
= newapic
;
498 /* every one is different, right? */
503 /* old apic/pin didn't exist, so just add new ones */
504 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
507 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
508 int mask_and
, int mask_or
,
509 void (*final
)(struct irq_pin_list
*entry
))
511 unsigned int reg
, pin
;
514 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
517 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
522 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
523 int mask_and
, int mask_or
,
524 void (*final
)(struct irq_pin_list
*entry
))
526 struct irq_pin_list
*entry
;
528 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
529 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
532 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
534 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
535 IO_APIC_REDIR_MASKED
, NULL
);
538 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
540 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
541 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
544 static void io_apic_sync(struct irq_pin_list
*entry
)
547 * Synchronize the IO-APIC and the CPU by doing
548 * a dummy read from the IO-APIC
550 struct io_apic __iomem
*io_apic
;
551 io_apic
= io_apic_base(entry
->apic
);
552 readl(&io_apic
->data
);
555 static void mask_ioapic(struct irq_cfg
*cfg
)
559 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
560 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
561 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
564 static void mask_ioapic_irq(struct irq_data
*data
)
566 mask_ioapic(data
->chip_data
);
569 static void __unmask_ioapic(struct irq_cfg
*cfg
)
571 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
574 static void unmask_ioapic(struct irq_cfg
*cfg
)
578 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
579 __unmask_ioapic(cfg
);
580 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
583 static void unmask_ioapic_irq(struct irq_data
*data
)
585 unmask_ioapic(data
->chip_data
);
588 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
590 struct IO_APIC_route_entry entry
;
592 /* Check delivery_mode to be sure we're not clearing an SMI pin */
593 entry
= ioapic_read_entry(apic
, pin
);
594 if (entry
.delivery_mode
== dest_SMI
)
597 * Disable it in the IO-APIC irq-routing table:
599 ioapic_mask_entry(apic
, pin
);
602 static void clear_IO_APIC (void)
606 for (apic
= 0; apic
< nr_ioapics
; apic
++)
607 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
608 clear_IO_APIC_pin(apic
, pin
);
613 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
614 * specific CPU-side IRQs.
618 static int pirq_entries
[MAX_PIRQS
] = {
619 [0 ... MAX_PIRQS
- 1] = -1
622 static int __init
ioapic_pirq_setup(char *str
)
625 int ints
[MAX_PIRQS
+1];
627 get_options(str
, ARRAY_SIZE(ints
), ints
);
629 apic_printk(APIC_VERBOSE
, KERN_INFO
630 "PIRQ redirection, working around broken MP-BIOS.\n");
632 if (ints
[0] < MAX_PIRQS
)
635 for (i
= 0; i
< max
; i
++) {
636 apic_printk(APIC_VERBOSE
, KERN_DEBUG
637 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
639 * PIRQs are mapped upside down, usually.
641 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
646 __setup("pirq=", ioapic_pirq_setup
);
647 #endif /* CONFIG_X86_32 */
650 * Saves all the IO-APIC RTE's
652 int save_ioapic_entries(void)
657 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
658 if (!ioapics
[apic
].saved_registers
) {
663 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
664 ioapics
[apic
].saved_registers
[pin
] =
665 ioapic_read_entry(apic
, pin
);
672 * Mask all IO APIC entries.
674 void mask_ioapic_entries(void)
678 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
679 if (!ioapics
[apic
].saved_registers
)
682 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
683 struct IO_APIC_route_entry entry
;
685 entry
= ioapics
[apic
].saved_registers
[pin
];
688 ioapic_write_entry(apic
, pin
, entry
);
695 * Restore IO APIC entries which was saved in the ioapic structure.
697 int restore_ioapic_entries(void)
701 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
702 if (!ioapics
[apic
].saved_registers
)
705 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
706 ioapic_write_entry(apic
, pin
,
707 ioapics
[apic
].saved_registers
[pin
]);
713 * Find the IRQ entry number of a certain pin.
715 static int find_irq_entry(int apic
, int pin
, int type
)
719 for (i
= 0; i
< mp_irq_entries
; i
++)
720 if (mp_irqs
[i
].irqtype
== type
&&
721 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(apic
) ||
722 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
723 mp_irqs
[i
].dstirq
== pin
)
730 * Find the pin to which IRQ[irq] (ISA) is connected
732 static int __init
find_isa_irq_pin(int irq
, int type
)
736 for (i
= 0; i
< mp_irq_entries
; i
++) {
737 int lbus
= mp_irqs
[i
].srcbus
;
739 if (test_bit(lbus
, mp_bus_not_pci
) &&
740 (mp_irqs
[i
].irqtype
== type
) &&
741 (mp_irqs
[i
].srcbusirq
== irq
))
743 return mp_irqs
[i
].dstirq
;
748 static int __init
find_isa_irq_apic(int irq
, int type
)
752 for (i
= 0; i
< mp_irq_entries
; i
++) {
753 int lbus
= mp_irqs
[i
].srcbus
;
755 if (test_bit(lbus
, mp_bus_not_pci
) &&
756 (mp_irqs
[i
].irqtype
== type
) &&
757 (mp_irqs
[i
].srcbusirq
== irq
))
760 if (i
< mp_irq_entries
) {
762 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
763 if (mpc_ioapic_id(apic
) == mp_irqs
[i
].dstapic
)
771 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
773 * EISA Edge/Level control register, ELCR
775 static int EISA_ELCR(unsigned int irq
)
777 if (irq
< legacy_pic
->nr_legacy_irqs
) {
778 unsigned int port
= 0x4d0 + (irq
>> 3);
779 return (inb(port
) >> (irq
& 7)) & 1;
781 apic_printk(APIC_VERBOSE
, KERN_INFO
782 "Broken MPtable reports ISA irq %d\n", irq
);
788 /* ISA interrupts are always polarity zero edge triggered,
789 * when listed as conforming in the MP table. */
791 #define default_ISA_trigger(idx) (0)
792 #define default_ISA_polarity(idx) (0)
794 /* EISA interrupts are always polarity zero and can be edge or level
795 * trigger depending on the ELCR value. If an interrupt is listed as
796 * EISA conforming in the MP table, that means its trigger type must
797 * be read in from the ELCR */
799 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
800 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
802 /* PCI interrupts are always polarity one level triggered,
803 * when listed as conforming in the MP table. */
805 #define default_PCI_trigger(idx) (1)
806 #define default_PCI_polarity(idx) (1)
808 /* MCA interrupts are always polarity zero level triggered,
809 * when listed as conforming in the MP table. */
811 #define default_MCA_trigger(idx) (1)
812 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
814 static int irq_polarity(int idx
)
816 int bus
= mp_irqs
[idx
].srcbus
;
820 * Determine IRQ line polarity (high active or low active):
822 switch (mp_irqs
[idx
].irqflag
& 3)
824 case 0: /* conforms, ie. bus-type dependent polarity */
825 if (test_bit(bus
, mp_bus_not_pci
))
826 polarity
= default_ISA_polarity(idx
);
828 polarity
= default_PCI_polarity(idx
);
830 case 1: /* high active */
835 case 2: /* reserved */
837 printk(KERN_WARNING
"broken BIOS!!\n");
841 case 3: /* low active */
846 default: /* invalid */
848 printk(KERN_WARNING
"broken BIOS!!\n");
856 static int irq_trigger(int idx
)
858 int bus
= mp_irqs
[idx
].srcbus
;
862 * Determine IRQ trigger mode (edge or level sensitive):
864 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
866 case 0: /* conforms, ie. bus-type dependent */
867 if (test_bit(bus
, mp_bus_not_pci
))
868 trigger
= default_ISA_trigger(idx
);
870 trigger
= default_PCI_trigger(idx
);
871 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
872 switch (mp_bus_id_to_type
[bus
]) {
873 case MP_BUS_ISA
: /* ISA pin */
875 /* set before the switch */
878 case MP_BUS_EISA
: /* EISA pin */
880 trigger
= default_EISA_trigger(idx
);
883 case MP_BUS_PCI
: /* PCI pin */
885 /* set before the switch */
888 case MP_BUS_MCA
: /* MCA pin */
890 trigger
= default_MCA_trigger(idx
);
895 printk(KERN_WARNING
"broken BIOS!!\n");
907 case 2: /* reserved */
909 printk(KERN_WARNING
"broken BIOS!!\n");
918 default: /* invalid */
920 printk(KERN_WARNING
"broken BIOS!!\n");
928 static int pin_2_irq(int idx
, int apic
, int pin
)
931 int bus
= mp_irqs
[idx
].srcbus
;
932 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(apic
);
935 * Debugging check, we are in big trouble if this message pops up!
937 if (mp_irqs
[idx
].dstirq
!= pin
)
938 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
940 if (test_bit(bus
, mp_bus_not_pci
)) {
941 irq
= mp_irqs
[idx
].srcbusirq
;
943 u32 gsi
= gsi_cfg
->gsi_base
+ pin
;
945 if (gsi
>= NR_IRQS_LEGACY
)
953 * PCI IRQ command line redirection. Yes, limits are hardcoded.
955 if ((pin
>= 16) && (pin
<= 23)) {
956 if (pirq_entries
[pin
-16] != -1) {
957 if (!pirq_entries
[pin
-16]) {
958 apic_printk(APIC_VERBOSE
, KERN_DEBUG
959 "disabling PIRQ%d\n", pin
-16);
961 irq
= pirq_entries
[pin
-16];
962 apic_printk(APIC_VERBOSE
, KERN_DEBUG
963 "using PIRQ%d -> IRQ %d\n",
974 * Find a specific PCI IRQ entry.
975 * Not an __init, possibly needed by modules
977 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
978 struct io_apic_irq_attr
*irq_attr
)
980 int apic
, i
, best_guess
= -1;
982 apic_printk(APIC_DEBUG
,
983 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
985 if (test_bit(bus
, mp_bus_not_pci
)) {
986 apic_printk(APIC_VERBOSE
,
987 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
990 for (i
= 0; i
< mp_irq_entries
; i
++) {
991 int lbus
= mp_irqs
[i
].srcbus
;
993 for (apic
= 0; apic
< nr_ioapics
; apic
++)
994 if (mpc_ioapic_id(apic
) == mp_irqs
[i
].dstapic
||
995 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
998 if (!test_bit(lbus
, mp_bus_not_pci
) &&
999 !mp_irqs
[i
].irqtype
&&
1001 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1002 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1004 if (!(apic
|| IO_APIC_IRQ(irq
)))
1007 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1008 set_io_apic_irq_attr(irq_attr
, apic
,
1015 * Use the first all-but-pin matching entry as a
1016 * best-guess fuzzy result for broken mptables.
1018 if (best_guess
< 0) {
1019 set_io_apic_irq_attr(irq_attr
, apic
,
1029 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1031 void lock_vector_lock(void)
1033 /* Used to the online set of cpus does not change
1034 * during assign_irq_vector.
1036 raw_spin_lock(&vector_lock
);
1039 void unlock_vector_lock(void)
1041 raw_spin_unlock(&vector_lock
);
1045 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1048 * NOTE! The local APIC isn't very good at handling
1049 * multiple interrupts at the same interrupt level.
1050 * As the interrupt level is determined by taking the
1051 * vector number and shifting that right by 4, we
1052 * want to spread these out a bit so that they don't
1053 * all fall in the same interrupt level.
1055 * Also, we've got to be careful not to trash gate
1056 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1058 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1059 static int current_offset
= VECTOR_OFFSET_START
% 8;
1060 unsigned int old_vector
;
1062 cpumask_var_t tmp_mask
;
1064 if (cfg
->move_in_progress
)
1067 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1070 old_vector
= cfg
->vector
;
1072 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1073 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1074 if (!cpumask_empty(tmp_mask
)) {
1075 free_cpumask_var(tmp_mask
);
1080 /* Only try and allocate irqs on cpus that are present */
1082 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1086 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1088 vector
= current_vector
;
1089 offset
= current_offset
;
1092 if (vector
>= first_system_vector
) {
1093 /* If out of vectors on large boxen, must share them. */
1094 offset
= (offset
+ 1) % 8;
1095 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1097 if (unlikely(current_vector
== vector
))
1100 if (test_bit(vector
, used_vectors
))
1103 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1104 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1107 current_vector
= vector
;
1108 current_offset
= offset
;
1110 cfg
->move_in_progress
= 1;
1111 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1113 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1114 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1115 cfg
->vector
= vector
;
1116 cpumask_copy(cfg
->domain
, tmp_mask
);
1120 free_cpumask_var(tmp_mask
);
1124 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1127 unsigned long flags
;
1129 raw_spin_lock_irqsave(&vector_lock
, flags
);
1130 err
= __assign_irq_vector(irq
, cfg
, mask
);
1131 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1135 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1139 BUG_ON(!cfg
->vector
);
1141 vector
= cfg
->vector
;
1142 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1143 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1146 cpumask_clear(cfg
->domain
);
1148 if (likely(!cfg
->move_in_progress
))
1150 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1151 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1153 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1155 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1159 cfg
->move_in_progress
= 0;
1162 void __setup_vector_irq(int cpu
)
1164 /* Initialize vector_irq on a new cpu */
1166 struct irq_cfg
*cfg
;
1169 * vector_lock will make sure that we don't run into irq vector
1170 * assignments that might be happening on another cpu in parallel,
1171 * while we setup our initial vector to irq mappings.
1173 raw_spin_lock(&vector_lock
);
1174 /* Mark the inuse vectors */
1175 for_each_active_irq(irq
) {
1176 cfg
= irq_get_chip_data(irq
);
1180 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1181 * will be part of the irq_cfg's domain.
1183 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1184 cpumask_set_cpu(cpu
, cfg
->domain
);
1186 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1188 vector
= cfg
->vector
;
1189 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1191 /* Mark the free vectors */
1192 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1193 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1198 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1199 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1201 raw_spin_unlock(&vector_lock
);
1204 static struct irq_chip ioapic_chip
;
1205 static struct irq_chip ir_ioapic_chip
;
1207 #ifdef CONFIG_X86_32
1208 static inline int IO_APIC_irq_trigger(int irq
)
1212 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1213 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1214 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1215 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1216 return irq_trigger(idx
);
1220 * nonexistent IRQs are edge default
1225 static inline int IO_APIC_irq_trigger(int irq
)
1231 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1232 unsigned long trigger
)
1234 struct irq_chip
*chip
= &ioapic_chip
;
1235 irq_flow_handler_t hdl
;
1238 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1239 trigger
== IOAPIC_LEVEL
) {
1240 irq_set_status_flags(irq
, IRQ_LEVEL
);
1243 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1247 if (irq_remapped(cfg
)) {
1248 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
1249 chip
= &ir_ioapic_chip
;
1250 fasteoi
= trigger
!= 0;
1253 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1254 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1255 fasteoi
? "fasteoi" : "edge");
1258 static int setup_ioapic_entry(int apic_id
, int irq
,
1259 struct IO_APIC_route_entry
*entry
,
1260 unsigned int destination
, int trigger
,
1261 int polarity
, int vector
, int pin
)
1264 * add it to the IO-APIC irq-routing table:
1266 memset(entry
,0,sizeof(*entry
));
1268 if (intr_remapping_enabled
) {
1269 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1271 struct IR_IO_APIC_route_entry
*ir_entry
=
1272 (struct IR_IO_APIC_route_entry
*) entry
;
1276 panic("No mapping iommu for ioapic %d\n", apic_id
);
1278 index
= alloc_irte(iommu
, irq
, 1);
1280 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1282 prepare_irte(&irte
, vector
, destination
);
1284 /* Set source-id of interrupt request */
1285 set_ioapic_sid(&irte
, apic_id
);
1287 modify_irte(irq
, &irte
);
1289 ir_entry
->index2
= (index
>> 15) & 0x1;
1291 ir_entry
->format
= 1;
1292 ir_entry
->index
= (index
& 0x7fff);
1294 * IO-APIC RTE will be configured with virtual vector.
1295 * irq handler will do the explicit EOI to the io-apic.
1297 ir_entry
->vector
= pin
;
1299 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"IOAPIC[%d]: "
1300 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1301 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1302 "Avail:%X Vector:%02X Dest:%08X "
1303 "SID:%04X SQ:%X SVT:%X)\n",
1304 apic_id
, irte
.present
, irte
.fpd
, irte
.dst_mode
,
1305 irte
.redir_hint
, irte
.trigger_mode
, irte
.dlvry_mode
,
1306 irte
.avail
, irte
.vector
, irte
.dest_id
,
1307 irte
.sid
, irte
.sq
, irte
.svt
);
1309 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1310 entry
->dest_mode
= apic
->irq_dest_mode
;
1311 entry
->dest
= destination
;
1312 entry
->vector
= vector
;
1315 entry
->mask
= 0; /* enable IRQ */
1316 entry
->trigger
= trigger
;
1317 entry
->polarity
= polarity
;
1319 /* Mask level triggered irqs.
1320 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1327 static void setup_ioapic_irq(int apic_id
, int pin
, unsigned int irq
,
1328 struct irq_cfg
*cfg
, int trigger
, int polarity
)
1330 struct IO_APIC_route_entry entry
;
1333 if (!IO_APIC_IRQ(irq
))
1336 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1337 * controllers like 8259. Now that IO-APIC can handle this irq, update
1340 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1341 apic
->vector_allocation_domain(0, cfg
->domain
);
1343 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1346 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1348 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1349 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1350 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1351 apic_id
, mpc_ioapic_id(apic_id
), pin
, cfg
->vector
,
1352 irq
, trigger
, polarity
, dest
);
1355 if (setup_ioapic_entry(mpc_ioapic_id(apic_id
), irq
, &entry
,
1356 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1357 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1358 mpc_ioapic_id(apic_id
), pin
);
1359 __clear_irq_vector(irq
, cfg
);
1363 ioapic_register_intr(irq
, cfg
, trigger
);
1364 if (irq
< legacy_pic
->nr_legacy_irqs
)
1365 legacy_pic
->mask(irq
);
1367 ioapic_write_entry(apic_id
, pin
, entry
);
1370 static bool __init
io_apic_pin_not_connected(int idx
, int apic_id
, int pin
)
1375 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" apic %d pin %d not connected\n",
1376 mpc_ioapic_id(apic_id
), pin
);
1380 static void __init
__io_apic_setup_irqs(unsigned int apic_id
)
1382 int idx
, node
= cpu_to_node(0);
1383 struct io_apic_irq_attr attr
;
1384 unsigned int pin
, irq
;
1386 for (pin
= 0; pin
< ioapics
[apic_id
].nr_registers
; pin
++) {
1387 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1388 if (io_apic_pin_not_connected(idx
, apic_id
, pin
))
1391 irq
= pin_2_irq(idx
, apic_id
, pin
);
1393 if ((apic_id
> 0) && (irq
> 16))
1397 * Skip the timer IRQ if there's a quirk handler
1398 * installed and if it returns 1:
1400 if (apic
->multi_timer_check
&&
1401 apic
->multi_timer_check(apic_id
, irq
))
1404 set_io_apic_irq_attr(&attr
, apic_id
, pin
, irq_trigger(idx
),
1407 io_apic_setup_irq_pin(irq
, node
, &attr
);
1411 static void __init
setup_IO_APIC_irqs(void)
1413 unsigned int apic_id
;
1415 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1417 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1418 __io_apic_setup_irqs(apic_id
);
1422 * for the gsit that is not in first ioapic
1423 * but could not use acpi_register_gsi()
1424 * like some special sci in IBM x3330
1426 void setup_IO_APIC_irq_extra(u32 gsi
)
1428 int apic_id
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1429 struct io_apic_irq_attr attr
;
1432 * Convert 'gsi' to 'ioapic.pin'.
1434 apic_id
= mp_find_ioapic(gsi
);
1438 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1439 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1443 irq
= pin_2_irq(idx
, apic_id
, pin
);
1445 /* Only handle the non legacy irqs on secondary ioapics */
1446 if (apic_id
== 0 || irq
< NR_IRQS_LEGACY
)
1449 set_io_apic_irq_attr(&attr
, apic_id
, pin
, irq_trigger(idx
),
1452 io_apic_setup_irq_pin_once(irq
, node
, &attr
);
1456 * Set up the timer pin, possibly with the 8259A-master behind.
1458 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1461 struct IO_APIC_route_entry entry
;
1463 if (intr_remapping_enabled
)
1466 memset(&entry
, 0, sizeof(entry
));
1469 * We use logical delivery to get the timer IRQ
1472 entry
.dest_mode
= apic
->irq_dest_mode
;
1473 entry
.mask
= 0; /* don't mask IRQ for edge */
1474 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1475 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1478 entry
.vector
= vector
;
1481 * The timer IRQ doesn't have to know that behind the
1482 * scene we may have a 8259A-master in AEOI mode ...
1484 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1488 * Add it to the IO-APIC irq-routing table:
1490 ioapic_write_entry(apic_id
, pin
, entry
);
1494 __apicdebuginit(void) print_IO_APIC(void)
1497 union IO_APIC_reg_00 reg_00
;
1498 union IO_APIC_reg_01 reg_01
;
1499 union IO_APIC_reg_02 reg_02
;
1500 union IO_APIC_reg_03 reg_03
;
1501 unsigned long flags
;
1502 struct irq_cfg
*cfg
;
1505 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1506 for (i
= 0; i
< nr_ioapics
; i
++)
1507 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1508 mpc_ioapic_id(i
), ioapics
[i
].nr_registers
);
1511 * We are a bit conservative about what we expect. We have to
1512 * know about every hardware change ASAP.
1514 printk(KERN_INFO
"testing the IO APIC.......................\n");
1516 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1518 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1519 reg_00
.raw
= io_apic_read(apic
, 0);
1520 reg_01
.raw
= io_apic_read(apic
, 1);
1521 if (reg_01
.bits
.version
>= 0x10)
1522 reg_02
.raw
= io_apic_read(apic
, 2);
1523 if (reg_01
.bits
.version
>= 0x20)
1524 reg_03
.raw
= io_apic_read(apic
, 3);
1525 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1528 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(apic
));
1529 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1530 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1531 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1532 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1534 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1535 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1536 reg_01
.bits
.entries
);
1538 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1539 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1540 reg_01
.bits
.version
);
1543 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1544 * but the value of reg_02 is read as the previous read register
1545 * value, so ignore it if reg_02 == reg_01.
1547 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1548 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1549 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1553 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1554 * or reg_03, but the value of reg_0[23] is read as the previous read
1555 * register value, so ignore it if reg_03 == reg_0[12].
1557 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1558 reg_03
.raw
!= reg_01
.raw
) {
1559 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1560 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1563 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1565 if (intr_remapping_enabled
) {
1566 printk(KERN_DEBUG
" NR Indx Fmt Mask Trig IRR"
1567 " Pol Stat Indx2 Zero Vect:\n");
1569 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1570 " Stat Dmod Deli Vect:\n");
1573 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1574 if (intr_remapping_enabled
) {
1575 struct IO_APIC_route_entry entry
;
1576 struct IR_IO_APIC_route_entry
*ir_entry
;
1578 entry
= ioapic_read_entry(apic
, i
);
1579 ir_entry
= (struct IR_IO_APIC_route_entry
*) &entry
;
1580 printk(KERN_DEBUG
" %02x %04X ",
1584 printk("%1d %1d %1d %1d %1d "
1585 "%1d %1d %X %02X\n",
1591 ir_entry
->delivery_status
,
1597 struct IO_APIC_route_entry entry
;
1599 entry
= ioapic_read_entry(apic
, i
);
1600 printk(KERN_DEBUG
" %02x %02X ",
1604 printk("%1d %1d %1d %1d %1d "
1610 entry
.delivery_status
,
1612 entry
.delivery_mode
,
1619 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1620 for_each_active_irq(irq
) {
1621 struct irq_pin_list
*entry
;
1623 cfg
= irq_get_chip_data(irq
);
1626 entry
= cfg
->irq_2_pin
;
1629 printk(KERN_DEBUG
"IRQ%d ", irq
);
1630 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1631 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1635 printk(KERN_INFO
".................................... done.\n");
1640 __apicdebuginit(void) print_APIC_field(int base
)
1646 for (i
= 0; i
< 8; i
++)
1647 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1649 printk(KERN_CONT
"\n");
1652 __apicdebuginit(void) print_local_APIC(void *dummy
)
1654 unsigned int i
, v
, ver
, maxlvt
;
1657 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1658 smp_processor_id(), hard_smp_processor_id());
1659 v
= apic_read(APIC_ID
);
1660 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1661 v
= apic_read(APIC_LVR
);
1662 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1663 ver
= GET_APIC_VERSION(v
);
1664 maxlvt
= lapic_get_maxlvt();
1666 v
= apic_read(APIC_TASKPRI
);
1667 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1669 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1670 if (!APIC_XAPIC(ver
)) {
1671 v
= apic_read(APIC_ARBPRI
);
1672 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1673 v
& APIC_ARBPRI_MASK
);
1675 v
= apic_read(APIC_PROCPRI
);
1676 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1680 * Remote read supported only in the 82489DX and local APIC for
1681 * Pentium processors.
1683 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1684 v
= apic_read(APIC_RRR
);
1685 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1688 v
= apic_read(APIC_LDR
);
1689 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1690 if (!x2apic_enabled()) {
1691 v
= apic_read(APIC_DFR
);
1692 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1694 v
= apic_read(APIC_SPIV
);
1695 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1697 printk(KERN_DEBUG
"... APIC ISR field:\n");
1698 print_APIC_field(APIC_ISR
);
1699 printk(KERN_DEBUG
"... APIC TMR field:\n");
1700 print_APIC_field(APIC_TMR
);
1701 printk(KERN_DEBUG
"... APIC IRR field:\n");
1702 print_APIC_field(APIC_IRR
);
1704 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1705 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1706 apic_write(APIC_ESR
, 0);
1708 v
= apic_read(APIC_ESR
);
1709 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1712 icr
= apic_icr_read();
1713 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1714 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1716 v
= apic_read(APIC_LVTT
);
1717 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1719 if (maxlvt
> 3) { /* PC is LVT#4. */
1720 v
= apic_read(APIC_LVTPC
);
1721 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1723 v
= apic_read(APIC_LVT0
);
1724 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1725 v
= apic_read(APIC_LVT1
);
1726 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1728 if (maxlvt
> 2) { /* ERR is LVT#3. */
1729 v
= apic_read(APIC_LVTERR
);
1730 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1733 v
= apic_read(APIC_TMICT
);
1734 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1735 v
= apic_read(APIC_TMCCT
);
1736 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1737 v
= apic_read(APIC_TDCR
);
1738 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1740 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1741 v
= apic_read(APIC_EFEAT
);
1742 maxlvt
= (v
>> 16) & 0xff;
1743 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1744 v
= apic_read(APIC_ECTRL
);
1745 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1746 for (i
= 0; i
< maxlvt
; i
++) {
1747 v
= apic_read(APIC_EILVTn(i
));
1748 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1754 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1762 for_each_online_cpu(cpu
) {
1765 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1770 __apicdebuginit(void) print_PIC(void)
1773 unsigned long flags
;
1775 if (!legacy_pic
->nr_legacy_irqs
)
1778 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1780 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1782 v
= inb(0xa1) << 8 | inb(0x21);
1783 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1785 v
= inb(0xa0) << 8 | inb(0x20);
1786 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1790 v
= inb(0xa0) << 8 | inb(0x20);
1794 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1796 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1798 v
= inb(0x4d1) << 8 | inb(0x4d0);
1799 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1802 static int __initdata show_lapic
= 1;
1803 static __init
int setup_show_lapic(char *arg
)
1807 if (strcmp(arg
, "all") == 0) {
1808 show_lapic
= CONFIG_NR_CPUS
;
1810 get_option(&arg
, &num
);
1817 __setup("show_lapic=", setup_show_lapic
);
1819 __apicdebuginit(int) print_ICs(void)
1821 if (apic_verbosity
== APIC_QUIET
)
1826 /* don't print out if apic is not there */
1827 if (!cpu_has_apic
&& !apic_from_smp_config())
1830 print_local_APICs(show_lapic
);
1836 late_initcall(print_ICs
);
1839 /* Where if anywhere is the i8259 connect in external int mode */
1840 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1842 void __init
enable_IO_APIC(void)
1844 int i8259_apic
, i8259_pin
;
1847 if (!legacy_pic
->nr_legacy_irqs
)
1850 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1852 /* See if any of the pins is in ExtINT mode */
1853 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1854 struct IO_APIC_route_entry entry
;
1855 entry
= ioapic_read_entry(apic
, pin
);
1857 /* If the interrupt line is enabled and in ExtInt mode
1858 * I have found the pin where the i8259 is connected.
1860 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1861 ioapic_i8259
.apic
= apic
;
1862 ioapic_i8259
.pin
= pin
;
1868 /* Look to see what if the MP table has reported the ExtINT */
1869 /* If we could not find the appropriate pin by looking at the ioapic
1870 * the i8259 probably is not connected the ioapic but give the
1871 * mptable a chance anyway.
1873 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1874 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1875 /* Trust the MP table if nothing is setup in the hardware */
1876 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1877 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1878 ioapic_i8259
.pin
= i8259_pin
;
1879 ioapic_i8259
.apic
= i8259_apic
;
1881 /* Complain if the MP table and the hardware disagree */
1882 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1883 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1885 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1889 * Do not trust the IO-APIC being empty at bootup
1895 * Not an __init, needed by the reboot code
1897 void disable_IO_APIC(void)
1900 * Clear the IO-APIC before rebooting:
1904 if (!legacy_pic
->nr_legacy_irqs
)
1908 * If the i8259 is routed through an IOAPIC
1909 * Put that IOAPIC in virtual wire mode
1910 * so legacy interrupts can be delivered.
1912 * With interrupt-remapping, for now we will use virtual wire A mode,
1913 * as virtual wire B is little complex (need to configure both
1914 * IOAPIC RTE as well as interrupt-remapping table entry).
1915 * As this gets called during crash dump, keep this simple for now.
1917 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1918 struct IO_APIC_route_entry entry
;
1920 memset(&entry
, 0, sizeof(entry
));
1921 entry
.mask
= 0; /* Enabled */
1922 entry
.trigger
= 0; /* Edge */
1924 entry
.polarity
= 0; /* High */
1925 entry
.delivery_status
= 0;
1926 entry
.dest_mode
= 0; /* Physical */
1927 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1929 entry
.dest
= read_apic_id();
1932 * Add it to the IO-APIC irq-routing table:
1934 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1938 * Use virtual wire A mode when interrupt remapping is enabled.
1940 if (cpu_has_apic
|| apic_from_smp_config())
1941 disconnect_bsp_APIC(!intr_remapping_enabled
&&
1942 ioapic_i8259
.pin
!= -1);
1945 #ifdef CONFIG_X86_32
1947 * function to set the IO-APIC physical IDs based on the
1948 * values stored in the MPC table.
1950 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1952 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1954 union IO_APIC_reg_00 reg_00
;
1955 physid_mask_t phys_id_present_map
;
1958 unsigned char old_id
;
1959 unsigned long flags
;
1962 * This is broken; anything with a real cpu count has to
1963 * circumvent this idiocy regardless.
1965 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1968 * Set the IOAPIC ID to the value stored in the MPC table.
1970 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1972 /* Read the register 0 value */
1973 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1974 reg_00
.raw
= io_apic_read(apic_id
, 0);
1975 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1977 old_id
= mpc_ioapic_id(apic_id
);
1979 if (mpc_ioapic_id(apic_id
) >= get_physical_broadcast()) {
1980 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1981 apic_id
, mpc_ioapic_id(apic_id
));
1982 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1984 ioapics
[apic_id
].mp_config
.apicid
= reg_00
.bits
.ID
;
1988 * Sanity check, is the ID really free? Every APIC in a
1989 * system must have a unique ID or we get lots of nice
1990 * 'stuck on smp_invalidate_needed IPI wait' messages.
1992 if (apic
->check_apicid_used(&phys_id_present_map
,
1993 mpc_ioapic_id(apic_id
))) {
1994 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1995 apic_id
, mpc_ioapic_id(apic_id
));
1996 for (i
= 0; i
< get_physical_broadcast(); i
++)
1997 if (!physid_isset(i
, phys_id_present_map
))
1999 if (i
>= get_physical_broadcast())
2000 panic("Max APIC ID exceeded!\n");
2001 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2003 physid_set(i
, phys_id_present_map
);
2004 ioapics
[apic_id
].mp_config
.apicid
= i
;
2007 apic
->apicid_to_cpu_present(mpc_ioapic_id(apic_id
),
2009 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2010 "phys_id_present_map\n",
2011 mpc_ioapic_id(apic_id
));
2012 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2016 * We need to adjust the IRQ routing table
2017 * if the ID changed.
2019 if (old_id
!= mpc_ioapic_id(apic_id
))
2020 for (i
= 0; i
< mp_irq_entries
; i
++)
2021 if (mp_irqs
[i
].dstapic
== old_id
)
2023 = mpc_ioapic_id(apic_id
);
2026 * Update the ID register according to the right value
2027 * from the MPC table if they are different.
2029 if (mpc_ioapic_id(apic_id
) == reg_00
.bits
.ID
)
2032 apic_printk(APIC_VERBOSE
, KERN_INFO
2033 "...changing IO-APIC physical APIC ID to %d ...",
2034 mpc_ioapic_id(apic_id
));
2036 reg_00
.bits
.ID
= mpc_ioapic_id(apic_id
);
2037 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2038 io_apic_write(apic_id
, 0, reg_00
.raw
);
2039 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2044 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2045 reg_00
.raw
= io_apic_read(apic_id
, 0);
2046 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2047 if (reg_00
.bits
.ID
!= mpc_ioapic_id(apic_id
))
2048 printk("could not set ID!\n");
2050 apic_printk(APIC_VERBOSE
, " ok.\n");
2054 void __init
setup_ioapic_ids_from_mpc(void)
2060 * Don't check I/O APIC IDs for xAPIC systems. They have
2061 * no meaning without the serial APIC bus.
2063 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2064 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2066 setup_ioapic_ids_from_mpc_nocheck();
2070 int no_timer_check __initdata
;
2072 static int __init
notimercheck(char *s
)
2077 __setup("no_timer_check", notimercheck
);
2080 * There is a nasty bug in some older SMP boards, their mptable lies
2081 * about the timer IRQ. We do the following to work around the situation:
2083 * - timer IRQ defaults to IO-APIC IRQ
2084 * - if this function detects that timer IRQs are defunct, then we fall
2085 * back to ISA timer IRQs
2087 static int __init
timer_irq_works(void)
2089 unsigned long t1
= jiffies
;
2090 unsigned long flags
;
2095 local_save_flags(flags
);
2097 /* Let ten ticks pass... */
2098 mdelay((10 * 1000) / HZ
);
2099 local_irq_restore(flags
);
2102 * Expect a few ticks at least, to be sure some possible
2103 * glue logic does not lock up after one or two first
2104 * ticks in a non-ExtINT mode. Also the local APIC
2105 * might have cached one ExtINT interrupt. Finally, at
2106 * least one tick may be lost due to delays.
2110 if (time_after(jiffies
, t1
+ 4))
2116 * In the SMP+IOAPIC case it might happen that there are an unspecified
2117 * number of pending IRQ events unhandled. These cases are very rare,
2118 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2119 * better to do it this way as thus we do not have to be aware of
2120 * 'pending' interrupts in the IRQ path, except at this point.
2123 * Edge triggered needs to resend any interrupt
2124 * that was delayed but this is now handled in the device
2129 * Starting up a edge-triggered IO-APIC interrupt is
2130 * nasty - we need to make sure that we get the edge.
2131 * If it is already asserted for some reason, we need
2132 * return 1 to indicate that is was pending.
2134 * This is not complete - we should be able to fake
2135 * an edge even if it isn't on the 8259A...
2138 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2140 int was_pending
= 0, irq
= data
->irq
;
2141 unsigned long flags
;
2143 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2144 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2145 legacy_pic
->mask(irq
);
2146 if (legacy_pic
->irq_pending(irq
))
2149 __unmask_ioapic(data
->chip_data
);
2150 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2155 static int ioapic_retrigger_irq(struct irq_data
*data
)
2157 struct irq_cfg
*cfg
= data
->chip_data
;
2158 unsigned long flags
;
2160 raw_spin_lock_irqsave(&vector_lock
, flags
);
2161 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2162 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2168 * Level and edge triggered IO-APIC interrupts need different handling,
2169 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2170 * handled with the level-triggered descriptor, but that one has slightly
2171 * more overhead. Level-triggered interrupts cannot be handled with the
2172 * edge-triggered handler, without risking IRQ storms and other ugly
2177 void send_cleanup_vector(struct irq_cfg
*cfg
)
2179 cpumask_var_t cleanup_mask
;
2181 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2183 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2184 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2186 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2187 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2188 free_cpumask_var(cleanup_mask
);
2190 cfg
->move_in_progress
= 0;
2193 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2196 struct irq_pin_list
*entry
;
2197 u8 vector
= cfg
->vector
;
2199 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2205 * With interrupt-remapping, destination information comes
2206 * from interrupt-remapping table entry.
2208 if (!irq_remapped(cfg
))
2209 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2210 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2211 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2213 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2218 * Either sets data->affinity to a valid value, and returns
2219 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2220 * leaves data->affinity untouched.
2222 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2223 unsigned int *dest_id
)
2225 struct irq_cfg
*cfg
= data
->chip_data
;
2227 if (!cpumask_intersects(mask
, cpu_online_mask
))
2230 if (assign_irq_vector(data
->irq
, data
->chip_data
, mask
))
2233 cpumask_copy(data
->affinity
, mask
);
2235 *dest_id
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
);
2240 ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2243 unsigned int dest
, irq
= data
->irq
;
2244 unsigned long flags
;
2247 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2248 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2250 /* Only the high 8 bits are valid. */
2251 dest
= SET_APIC_LOGICAL_ID(dest
);
2252 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2254 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2258 #ifdef CONFIG_INTR_REMAP
2261 * Migrate the IO-APIC irq in the presence of intr-remapping.
2263 * For both level and edge triggered, irq migration is a simple atomic
2264 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2266 * For level triggered, we eliminate the io-apic RTE modification (with the
2267 * updated vector information), by using a virtual vector (io-apic pin number).
2268 * Real vector that is used for interrupting cpu will be coming from
2269 * the interrupt-remapping table entry.
2272 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2275 struct irq_cfg
*cfg
= data
->chip_data
;
2276 unsigned int dest
, irq
= data
->irq
;
2279 if (!cpumask_intersects(mask
, cpu_online_mask
))
2282 if (get_irte(irq
, &irte
))
2285 if (assign_irq_vector(irq
, cfg
, mask
))
2288 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2290 irte
.vector
= cfg
->vector
;
2291 irte
.dest_id
= IRTE_DEST(dest
);
2294 * Modified the IRTE and flushes the Interrupt entry cache.
2296 modify_irte(irq
, &irte
);
2298 if (cfg
->move_in_progress
)
2299 send_cleanup_vector(cfg
);
2301 cpumask_copy(data
->affinity
, mask
);
2307 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2314 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2316 unsigned vector
, me
;
2322 me
= smp_processor_id();
2323 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2326 struct irq_desc
*desc
;
2327 struct irq_cfg
*cfg
;
2328 irq
= __this_cpu_read(vector_irq
[vector
]);
2333 desc
= irq_to_desc(irq
);
2338 raw_spin_lock(&desc
->lock
);
2341 * Check if the irq migration is in progress. If so, we
2342 * haven't received the cleanup request yet for this irq.
2344 if (cfg
->move_in_progress
)
2347 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2350 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2352 * Check if the vector that needs to be cleanedup is
2353 * registered at the cpu's IRR. If so, then this is not
2354 * the best time to clean it up. Lets clean it up in the
2355 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2358 if (irr
& (1 << (vector
% 32))) {
2359 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2362 __this_cpu_write(vector_irq
[vector
], -1);
2364 raw_spin_unlock(&desc
->lock
);
2370 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2374 if (likely(!cfg
->move_in_progress
))
2377 me
= smp_processor_id();
2379 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2380 send_cleanup_vector(cfg
);
2383 static void irq_complete_move(struct irq_cfg
*cfg
)
2385 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2388 void irq_force_complete_move(int irq
)
2390 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
2395 __irq_complete_move(cfg
, cfg
->vector
);
2398 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2401 static void ack_apic_edge(struct irq_data
*data
)
2403 irq_complete_move(data
->chip_data
);
2408 atomic_t irq_mis_count
;
2411 * IO-APIC versions below 0x20 don't support EOI register.
2412 * For the record, here is the information about various versions:
2414 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2415 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2418 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2419 * version as 0x2. This is an error with documentation and these ICH chips
2420 * use io-apic's of version 0x20.
2422 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2423 * Otherwise, we simulate the EOI message manually by changing the trigger
2424 * mode to edge and then back to level, with RTE being masked during this.
2426 static void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2428 struct irq_pin_list
*entry
;
2429 unsigned long flags
;
2431 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2432 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2433 if (mpc_ioapic_ver(entry
->apic
) >= 0x20) {
2435 * Intr-remapping uses pin number as the virtual vector
2436 * in the RTE. Actual vector is programmed in
2437 * intr-remapping table entry. Hence for the io-apic
2438 * EOI we use the pin number.
2440 if (irq_remapped(cfg
))
2441 io_apic_eoi(entry
->apic
, entry
->pin
);
2443 io_apic_eoi(entry
->apic
, cfg
->vector
);
2445 __mask_and_edge_IO_APIC_irq(entry
);
2446 __unmask_and_level_IO_APIC_irq(entry
);
2449 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2452 static void ack_apic_level(struct irq_data
*data
)
2454 struct irq_cfg
*cfg
= data
->chip_data
;
2455 int i
, do_unmask_irq
= 0, irq
= data
->irq
;
2458 irq_complete_move(cfg
);
2459 #ifdef CONFIG_GENERIC_PENDING_IRQ
2460 /* If we are moving the irq we need to mask it */
2461 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2468 * It appears there is an erratum which affects at least version 0x11
2469 * of I/O APIC (that's the 82093AA and cores integrated into various
2470 * chipsets). Under certain conditions a level-triggered interrupt is
2471 * erroneously delivered as edge-triggered one but the respective IRR
2472 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2473 * message but it will never arrive and further interrupts are blocked
2474 * from the source. The exact reason is so far unknown, but the
2475 * phenomenon was observed when two consecutive interrupt requests
2476 * from a given source get delivered to the same CPU and the source is
2477 * temporarily disabled in between.
2479 * A workaround is to simulate an EOI message manually. We achieve it
2480 * by setting the trigger mode to edge and then to level when the edge
2481 * trigger mode gets detected in the TMR of a local APIC for a
2482 * level-triggered interrupt. We mask the source for the time of the
2483 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2484 * The idea is from Manfred Spraul. --macro
2486 * Also in the case when cpu goes offline, fixup_irqs() will forward
2487 * any unhandled interrupt on the offlined cpu to the new cpu
2488 * destination that is handling the corresponding interrupt. This
2489 * interrupt forwarding is done via IPI's. Hence, in this case also
2490 * level-triggered io-apic interrupt will be seen as an edge
2491 * interrupt in the IRR. And we can't rely on the cpu's EOI
2492 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2493 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2494 * supporting EOI register, we do an explicit EOI to clear the
2495 * remote IRR and on IO-APIC's which don't have an EOI register,
2496 * we use the above logic (mask+edge followed by unmask+level) from
2497 * Manfred Spraul to clear the remote IRR.
2500 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2503 * We must acknowledge the irq before we move it or the acknowledge will
2504 * not propagate properly.
2509 * Tail end of clearing remote IRR bit (either by delivering the EOI
2510 * message via io-apic EOI register write or simulating it using
2511 * mask+edge followed by unnask+level logic) manually when the
2512 * level triggered interrupt is seen as the edge triggered interrupt
2515 if (!(v
& (1 << (i
& 0x1f)))) {
2516 atomic_inc(&irq_mis_count
);
2518 eoi_ioapic_irq(irq
, cfg
);
2521 /* Now we can move and renable the irq */
2522 if (unlikely(do_unmask_irq
)) {
2523 /* Only migrate the irq if the ack has been received.
2525 * On rare occasions the broadcast level triggered ack gets
2526 * delayed going to ioapics, and if we reprogram the
2527 * vector while Remote IRR is still set the irq will never
2530 * To prevent this scenario we read the Remote IRR bit
2531 * of the ioapic. This has two effects.
2532 * - On any sane system the read of the ioapic will
2533 * flush writes (and acks) going to the ioapic from
2535 * - We get to see if the ACK has actually been delivered.
2537 * Based on failed experiments of reprogramming the
2538 * ioapic entry from outside of irq context starting
2539 * with masking the ioapic entry and then polling until
2540 * Remote IRR was clear before reprogramming the
2541 * ioapic I don't trust the Remote IRR bit to be
2542 * completey accurate.
2544 * However there appears to be no other way to plug
2545 * this race, so if the Remote IRR bit is not
2546 * accurate and is causing problems then it is a hardware bug
2547 * and you can go talk to the chipset vendor about it.
2549 if (!io_apic_level_ack_pending(cfg
))
2550 irq_move_masked_irq(data
);
2555 #ifdef CONFIG_INTR_REMAP
2556 static void ir_ack_apic_edge(struct irq_data
*data
)
2561 static void ir_ack_apic_level(struct irq_data
*data
)
2564 eoi_ioapic_irq(data
->irq
, data
->chip_data
);
2566 #endif /* CONFIG_INTR_REMAP */
2568 static struct irq_chip ioapic_chip __read_mostly
= {
2570 .irq_startup
= startup_ioapic_irq
,
2571 .irq_mask
= mask_ioapic_irq
,
2572 .irq_unmask
= unmask_ioapic_irq
,
2573 .irq_ack
= ack_apic_edge
,
2574 .irq_eoi
= ack_apic_level
,
2576 .irq_set_affinity
= ioapic_set_affinity
,
2578 .irq_retrigger
= ioapic_retrigger_irq
,
2581 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2582 .name
= "IR-IO-APIC",
2583 .irq_startup
= startup_ioapic_irq
,
2584 .irq_mask
= mask_ioapic_irq
,
2585 .irq_unmask
= unmask_ioapic_irq
,
2586 #ifdef CONFIG_INTR_REMAP
2587 .irq_ack
= ir_ack_apic_edge
,
2588 .irq_eoi
= ir_ack_apic_level
,
2590 .irq_set_affinity
= ir_ioapic_set_affinity
,
2593 .irq_retrigger
= ioapic_retrigger_irq
,
2596 static inline void init_IO_APIC_traps(void)
2598 struct irq_cfg
*cfg
;
2602 * NOTE! The local APIC isn't very good at handling
2603 * multiple interrupts at the same interrupt level.
2604 * As the interrupt level is determined by taking the
2605 * vector number and shifting that right by 4, we
2606 * want to spread these out a bit so that they don't
2607 * all fall in the same interrupt level.
2609 * Also, we've got to be careful not to trash gate
2610 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2612 for_each_active_irq(irq
) {
2613 cfg
= irq_get_chip_data(irq
);
2614 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2616 * Hmm.. We don't have an entry for this,
2617 * so default to an old-fashioned 8259
2618 * interrupt if we can..
2620 if (irq
< legacy_pic
->nr_legacy_irqs
)
2621 legacy_pic
->make_irq(irq
);
2623 /* Strange. Oh, well.. */
2624 irq_set_chip(irq
, &no_irq_chip
);
2630 * The local APIC irq-chip implementation:
2633 static void mask_lapic_irq(struct irq_data
*data
)
2637 v
= apic_read(APIC_LVT0
);
2638 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2641 static void unmask_lapic_irq(struct irq_data
*data
)
2645 v
= apic_read(APIC_LVT0
);
2646 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2649 static void ack_lapic_irq(struct irq_data
*data
)
2654 static struct irq_chip lapic_chip __read_mostly
= {
2655 .name
= "local-APIC",
2656 .irq_mask
= mask_lapic_irq
,
2657 .irq_unmask
= unmask_lapic_irq
,
2658 .irq_ack
= ack_lapic_irq
,
2661 static void lapic_register_intr(int irq
)
2663 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2664 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2669 * This looks a bit hackish but it's about the only one way of sending
2670 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2671 * not support the ExtINT mode, unfortunately. We need to send these
2672 * cycles as some i82489DX-based boards have glue logic that keeps the
2673 * 8259A interrupt line asserted until INTA. --macro
2675 static inline void __init
unlock_ExtINT_logic(void)
2678 struct IO_APIC_route_entry entry0
, entry1
;
2679 unsigned char save_control
, save_freq_select
;
2681 pin
= find_isa_irq_pin(8, mp_INT
);
2686 apic
= find_isa_irq_apic(8, mp_INT
);
2692 entry0
= ioapic_read_entry(apic
, pin
);
2693 clear_IO_APIC_pin(apic
, pin
);
2695 memset(&entry1
, 0, sizeof(entry1
));
2697 entry1
.dest_mode
= 0; /* physical delivery */
2698 entry1
.mask
= 0; /* unmask IRQ now */
2699 entry1
.dest
= hard_smp_processor_id();
2700 entry1
.delivery_mode
= dest_ExtINT
;
2701 entry1
.polarity
= entry0
.polarity
;
2705 ioapic_write_entry(apic
, pin
, entry1
);
2707 save_control
= CMOS_READ(RTC_CONTROL
);
2708 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2709 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2711 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2716 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2720 CMOS_WRITE(save_control
, RTC_CONTROL
);
2721 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2722 clear_IO_APIC_pin(apic
, pin
);
2724 ioapic_write_entry(apic
, pin
, entry0
);
2727 static int disable_timer_pin_1 __initdata
;
2728 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2729 static int __init
disable_timer_pin_setup(char *arg
)
2731 disable_timer_pin_1
= 1;
2734 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2736 int timer_through_8259 __initdata
;
2739 * This code may look a bit paranoid, but it's supposed to cooperate with
2740 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2741 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2742 * fanatically on his truly buggy board.
2744 * FIXME: really need to revamp this for all platforms.
2746 static inline void __init
check_timer(void)
2748 struct irq_cfg
*cfg
= irq_get_chip_data(0);
2749 int node
= cpu_to_node(0);
2750 int apic1
, pin1
, apic2
, pin2
;
2751 unsigned long flags
;
2754 local_irq_save(flags
);
2757 * get/set the timer IRQ vector:
2759 legacy_pic
->mask(0);
2760 assign_irq_vector(0, cfg
, apic
->target_cpus());
2763 * As IRQ0 is to be enabled in the 8259A, the virtual
2764 * wire has to be disabled in the local APIC. Also
2765 * timer interrupts need to be acknowledged manually in
2766 * the 8259A for the i82489DX when using the NMI
2767 * watchdog as that APIC treats NMIs as level-triggered.
2768 * The AEOI mode will finish them in the 8259A
2771 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2772 legacy_pic
->init(1);
2774 pin1
= find_isa_irq_pin(0, mp_INT
);
2775 apic1
= find_isa_irq_apic(0, mp_INT
);
2776 pin2
= ioapic_i8259
.pin
;
2777 apic2
= ioapic_i8259
.apic
;
2779 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2780 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2781 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2784 * Some BIOS writers are clueless and report the ExtINTA
2785 * I/O APIC input from the cascaded 8259A as the timer
2786 * interrupt input. So just in case, if only one pin
2787 * was found above, try it both directly and through the
2791 if (intr_remapping_enabled
)
2792 panic("BIOS bug: timer not connected to IO-APIC");
2796 } else if (pin2
== -1) {
2803 * Ok, does IRQ0 through the IOAPIC work?
2806 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2807 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2809 /* for edge trigger, setup_ioapic_irq already
2810 * leave it unmasked.
2811 * so only need to unmask if it is level-trigger
2812 * do we really have level trigger timer?
2815 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2816 if (idx
!= -1 && irq_trigger(idx
))
2819 if (timer_irq_works()) {
2820 if (disable_timer_pin_1
> 0)
2821 clear_IO_APIC_pin(0, pin1
);
2824 if (intr_remapping_enabled
)
2825 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2826 local_irq_disable();
2827 clear_IO_APIC_pin(apic1
, pin1
);
2829 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2830 "8254 timer not connected to IO-APIC\n");
2832 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2833 "(IRQ0) through the 8259A ...\n");
2834 apic_printk(APIC_QUIET
, KERN_INFO
2835 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2837 * legacy devices should be connected to IO APIC #0
2839 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2840 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2841 legacy_pic
->unmask(0);
2842 if (timer_irq_works()) {
2843 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2844 timer_through_8259
= 1;
2848 * Cleanup, just in case ...
2850 local_irq_disable();
2851 legacy_pic
->mask(0);
2852 clear_IO_APIC_pin(apic2
, pin2
);
2853 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2856 apic_printk(APIC_QUIET
, KERN_INFO
2857 "...trying to set up timer as Virtual Wire IRQ...\n");
2859 lapic_register_intr(0);
2860 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2861 legacy_pic
->unmask(0);
2863 if (timer_irq_works()) {
2864 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2867 local_irq_disable();
2868 legacy_pic
->mask(0);
2869 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2870 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2872 apic_printk(APIC_QUIET
, KERN_INFO
2873 "...trying to set up timer as ExtINT IRQ...\n");
2875 legacy_pic
->init(0);
2876 legacy_pic
->make_irq(0);
2877 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2879 unlock_ExtINT_logic();
2881 if (timer_irq_works()) {
2882 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2885 local_irq_disable();
2886 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2887 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2888 "report. Then try booting with the 'noapic' option.\n");
2890 local_irq_restore(flags
);
2894 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2895 * to devices. However there may be an I/O APIC pin available for
2896 * this interrupt regardless. The pin may be left unconnected, but
2897 * typically it will be reused as an ExtINT cascade interrupt for
2898 * the master 8259A. In the MPS case such a pin will normally be
2899 * reported as an ExtINT interrupt in the MP table. With ACPI
2900 * there is no provision for ExtINT interrupts, and in the absence
2901 * of an override it would be treated as an ordinary ISA I/O APIC
2902 * interrupt, that is edge-triggered and unmasked by default. We
2903 * used to do this, but it caused problems on some systems because
2904 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2905 * the same ExtINT cascade interrupt to drive the local APIC of the
2906 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2907 * the I/O APIC in all cases now. No actual device should request
2908 * it anyway. --macro
2910 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2912 void __init
setup_IO_APIC(void)
2916 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2918 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
2920 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2922 * Set up IO-APIC IRQ routing.
2924 x86_init
.mpparse
.setup_ioapic_ids();
2927 setup_IO_APIC_irqs();
2928 init_IO_APIC_traps();
2929 if (legacy_pic
->nr_legacy_irqs
)
2934 * Called after all the initialization is done. If we didn't find any
2935 * APIC bugs then we can allow the modify fast path
2938 static int __init
io_apic_bug_finalize(void)
2940 if (sis_apic_bug
== -1)
2945 late_initcall(io_apic_bug_finalize
);
2947 static void resume_ioapic_id(int ioapic_id
)
2949 unsigned long flags
;
2950 union IO_APIC_reg_00 reg_00
;
2953 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2954 reg_00
.raw
= io_apic_read(ioapic_id
, 0);
2955 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_id
)) {
2956 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_id
);
2957 io_apic_write(ioapic_id
, 0, reg_00
.raw
);
2959 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2962 static void ioapic_resume(void)
2966 for (ioapic_id
= nr_ioapics
- 1; ioapic_id
>= 0; ioapic_id
--)
2967 resume_ioapic_id(ioapic_id
);
2969 restore_ioapic_entries();
2972 static struct syscore_ops ioapic_syscore_ops
= {
2973 .suspend
= save_ioapic_entries
,
2974 .resume
= ioapic_resume
,
2977 static int __init
ioapic_init_ops(void)
2979 register_syscore_ops(&ioapic_syscore_ops
);
2984 device_initcall(ioapic_init_ops
);
2987 * Dynamic irq allocate and deallocation
2989 unsigned int create_irq_nr(unsigned int from
, int node
)
2991 struct irq_cfg
*cfg
;
2992 unsigned long flags
;
2993 unsigned int ret
= 0;
2996 if (from
< nr_irqs_gsi
)
2999 irq
= alloc_irq_from(from
, node
);
3002 cfg
= alloc_irq_cfg(irq
, node
);
3004 free_irq_at(irq
, NULL
);
3008 raw_spin_lock_irqsave(&vector_lock
, flags
);
3009 if (!__assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
3011 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3014 irq_set_chip_data(irq
, cfg
);
3015 irq_clear_status_flags(irq
, IRQ_NOREQUEST
);
3017 free_irq_at(irq
, cfg
);
3022 int create_irq(void)
3024 int node
= cpu_to_node(0);
3025 unsigned int irq_want
;
3028 irq_want
= nr_irqs_gsi
;
3029 irq
= create_irq_nr(irq_want
, node
);
3037 void destroy_irq(unsigned int irq
)
3039 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
3040 unsigned long flags
;
3042 irq_set_status_flags(irq
, IRQ_NOREQUEST
|IRQ_NOPROBE
);
3044 if (irq_remapped(cfg
))
3046 raw_spin_lock_irqsave(&vector_lock
, flags
);
3047 __clear_irq_vector(irq
, cfg
);
3048 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3049 free_irq_at(irq
, cfg
);
3053 * MSI message composition
3055 #ifdef CONFIG_PCI_MSI
3056 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3057 struct msi_msg
*msg
, u8 hpet_id
)
3059 struct irq_cfg
*cfg
;
3067 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3071 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3073 if (irq_remapped(cfg
)) {
3078 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3079 BUG_ON(ir_index
== -1);
3081 prepare_irte(&irte
, cfg
->vector
, dest
);
3083 /* Set source-id of interrupt request */
3085 set_msi_sid(&irte
, pdev
);
3087 set_hpet_sid(&irte
, hpet_id
);
3089 modify_irte(irq
, &irte
);
3091 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3092 msg
->data
= sub_handle
;
3093 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3095 MSI_ADDR_IR_INDEX1(ir_index
) |
3096 MSI_ADDR_IR_INDEX2(ir_index
);
3098 if (x2apic_enabled())
3099 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3100 MSI_ADDR_EXT_DEST_ID(dest
);
3102 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3106 ((apic
->irq_dest_mode
== 0) ?
3107 MSI_ADDR_DEST_MODE_PHYSICAL
:
3108 MSI_ADDR_DEST_MODE_LOGICAL
) |
3109 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3110 MSI_ADDR_REDIRECTION_CPU
:
3111 MSI_ADDR_REDIRECTION_LOWPRI
) |
3112 MSI_ADDR_DEST_ID(dest
);
3115 MSI_DATA_TRIGGER_EDGE
|
3116 MSI_DATA_LEVEL_ASSERT
|
3117 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3118 MSI_DATA_DELIVERY_FIXED
:
3119 MSI_DATA_DELIVERY_LOWPRI
) |
3120 MSI_DATA_VECTOR(cfg
->vector
);
3127 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3129 struct irq_cfg
*cfg
= data
->chip_data
;
3133 if (__ioapic_set_affinity(data
, mask
, &dest
))
3136 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3138 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3139 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3140 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3141 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3143 __write_msi_msg(data
->msi_desc
, &msg
);
3147 #ifdef CONFIG_INTR_REMAP
3149 * Migrate the MSI irq to another cpumask. This migration is
3150 * done in the process context using interrupt-remapping hardware.
3153 ir_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3156 struct irq_cfg
*cfg
= data
->chip_data
;
3157 unsigned int dest
, irq
= data
->irq
;
3160 if (get_irte(irq
, &irte
))
3163 if (__ioapic_set_affinity(data
, mask
, &dest
))
3166 irte
.vector
= cfg
->vector
;
3167 irte
.dest_id
= IRTE_DEST(dest
);
3170 * atomically update the IRTE with the new destination and vector.
3172 modify_irte(irq
, &irte
);
3175 * After this point, all the interrupts will start arriving
3176 * at the new destination. So, time to cleanup the previous
3177 * vector allocation.
3179 if (cfg
->move_in_progress
)
3180 send_cleanup_vector(cfg
);
3186 #endif /* CONFIG_SMP */
3189 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3190 * which implement the MSI or MSI-X Capability Structure.
3192 static struct irq_chip msi_chip
= {
3194 .irq_unmask
= unmask_msi_irq
,
3195 .irq_mask
= mask_msi_irq
,
3196 .irq_ack
= ack_apic_edge
,
3198 .irq_set_affinity
= msi_set_affinity
,
3200 .irq_retrigger
= ioapic_retrigger_irq
,
3203 static struct irq_chip msi_ir_chip
= {
3204 .name
= "IR-PCI-MSI",
3205 .irq_unmask
= unmask_msi_irq
,
3206 .irq_mask
= mask_msi_irq
,
3207 #ifdef CONFIG_INTR_REMAP
3208 .irq_ack
= ir_ack_apic_edge
,
3210 .irq_set_affinity
= ir_msi_set_affinity
,
3213 .irq_retrigger
= ioapic_retrigger_irq
,
3217 * Map the PCI dev to the corresponding remapping hardware unit
3218 * and allocate 'nvec' consecutive interrupt-remapping table entries
3221 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3223 struct intel_iommu
*iommu
;
3226 iommu
= map_dev_to_ir(dev
);
3229 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3233 index
= alloc_irte(iommu
, irq
, nvec
);
3236 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3243 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3245 struct irq_chip
*chip
= &msi_chip
;
3249 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3253 irq_set_msi_desc(irq
, msidesc
);
3254 write_msi_msg(irq
, &msg
);
3256 if (irq_remapped(irq_get_chip_data(irq
))) {
3257 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3258 chip
= &msi_ir_chip
;
3261 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3263 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3268 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3270 int node
, ret
, sub_handle
, index
= 0;
3271 unsigned int irq
, irq_want
;
3272 struct msi_desc
*msidesc
;
3273 struct intel_iommu
*iommu
= NULL
;
3275 /* x86 doesn't support multiple MSI yet */
3276 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3279 node
= dev_to_node(&dev
->dev
);
3280 irq_want
= nr_irqs_gsi
;
3282 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3283 irq
= create_irq_nr(irq_want
, node
);
3287 if (!intr_remapping_enabled
)
3292 * allocate the consecutive block of IRTE's
3295 index
= msi_alloc_irte(dev
, irq
, nvec
);
3301 iommu
= map_dev_to_ir(dev
);
3307 * setup the mapping between the irq and the IRTE
3308 * base index, the sub_handle pointing to the
3309 * appropriate interrupt remap table entry.
3311 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3314 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3326 void native_teardown_msi_irq(unsigned int irq
)
3331 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3334 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3337 struct irq_cfg
*cfg
= data
->chip_data
;
3338 unsigned int dest
, irq
= data
->irq
;
3341 if (__ioapic_set_affinity(data
, mask
, &dest
))
3344 dmar_msi_read(irq
, &msg
);
3346 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3347 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3348 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3349 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3350 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3352 dmar_msi_write(irq
, &msg
);
3357 #endif /* CONFIG_SMP */
3359 static struct irq_chip dmar_msi_type
= {
3361 .irq_unmask
= dmar_msi_unmask
,
3362 .irq_mask
= dmar_msi_mask
,
3363 .irq_ack
= ack_apic_edge
,
3365 .irq_set_affinity
= dmar_msi_set_affinity
,
3367 .irq_retrigger
= ioapic_retrigger_irq
,
3370 int arch_setup_dmar_msi(unsigned int irq
)
3375 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3378 dmar_msi_write(irq
, &msg
);
3379 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3385 #ifdef CONFIG_HPET_TIMER
3388 static int hpet_msi_set_affinity(struct irq_data
*data
,
3389 const struct cpumask
*mask
, bool force
)
3391 struct irq_cfg
*cfg
= data
->chip_data
;
3395 if (__ioapic_set_affinity(data
, mask
, &dest
))
3398 hpet_msi_read(data
->handler_data
, &msg
);
3400 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3401 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3402 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3403 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3405 hpet_msi_write(data
->handler_data
, &msg
);
3410 #endif /* CONFIG_SMP */
3412 static struct irq_chip ir_hpet_msi_type
= {
3413 .name
= "IR-HPET_MSI",
3414 .irq_unmask
= hpet_msi_unmask
,
3415 .irq_mask
= hpet_msi_mask
,
3416 #ifdef CONFIG_INTR_REMAP
3417 .irq_ack
= ir_ack_apic_edge
,
3419 .irq_set_affinity
= ir_msi_set_affinity
,
3422 .irq_retrigger
= ioapic_retrigger_irq
,
3425 static struct irq_chip hpet_msi_type
= {
3427 .irq_unmask
= hpet_msi_unmask
,
3428 .irq_mask
= hpet_msi_mask
,
3429 .irq_ack
= ack_apic_edge
,
3431 .irq_set_affinity
= hpet_msi_set_affinity
,
3433 .irq_retrigger
= ioapic_retrigger_irq
,
3436 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3438 struct irq_chip
*chip
= &hpet_msi_type
;
3442 if (intr_remapping_enabled
) {
3443 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3449 index
= alloc_irte(iommu
, irq
, 1);
3454 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3458 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3459 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3460 if (irq_remapped(irq_get_chip_data(irq
)))
3461 chip
= &ir_hpet_msi_type
;
3463 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3468 #endif /* CONFIG_PCI_MSI */
3470 * Hypertransport interrupt support
3472 #ifdef CONFIG_HT_IRQ
3476 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3478 struct ht_irq_msg msg
;
3479 fetch_ht_irq_msg(irq
, &msg
);
3481 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3482 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3484 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3485 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3487 write_ht_irq_msg(irq
, &msg
);
3491 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3493 struct irq_cfg
*cfg
= data
->chip_data
;
3496 if (__ioapic_set_affinity(data
, mask
, &dest
))
3499 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3505 static struct irq_chip ht_irq_chip
= {
3507 .irq_mask
= mask_ht_irq
,
3508 .irq_unmask
= unmask_ht_irq
,
3509 .irq_ack
= ack_apic_edge
,
3511 .irq_set_affinity
= ht_set_affinity
,
3513 .irq_retrigger
= ioapic_retrigger_irq
,
3516 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3518 struct irq_cfg
*cfg
;
3525 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3527 struct ht_irq_msg msg
;
3530 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3531 apic
->target_cpus());
3533 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3537 HT_IRQ_LOW_DEST_ID(dest
) |
3538 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3539 ((apic
->irq_dest_mode
== 0) ?
3540 HT_IRQ_LOW_DM_PHYSICAL
:
3541 HT_IRQ_LOW_DM_LOGICAL
) |
3542 HT_IRQ_LOW_RQEOI_EDGE
|
3543 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3544 HT_IRQ_LOW_MT_FIXED
:
3545 HT_IRQ_LOW_MT_ARBITRATED
) |
3546 HT_IRQ_LOW_IRQ_MASKED
;
3548 write_ht_irq_msg(irq
, &msg
);
3550 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3551 handle_edge_irq
, "edge");
3553 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3557 #endif /* CONFIG_HT_IRQ */
3560 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3562 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3567 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3569 setup_ioapic_irq(attr
->ioapic
, attr
->ioapic_pin
, irq
, cfg
,
3570 attr
->trigger
, attr
->polarity
);
3574 int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
3575 struct io_apic_irq_attr
*attr
)
3577 unsigned int id
= attr
->ioapic
, pin
= attr
->ioapic_pin
;
3580 /* Avoid redundant programming */
3581 if (test_bit(pin
, ioapics
[id
].pin_programmed
)) {
3582 pr_debug("Pin %d-%d already programmed\n",
3583 mpc_ioapic_id(id
), pin
);
3586 ret
= io_apic_setup_irq_pin(irq
, node
, attr
);
3588 set_bit(pin
, ioapics
[id
].pin_programmed
);
3592 static int __init
io_apic_get_redir_entries(int ioapic
)
3594 union IO_APIC_reg_01 reg_01
;
3595 unsigned long flags
;
3597 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3598 reg_01
.raw
= io_apic_read(ioapic
, 1);
3599 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3601 /* The register returns the maximum index redir index
3602 * supported, which is one less than the total number of redir
3605 return reg_01
.bits
.entries
+ 1;
3608 static void __init
probe_nr_irqs_gsi(void)
3612 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3613 if (nr
> nr_irqs_gsi
)
3616 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3619 int get_nr_irqs_gsi(void)
3624 #ifdef CONFIG_SPARSE_IRQ
3625 int __init
arch_probe_nr_irqs(void)
3629 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3630 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3632 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3633 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3635 * for MSI and HT dyn irq
3637 nr
+= nr_irqs_gsi
* 16;
3642 return NR_IRQS_LEGACY
;
3646 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3647 struct io_apic_irq_attr
*irq_attr
)
3651 if (!IO_APIC_IRQ(irq
)) {
3652 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3657 node
= dev
? dev_to_node(dev
) : cpu_to_node(0);
3659 return io_apic_setup_irq_pin_once(irq
, node
, irq_attr
);
3662 #ifdef CONFIG_X86_32
3663 static int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3665 union IO_APIC_reg_00 reg_00
;
3666 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3668 unsigned long flags
;
3672 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3673 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3674 * supports up to 16 on one shared APIC bus.
3676 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3677 * advantage of new APIC bus architecture.
3680 if (physids_empty(apic_id_map
))
3681 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3683 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3684 reg_00
.raw
= io_apic_read(ioapic
, 0);
3685 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3687 if (apic_id
>= get_physical_broadcast()) {
3688 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3689 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3690 apic_id
= reg_00
.bits
.ID
;
3694 * Every APIC in a system must have a unique ID or we get lots of nice
3695 * 'stuck on smp_invalidate_needed IPI wait' messages.
3697 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3699 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3700 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3704 if (i
== get_physical_broadcast())
3705 panic("Max apic_id exceeded!\n");
3707 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3708 "trying %d\n", ioapic
, apic_id
, i
);
3713 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3714 physids_or(apic_id_map
, apic_id_map
, tmp
);
3716 if (reg_00
.bits
.ID
!= apic_id
) {
3717 reg_00
.bits
.ID
= apic_id
;
3719 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3720 io_apic_write(ioapic
, 0, reg_00
.raw
);
3721 reg_00
.raw
= io_apic_read(ioapic
, 0);
3722 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3725 if (reg_00
.bits
.ID
!= apic_id
) {
3726 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3731 apic_printk(APIC_VERBOSE
, KERN_INFO
3732 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3737 static u8 __init
io_apic_unique_id(u8 id
)
3739 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3740 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3741 return io_apic_get_unique_id(nr_ioapics
, id
);
3746 static u8 __init
io_apic_unique_id(u8 id
)
3749 DECLARE_BITMAP(used
, 256);
3751 bitmap_zero(used
, 256);
3752 for (i
= 0; i
< nr_ioapics
; i
++) {
3753 __set_bit(mpc_ioapic_id(i
), used
);
3755 if (!test_bit(id
, used
))
3757 return find_first_zero_bit(used
, 256);
3761 static int __init
io_apic_get_version(int ioapic
)
3763 union IO_APIC_reg_01 reg_01
;
3764 unsigned long flags
;
3766 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3767 reg_01
.raw
= io_apic_read(ioapic
, 1);
3768 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3770 return reg_01
.bits
.version
;
3773 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3775 int ioapic
, pin
, idx
;
3777 if (skip_ioapic_setup
)
3780 ioapic
= mp_find_ioapic(gsi
);
3784 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3788 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3792 *trigger
= irq_trigger(idx
);
3793 *polarity
= irq_polarity(idx
);
3798 * This function currently is only a helper for the i386 smp boot process where
3799 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3800 * so mask in all cases should simply be apic->target_cpus()
3803 void __init
setup_ioapic_dest(void)
3805 int pin
, ioapic
, irq
, irq_entry
;
3806 const struct cpumask
*mask
;
3807 struct irq_data
*idata
;
3809 if (skip_ioapic_setup
== 1)
3812 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
3813 for (pin
= 0; pin
< ioapics
[ioapic
].nr_registers
; pin
++) {
3814 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3815 if (irq_entry
== -1)
3817 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3819 if ((ioapic
> 0) && (irq
> 16))
3822 idata
= irq_get_irq_data(irq
);
3825 * Honour affinities which have been set in early boot
3827 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3828 mask
= idata
->affinity
;
3830 mask
= apic
->target_cpus();
3832 if (intr_remapping_enabled
)
3833 ir_ioapic_set_affinity(idata
, mask
, false);
3835 ioapic_set_affinity(idata
, mask
, false);
3841 #define IOAPIC_RESOURCE_NAME_SIZE 11
3843 static struct resource
*ioapic_resources
;
3845 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
3848 struct resource
*res
;
3852 if (nr_ioapics
<= 0)
3855 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3858 mem
= alloc_bootmem(n
);
3861 mem
+= sizeof(struct resource
) * nr_ioapics
;
3863 for (i
= 0; i
< nr_ioapics
; i
++) {
3865 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3866 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3867 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3870 ioapic_resources
= res
;
3875 void __init
ioapic_and_gsi_init(void)
3877 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3878 struct resource
*ioapic_res
;
3881 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
3882 for (i
= 0; i
< nr_ioapics
; i
++) {
3883 if (smp_found_config
) {
3884 ioapic_phys
= mpc_ioapic_addr(i
);
3885 #ifdef CONFIG_X86_32
3888 "WARNING: bogus zero IO-APIC "
3889 "address found in MPTABLE, "
3890 "disabling IO/APIC support!\n");
3891 smp_found_config
= 0;
3892 skip_ioapic_setup
= 1;
3893 goto fake_ioapic_page
;
3897 #ifdef CONFIG_X86_32
3900 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3901 ioapic_phys
= __pa(ioapic_phys
);
3903 set_fixmap_nocache(idx
, ioapic_phys
);
3904 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3905 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3909 ioapic_res
->start
= ioapic_phys
;
3910 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3914 probe_nr_irqs_gsi();
3917 void __init
ioapic_insert_resources(void)
3920 struct resource
*r
= ioapic_resources
;
3925 "IO APIC resources couldn't be allocated.\n");
3929 for (i
= 0; i
< nr_ioapics
; i
++) {
3930 insert_resource(&iomem_resource
, r
);
3935 int mp_find_ioapic(u32 gsi
)
3939 if (nr_ioapics
== 0)
3942 /* Find the IOAPIC that manages this GSI. */
3943 for (i
= 0; i
< nr_ioapics
; i
++) {
3944 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
3945 if ((gsi
>= gsi_cfg
->gsi_base
)
3946 && (gsi
<= gsi_cfg
->gsi_end
))
3950 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3954 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3956 struct mp_ioapic_gsi
*gsi_cfg
;
3958 if (WARN_ON(ioapic
== -1))
3961 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3962 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
3965 return gsi
- gsi_cfg
->gsi_base
;
3968 static __init
int bad_ioapic(unsigned long address
)
3970 if (nr_ioapics
>= MAX_IO_APICS
) {
3971 printk(KERN_WARNING
"WARNING: Max # of I/O APICs (%d) exceeded "
3972 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
3976 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
3977 " found in table, skipping!\n");
3983 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
3987 struct mp_ioapic_gsi
*gsi_cfg
;
3989 if (bad_ioapic(address
))
3994 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
3995 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
3996 ioapics
[idx
].mp_config
.apicaddr
= address
;
3998 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
3999 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(id
);
4000 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
4003 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4004 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4006 entries
= io_apic_get_redir_entries(idx
);
4007 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
4008 gsi_cfg
->gsi_base
= gsi_base
;
4009 gsi_cfg
->gsi_end
= gsi_base
+ entries
- 1;
4012 * The number of IO-APIC IRQ registers (== #pins):
4014 ioapics
[idx
].nr_registers
= entries
;
4016 if (gsi_cfg
->gsi_end
>= gsi_top
)
4017 gsi_top
= gsi_cfg
->gsi_end
+ 1;
4019 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4020 "GSI %d-%d\n", idx
, mpc_ioapic_id(idx
),
4021 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
4022 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
4027 /* Enable IOAPIC early just for system timer */
4028 void __init
pre_init_apic_IRQ0(void)
4030 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
4032 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4034 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
4035 &phys_cpu_present_map
);
4039 io_apic_setup_irq_pin(0, 0, &attr
);
4040 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,